i

Tailored Al2O3/4H-SiC interface

using ion implantation

Yutong Zeng

Master of Science Thesis

Kungliga Tekniska Högskolan KTH

School of Information and Communication Technology

Department of Integrated Circuits and Devices

Stockholm, November 2011

TRITA-ICT-EX-2011:280

ii

Tailored Al2O3/4H-SiC interface using ion

implantation

Yutong Zeng

Master of Science Thesis

TRITA-ICT-EX-2011:280

KTH Royal Institute of Technology

School of Information and Communication Technology

Department of Integrated Circuits and Devices

Stockholm, Sweden

November, 2011

iii

Abstract

The effects of ion implantation of Al2O3 interface to 4H-SiC epitaxial n- and p-type

layers are presented. Different fluencies of carbon and nitrogen ions are used, as well

as different annealing processes, with the aim to study the effects of implanted ions at

the Al2O3/SiC interface. Capacitance-Voltage (C-V) behavior for fabricated MOS

capacitors is studied before and after implantation to determine the effect of the

implantation. Terman‟s method was employed to extract the density of interface traps

(Dit) present at the Al2O3/SiC interface. Effective oxide charges density (Neff), present

inside the Al2O3, was also evaluated by comparing the theoretical (ideal) C-V curve

with the experimental C-V curves.

It is generally known, and also proved by this study, that Al2O3 on n-type 4H-SiC

shows significantly higher effective oxide charges density (Neff) and density of

interface traps (Dit=3-4×1012

eV-1

cm-2

) compared to n-type SiO2/SiC MOS capacitors.

However, the analysis of the collected data from N and C implanted n-type Al2O3/SiC

samples show Dit values around 2-9×1011

eV-1

cm-2

, i.e., an effective reduction has

been achieved by the ion implantation. The values of Neff for N ion implanted n-type

Al2O3/SiC is as high as 1013

cm-2

in some cases, but C implanted n-type Al2O3/SiC

sample shows exceptionally low Neff =1.8×1011

cm-2

, which is comparable to

SiO2/SiC based MOS capacitor. This result suggest that using C ion implantation

before the formation of the oxide layer could be a promising approach to improving

both oxide and interface properties of n-type 4H-SiC MOS capacitors.

iv

Acknowledgment

It is a pleasure to thank those who made this thesis possible. I am heartily thankful to

my examiner, Professor Anders Hallén, whose encouragement, guidance and support

from the initial to the final level enabled me to develop an understanding of this thesis

project.

Also I would like to thank my supervisor, Muhammad Usman for his supporting and

patient guidance and valuable advice during this thesis work.

Further I would like to thank Assoc. Professor B Gunnar Malm for allowing me to

work in the laboratory. I am also thankful to my friend Sethu Saveda Suvanam for his

useful tips for the Matlab program.

At last, I would like to thank my parents for their continuous supports during my

studies in Sweden.

v

Contents

Abstract ............................................................................................................................................ iii

Acknowledgment ............................................................................................................................. iv

1. Introduction ............................................................................................................................... - 1 -

2. Physics of MOS capacitor ......................................................................................................... - 2 -

2.1 Basic structure and principle of MOS capacitor ............................................................. - 2 -

2.2 Defects in MOS capacitor ............................................................................................... - 4 -

3. Experimental procedures and samples ...................................................................................... - 7 -

3.1 Sample preparation procedures ....................................................................................... - 7 -

3.1.1 Ion implantation ................................................................................................... - 8 -

3.1.2 Substrate cleaning ................................................................................................ - 8 -

3.1.3 Oxide deposition (ALD)....................................................................................... - 9 -

3.1.4 Annealing ............................................................................................................. - 9 -

3.1.5 Contact formation ...............................................................................................- 10 -

3.2 Summarized table of detailed information of all the samples used for this study .........- 10 -

4. Electrical analysis---Interface traps charge and effective oxide charge measurement ............- 12 -

4.1 Ideal MOS capacitance Curves .....................................................................................- 12 -

4.2 Terman‟s method to determine interface traps ..............................................................- 14 -

4.3 Calculation of Flat-band voltage and effective oxide charges. .....................................- 17 -

4.3.1 Work function difference ....................................................................................- 17 -

4.3.2 Flat-band voltage ................................................................................................- 18 -

4.3.3 Calculation of Effective Oxide Charges Qeff and number density Neff. ..............- 19 -

4.4 Probe station and CV measurement set-up....................................................................- 20 -

4.4.1 Experimental set-up ...........................................................................................- 20 -

5. Experimental results ................................................................................................................- 24 -

5.1 Introduction ...................................................................................................................- 24 -

5.2 Electrical analysis of n-type Al2O3/SiC MOS capacitors (Reference samples) ............- 25 -

5.3 Electrical analysis of n-type Al2O3/SiC MOS capacitors (N- or C-implanted samples)- 29

-

5.4 Electrical analysis of p-type Al2O3/SiC MOS capacitors (Reference samples) ............- 33 -

5.5 Electrical analysis of p-type Al2O3/SiC MOS capacitors (N- implanted samples) .......- 35 -

6. Discussion ...............................................................................................................................- 37 -

7. Conclusion ..............................................................................................................................- 39 -

Reference ....................................................................................................................................- 40 -

Appendix .....................................................................................................................................- 42 -

- 1 -

1. Introduction

Silicon carbide (SiC) is considered as the “third generation” semiconductor material.

Compared to the “first generation” semiconductor material Si and the “second

generation” semiconductor material GaAs, SiC has superior electronic properties

under high temperature, high frequency, high power and high radiation conditions [1].

Moreover, SiC also has the ability to grow natural oxide (SiO2) on the surface. This

property enables us to utilize the well-developed process technology of Si to deal with

SiC. These superior advantages make SiC rapidly emerging as the technology of

choice for next-generation power electronics.

However, in the current state of the art processes for SiC, there are several problems

that should be solved to improve SiC MOS devices and the use of SiO2 as a

passivation layer on SiC power devices. For instance, the surface mobility is strongly

degraded by the high SiO2/SiC interface state density, which is about one to two

orders of magnitude higher than the one of traditional Si-based MOS devices [2], and

furthermore, involves the states near the conduction band edge [3, 4]. Therefore, one

of the critical issues is to reduce the interface state density (Dit) at the SiO2/SiC

interface thus to improve channel mobility and the performance of SiC-based MOS

devices. Previous research on Dit reduction involves for instance to use wet ambient

during the oxidation and/or in the post oxidation annealing (POA) at 900-950 oC [4].

Alternatively, interface state density can be reduced by annealing of pre-grown oxide,

or direct oxide growth in NO or N2O environment at 1000 oC [5]. Recently, some

investigations proposed the use of nitrogen ion implantation before the oxidation of

SiC in order to reduce the interface state density [4]. Another problem than low

channel mobility is the low reliability when using silicon dioxide (SiO2) as dielectric

for SiC devices because SiC-based devices are supposed to operate at high fields

which will cause reliability problems and high leakage current. This problem is not

only related to the poor quality of the dielectric/SiC interface, but is also related to the

relatively low dielectric constant of SiO2, One solution could be to employ high-k

dielectrics such as Al2O3, AIN, or HfO2 instead of SiO2 [6].

This thesis will mainly focus on electrical properties of 4H-SiC MOS devices using

Al2O3 as dielectric and using ion implantation to affect the interface quality.

- 2 -

2. Physics of MOS capacitor

2.1 Basic structure and principle of MOS capacitor

A Metal-Oxide-Semiconductor structure is illustrated in Fig.1 [7]. As it is shown, a

crystal layer of semiconductor substrate, say SiC, is followed by an oxide layer with

thickness d as insulator, and a layer of contact metal as gate. This structure forms a

MOS capacitor.

Figure 1. MOS capacitor structure [7]

- 3 -

Figure 2. Charges in a p-type Metal-Oxide-Semiconductor structure under

accumulation, depletion and inversion conditions [8].

There are typically three different bias modes of a MOS capacitor shown in the Fig.2

[8].Taking a p-type substrate MOS capacitor as an example, accumulation occurs

typically when the negative gate voltage that is less than the flat-band voltage applied.

In this case, the negative charge on the gate attracts majority carriers (holes) from the

substrate to the oxide-semiconductor interface. This is so-called accumulation.

Depletion occurs when a more positive voltage is applied; the positive charge on the

gate pushes the mobile holes into the substrate. Therefore, the semiconductor is

depleted of majority carriers (holes) at the interface and negative ionized acceptor

ions, are left in the space charge region. The voltage separating the accumulation and

depletion regime is referred to as the flat-band voltage, VFB. For ideal MOS capacitors

it is equal to zero but if there is a fixed charge in the oxide and/or at the oxide-silicon

interface, the flat-band voltage is not zero. The expression of deciding flat-band

voltage will be discussed in the following chapters. There exists a negatively charged

inversion layer at the oxide-semiconductor interface in addition to the depletion layer.

This so called inversion layer is due to the minority carriers (electrons) that are

attracted to the interface by the positive gate voltage. Similar results can be obtained

for the n-type semiconductor. However, the polarity of the voltage should be changed

for the n-type semiconductor [7, 8].

- 4 -

2.2 Defects in MOS capacitor

Interface traps and oxide charges will, however, exist in a real MOS capacitor and

affect the ideal MOS characteristics just described. These traps and charges have been

studied and classified into four types, as shown in Fig.3 for the most common MOS

capacitor [7].

Figure 3. Cross section of SiO2/Si-based MOS capacitor with the different classified charges [7].

(1) Interface traps density Dit and trapped charges Qit, which are located at the SiO2/Si

interface. These states have different energies within the silicon forbidden band-gap

and can exchange charges with silicon conduction or valence band in a short time; Qit

is also determined by the occupancy of the Fermi level and its amount is bias and

temperature dependent. Interface traps can possibly be produced by excess silicon

(trivalent silicon), broken Si-H bonds, excess oxygen and impurities for Si MOS;

however the interface traps in SiC MOS capacitor are caused by some other reasons

which will be further discussed in the following chapter.

(2) Fixed oxide charges Qf, which are located at or near the interface and are

immobile under an applied electric field.

(3) Oxide trapped charges Qot, which can be created, for example, by X-ray radiation,

or hot electron injection; these traps are distributed inside the oxide layer.

(4) Mobile ionic charges Qm, such as sodium ions, which are mobile within the oxide

under bias-temperature stress conditions [7].

- 5 -

In order to find a way to reduce interface state density in SiC MOS capacitor, one

should first find the reasons why do these interface traps exist.

It is generally accepted that the main reason why interface traps exist in Si MOS are

because the broken Si-H bonds produced by the lattice mismatch between the

substrate layer and oxide layer. However, for SiC MOS this is not necessarily the

reason which causes a high interface state density. There are mainly three reasons:

(1) The existence of carbon causes a high interface state density at the SiO2/SiC

interface. During the oxidation and formation of SiO2, the carbon at the SiC surface

will form graphite-like carbon clusters which will remain on the interface as interface

traps. Moreover, the carbon can be oxidized into CO that could form

many unsaturated carbon atoms on the oxide surface that also produce interface traps

[9].

(2) There are oxide trapped charges which are so called slow interface states, located

within about 2nm from the SiO2/SiC interface, which makes a large contribution to

the interface states [10].

(3) The SiO2 layer, which is incompletely oxidized silicon, would produce interface

traps. Moreover, further studies of this are needed.

According to these three reasons, the only effective way to reduce interface traps is to

reduce the residual carbon element.

Because of different factors that affect the SiO2/SiC interface quality other than those

which affect on SiO2/Si interface, improved annealing process based on the one

employed for Si and ion implantation process has been proposed.

(1) ROA: Re-oxidation annealing is a second oxidation process after the typical

oxidation process with the same or lower temperature. Different than the typical

oxidation process, ROA includes two oxidation processes. First one is to oxidize the

incompletely oxidized carbon element. The second one is to continue oxidizing SiC at

the SiO2/SiC interface. In order to improve the quality of the interface, the aim of

ROA is to oxidize carbon element not SiC, is it reported that anneal with the

temperature around 900 - 950 oC can achieve this aim that only carbon element will

be oxidized [11].

(2) Annealing in NO, N2O or NO2 environment: In NO, N2O or NO2 environment, on

one hand, the Nitrogen atoms can go into the interface to form N-Si bond with the

unsaturated Si bond. On the other hand, Oxide atoms can go into interface to oxidize

C atoms thus to effectively reduce carbon cluster which produce interface traps [12,

13].

(3) Ion implantation process on the SiO2/SiC interface: Recently, many research

groups report that pre-oxidation treatment by N implantation produces a strong

reduction of Dit near the conduction band edge associated to an increase of the

interface traps near the valence band edge. The strong reduction of Dit near the

- 6 -

conduction band can be achieved only if a high dose of nitrogen ions remain at the

oxide-SiC interface. Drawback of such N implantation process is the increase of fixed

positive charges in the oxide which cause an unwanted shift of the flat-band voltage

(VFB) [4]. Based on this improved treatment, a further reduction of the interface states

should be expected by combining N+ implantation with improved annealing

techniques in the manufacturing process of a MOS structure.

(4) Using different dielectrics as gate material instead of SiO2: The low reliability

when using silicon dioxide (SiO2) as dielectric is another problem for SiC based

devices because SiC-based devices are supposed to operate at high field which will

cause reliability problems and high leakage current. This problem is also related to the

poor quality of the dielectric/SiC interface, but is also related to the relatively low

dielectric constant of SiO2, one solution could be employ high-k dielectric such as

Al2O3, AIN, or HfO2 instead of SiO2 by using Atomic layer deposition (ALD) [6].

- 7 -

3. Experimental procedures and samples

3.1 Sample preparation procedures

In this study we fabricated 4H-SiC MOS capacitor using Al2O3 as dielectric deposited

on 4H-SiC epitaxial layers with different doses of implanted nitrogen or carbon ions.

Also four Al2O3/SiC MOS capacitors without implantation were fabricated as

reference samples.

The MOS capacitors were fabricated on 4H-SiC wafers from SiCrystal AG (4o

off-axis, with an epitaxial layer of thickness 8-10 μm, and nitrogen doping

concentration of 5x1015

cm-3

). The wafers were cut into nine samples which were

processed as shown in Table 3.1. The main steps of fabricating SiC MOS capacitor are

shown in Fig.3.1.

Figure 3.1. SiC MOS capacitor fabrication process

First these wafers were cleaned by chemical reagents, and then three n-type samples

were implanted by nitrogen ions at room temperature with energy of 2 keV by

different doses, while one n-type sample was implanted by carbon ions with the same

energy. There were two p-type samples implanted at room temperature by nitrogen

ions at 2 keV. Then Al2O3 oxide layers with thickness about 56 nm were deposited by

atomic layer deposition (ALD). Afterwards, the samples were annealed in an Ar

environment at 950 oC for 1 hour. All the samples were fabricated by using Al2O3 as

oxide. Nickel silicide was developed for the Ohmic contact on the back and aluminum

was used for front side contact.

- 8 -

3.1.1 Ion implantation

Previous research shows that only high concentration of nitrogen remained at the

SiO2/SiC interface is effective in reducing interface state density [4]. Based on the

previous results we expect to introduce high concentration of N at the Al2O3/SiC

interface. Before implantation, we used the „SRIM‟ simulation software to calculate

the energy and doses of the implantation that we expect to employ in this study. The

Stopping and Range of Ions in Matter (SRIM) is a collection of software packages

which calculate many features of the transport of ions in matter. The as-implanted N

distribution was computed by SRIM. Energy and doses were chosen after simulations.

We implanted the five samples illustrated in Fig. 3.2 and all the sample information is

summarized in Table 3.1. It is worth to mention that we also implanted C ions to study

the damages caused by C ions at Al2O3/SiC interface. Surprisingly, the sample

implanted by C ions shows best CV characteristics than all the other investigation

samples. The results will be discussed in the following chapters.

Figure 3.2. Ion implantation process in this study. N or C ions were implanted into at

the interface of Al2O3/SiC.

3.1.2 Substrate cleaning

First these SiC wafers were cleaned by de-ionized water and then by chemical

reagents H2SO4:H2O2 for 5 minutes and HF: H2O (1:4) for 2 minutes at 110 oC. This

substrate cleaning could remove contamination and natural oxide on the substrate

surface but does not restore crystal defects.

- 9 -

3.1.3 Oxide deposition (ALD)

Atomic layer deposition (ALD) process was employed in this study for Al2O3

deposition on SiC by using trimethyl aluminum (TMA) and O3 at 250 oC illustrated in

Fig 3.3. Before oxidation process, all the samples had been deposited so-called

precursors uniformly on the surface. These precursors react with a surface

one-at-a-time in a sequential manner. By exposing the precursors to the growth

surface repeatedly, a thin film is deposited. To grow an oxide layer, reaction cycles are

repeated as many as required for the desired film thickness. In this study, A 56 nm

Al2O3 layer was deposited on SiC epitaxial samples by this process.

Figure 3.3. 56 nm Al2O3 layer deposited using atomic layer deposition (ALD) process in this study.

3.1.4 Annealing

Annealing is a process in which a material is treated in heat to reduce defects and get

the material back into a previous stable form. During this annealing process the

sample is heated to a certain temperature where it maintained for a specified time and

then cooled down to room temperature. It is used to relieve internal stresses of the

crystal and recover the damage caused by ion implantation.

Except two reference samples served for a comparison, all the implanted samples

were annealed in Ar atmosphere at 950 oC for 1 hour showed in Table 3.1.

- 10 -

3.1.5 Contact formation

The top circular contacts were patterned using 100 nm thick Al with circular gate

geometry of 50, 100, 150, 200, 250, 300, 350, 400, 500 μm in diameter. The backside

contact was deposited with nickel silicide.

Figure 3.4. Contact deposition process of SiC-based MOS capacitor.

3.2 Summarized table of detailed information of all the

samples used for this study

As this table shows that there are nine samples used in this study. Four of these

samples were implanted with nitrogen ions and one sample was implanted with

carbon ions as a comparison and then deposited with Al2O3 as a dielectric. We

prepared both n-type and p-type samples with two different implantation doses of

5x1013

cm-3

and 5x1014

cm-3

to study the effect of ion implantation at different doses

to these samples. There are four samples without ion implantation as reference

samples in the lower part of this table. Two of them are n-type with and without

annealing and the remaining two samples are p-type with the same treatment.

- 11 -

Figure 3.5. Photo of investigated samples. The samples are about 1 cm2. The dark area

without metallization is for optical measurements.

Type of epi Implanted ionsImplantation dosesDielectric Annealing Develop contacts Name(Substr. n-type) (Energy 2 keV) (time:1 hour)(Front/Back side)

Nitrogen 5×1013 Al2O3 Ar 950 °C Al/Ni 1N3

n-type Nitrogen 5×1014 Al2O3 Ar 950 °C Al/Ni 2N4

Carbon 5×1013 Al2O3 Ar 950 °C Al/Ni 3N3

Nitrogen 5×1013 Al2O3 Ar 950 °C Al/Ni 1P3

p-type Nitrogen 5×1014 Al2O3 Ar 950 °C Al/Ni 2P4

Reference Dielectric Annealing Develop contacts Name(time:1 hour)(Front/Back side)

Al2O3 Ar 950 °C Al/Ni 1RN

n-typeAl2O3 Not annealed Al/Ni 2RN

Al2O3 Ar 950 °C Al/Ni 1RP

p-typeAl2O3 Not annealed Al/Ni 2RP

Implantation

non-implanted

non-implanted

non-implanted

non-implanted

Table 3.1. Summary of the specific information of all the samples used in this study.

- 12 -

4. Electrical analysis---Interface traps charge and

effective oxide charge measurement

4.1 Ideal MOS capacitance Curves

In order to derive the relations between the capacitance and voltage of the ideal MOS

structure, one should first determine the relations between space-charge density Qs

and surface potential ѱs. Fig.4.1 showed a typical variation of the space-charge

density Qs (C/cm2) as a function of the surface potential ѱs for a p-type silicon with

NA=4×1015

cm-3

at room temperature [7]. Accumulation region occurs when ѱs is

negative, Qs is positive. The flat-band condition happens when ѱs=0 and Qs=0. For 2

ѱB> ѱs>0, Qs is negative and represents the depletion and weak-inversion regions.

Strong inversion happens when ѱs>2 ѱB.

Figure 4.1. Space-charge density Qs versus the surface potential Ψs for a

p-type silicon with NA=4x1015

cm-3

.at room temperature [7].

- 13 -

As long as the relation between Qs and ѱs is known, the C-V relation can be derived

as following. The applied voltage is applied partly on the insulator and partly across

the semiconductor, as shown in equation (1)

)1(siVV

Vi is the voltage applied across the insulator given by equation (2)

)2(

||

ox

s

i

si

C

QdQV

The total capacitance is a combination of the insulator capacitance Cox and the

semiconductor Cs expressed as follows:

)3(

dC i

ox

The capacitance of the semiconductor is obtained by differentiating the total static

charge in equation (6) with respect to the surface potential of the semiconductor.

By combining equations (1) to (6), the ideal CV curves in different frequency cases

can be achieved as shown in Fig.4.2 [7].

)5(112

21

2

2

kT

qe

N

n

kT

qekTNEQ skT

q

A

iskT

q

ASisSis

ss

)6()(

s

s

sd

QdC

)4(sox

sox

CC

CCC

- 14 -

Figure 4.2. Ideal MOS capacitor CV curve: (a) Low frequency. (b) Intermediate

frequency. (c) High frequency. (d) High frequency with fast sweep (deep

depletion). Flat-band voltage of V = 0 is assumed [7].

4.2 Terman’s method to determine interface traps

Basically, there are three methods [14] for measurement of interface traps from

recording the C-V relation:

1) High frequency method;

2) Low frequency method;

3) High-Low-Frequency capacitance methods;

High frequency method was used to evaluate the density of interface traps in this

study. High frequency method was firstly developed by Terman in 1962 [15];

therefore it is also referred to as Terman‟s method. In this method, a sufficiently high

frequency, which is usually 100 KHz - 1 MHz, is used in C-V measurement. The

interface traps are assumed to respond slower than AC probe frequency. The AC

signal is typically 15 mV rms or less, and a common signal frequency is 1 MHz [16].

However, interface traps do respond to the slowly varying DC gate voltage. Because

the measurement frequency is comparably high, the generation-recombination process

will not be able to supply or eliminate minority carriers in response to the applied AC

signal. The minority carriers in the inversion layer will remain fixed at its DC value

[16]. It is this very reason that causes the High-frequency C-V curve to „stretch out‟,

which shows a non-parallel shift compared to the ideal C-V curve along the gate

- 15 -

voltage axis, illustrated in Fig.4.3 [14].

Figure 4.3. Effect of Dit on theoretical high-frequency C-V curves (Dit=0) and

experimental C-V curves ((Dit≠0)

Different interface traps distributions through the semiconductor band gap produces

different kinds of distorted C-V curve. Uniformly distributed interface traps produce a

fairly smooth but distorted C-V curve. However, Interface traps with peaked

distributions produce more abrupt distortions in the C-V curve. This explains why we

obtained some abrupt distortions in the C-V curve in some of our experimental results

which are not considered as good quality. The relevant equivalent circuit of the

High-frequency of MOS capacitor is shown in Fig.4.4 [7].

Figure 4.4. (c) Equivalent circuits of MOS capacitor in low-frequency (d) and

high-frequency [7].

The equivalent circuit of MOS capacitor in high-frequency does not contain Cit. The

- 16 -

measured capacitance CHF can determine Cs directly by the equation CHF = Cox × Cs/

(Cox+ Cs). The variation of Cs with surface potential ѱs is known for an ideal device.

Thus a relationship between ѱs and VG can be constructed as follow: First, find a

value of ѱs from the ideal MOS capacitor C-V curve, this ѱs corresponded to a given

CHF. Then find a value of VG from the experimental curve for the same CHF. As a

result, one point of a ѱs versus VG curve is constructed. And repeat for other points to

obtain the ѱs--VG relationship shown in Fig.4.5 [14]. The effect of the interface traps

makes the curve stretch out in the voltage direction due to the extra charge which fill

the traps, so more applied voltage is needed to achieve the same surface potential (ѱs)

or band bending [7]. This stretched out ѱs-VG curve contains the interface trap

information which can determine the interface trap density by [14]

22)(

q

C

d

dV

q

CD s

s

Goxit

(7)

Figure 4.5. Influence of interface traps on high-frequency ѱs--VG curves [7].

Figure 4.6. Terman‟s method to determine interface traps density (Dit) [17].

- 17 -

4.3 Calculation of Flat-band voltage and effective oxide

charges.

In general, interface traps cause a non-parallel shift of the C-V curve, leading to the

C-V “stretch out” [14]. Fixed oxide charges cause a parallel voltage shift along the x-

axis (gate voltage). The direction of this voltage shift only depends on the sign of

oxide charge and not on the sign of the charge of the donor and acceptor dopant

impurities [18]. Oxide trapped charges cause so-called hysteresis which will be

discussed in the results part.

Now let us discuss about how to extract effective oxide charges and its density from

experimental data, starting from flat-band voltage calculation.

4.3.1 Work function difference

Work function difference is the difference between the gate metal and the

semiconductor work functions in a MOS capacitor [7].

B

g

msmmsq

E

2

(8)

Where m is the work function of the gate metal, s is the work function of the

semiconductor, is electron affinity, gE is the band gap of the semiconductor, and

the Fermi potential B is expressed as [7]:

i

subB

n

N

q

kTln

(9)

Where subN is the doping concentration in the substrate, in is the intrinsic carrier

concentration. The work function of the gate metal ( m ) is equal to the minimum

energy that can extract an electron from the Fermi energy level to the vacuum level.

The work function of the semiconductor ( s ) equals to the sum of electron affinity,

the band gap of the semiconductor divided by the electronic charge and the Fermi

energy shown below.

)10(2

B

g

sq

E

- 18 -

4.3.2 Flat-band voltage

In an ideal MOS capacitor, it is assumed that there is no work function difference and

no charge exists at the interface and no oxide charges. In this case flat band condition

occurs when the applied gate voltage VG=0, where work function difference ms =0,

then VFB=0. The so-called „flat-band‟ means that the energy band diagram of the MOS

structure is horizontal, and no band bending occurs. However, in a real MOS capacitor,

there are many non-ideal effects, for instance by the work function difference and

charge in the oxide and/or at the oxide-semiconductor interface, which must be

considered. The work function difference between the metal and semiconductor is not

equal to zero since the Fermi energy varies with the doping of the semiconductor

material and oxide interface charge. The types of charge in the oxide and at the

interface of oxide-semiconductor have been discussed in the chapter 3. They are

named as the fixed oxide charge Qf, oxide trapped charge Qot and mobile ionic charge

Qm. The sum of these three charges is referred to as effective oxide charge Qeff and its

number density Neff. Both the work function difference and effective oxide charge

affect the flat band condition and the applied voltage to achieve flat band condition in

a real MOS capacitor is called flat-band voltage. It is determined by the equation

below [14]:

eff

ms oxFB

ox

QV

q C

(11)

eff

oxQ = otm QQ fQ (12)

In general, unlike interface trapped charges, these oxide charges only cause a parallel

shift in the gate voltage direction because they are independent of gate bias. In fact,

the location of the charge in the oxide layer determines the voltage shift, i.e., the

closer to the oxide-semiconductor interface, the more shift will be observed [7].

The method to extract flat band voltage VFB illustrated in Fig.4.7. The first step is to

compare experimental and theoretical C-V curves and find out the capacitance value

from the theoretical C-V curve at voltage equals to zero. The capacitance in this case

is called flat-band capacitance CFB. As long as the flat-band capacitance is known, the

corresponding gate voltage, which can be found from the experimental data, is the

flat-band voltage for a real MOS capacitor.

- 19 -

Figure 4.7. Method to extract flat-band voltage from the experimental C-V curve and

ideal C-V curve.

4.3.3 Calculation of Effective Oxide Charges Qeff and

number density Neff.

Once the flat band voltage VFB is obtained, its value is used to calculate the effective

oxide charge eff

oxQ .

eff

ms oxFB

ox

QV

q C

(15)

where Φms and Qeff can be determined if VFB versus Cox is known.

The number density of effective oxide charge eff

oxN is determined by the following

equation:

q

VC

q

QN FBmsox

eff

oxeff

ox

)('

(16)

where C'ox is the oxide capacitance per unit area measured at accumulation.

In order to determine the non-ideal effects caused by oxide charges and interface traps

to capacitance-voltage (C-V) behavior of MOS capacitor, it is necessary to plot the

experimental C-V and theoretical C-V in the same graph to extract the parameters

such as oxide charge ( eff

oxQ ) , density numbers of the oxide charge ( eff

oxN ), flat band

- 20 -

voltage (VFB) and interface state density (Dit) according to the equations defined in

previous discussion. In general, experimental C-V curve shows voltage shift and

distortion compared with ideal C-V curve indicates the existence of both oxide charge

and interface traps. The voltage shift which is indicated by the flat-band voltage

difference of experimental C-V curve from that of the ideal C-V curve will be

discussed in detail later. The distortion of the C-V curve can be considered as the C-V

curve stretch-out along the gate voltage axis. This difference between the stretched

out experimental C-V curve and ideal C-V curve include information of interface

traps which can be used to calculate Dit. Qualitatively, the higher the rate of the slope

in the depletion part, the lower the interface trap density and better interface quality of

the MOS capacitor, and vice versa.

4.4 Probe station and CV measurement set-up

4.4.1 Experimental set-up

The instrument used in this study is mainly for capacitance-voltage (C-V)

measurements as well as current-voltage (I-V) measurements. The main device is a

probe station which consists of four micro-positioners with sharp probes and a

microscope to observe the investigated chip as shown in Fig 4.8(a). These sharp

needles are used to electrically contact the device under test by using manipulators.

There is a sample holder to fix the wafer by vacuum and the whole station is covered

by shielding box preventing light to disturb the measurements. The probe station is

connected to an impedance analyzer LCR (HP 4284A) shown in Fig.4.8 (b), which is

controlled by a PC computer. Labview software is used to perform the desired

measurements and also to analyze the capacitance, frequency and voltage data etc.

- 21 -

Figure 4.8. The capacitance meter is controlled by a PC computer and the output data

is stored in a text file.

(a) Probe station

(b) Impedance analyzer LCR (HP 4284A)

- 22 -

Figure 4.9. The measurement can be control by software in a PC computer.

The measurement parameters can be controlled and changed by using software

„LabView‟ in a PC computer. The measurement results (C-V curve) will be shown

directly on the screen and can also be stored as a text file for further analysis, plotting

etc. During the C-V measurement, two superimposed voltages will be applied to the

sample. One AC probe frequency signal with small amplitude and the other a slowly

varying DC gate voltage at the same time as shown in Fig. 4.10. The small AC signal

is used to extract the capacitance value.

The measurement frequency can be varied from 20 Hz to 1 MHz and the voltage

applied to the sample can be varied from -40 V to 40 V. The step bias can be changed

from 0.05 V to 1 V to control the speed of DC voltage sweep from inversion to

accumulation.

Figure 4.10. Schematic of C-V measurement on semiconductor sample.

- 23 -

Before any measurements can be started, one needs to check the noise level and

calibrate the impedance analyzer to avoid the impact of external noise in the

measurement setup.

The procedures to make a high frequency (HF) C-V measurement are as follows:

Firstly, Setup the DC bias which makes the MOS capacitor working in inversion

region and sweep towards accumulation region. Taking n-type MOS capacitor as an

example, the voltage sweep should start from negative voltage to positive voltage.

Secondly, illumination used to position the probes should be turned off and then one

needs to wait until the capacitance is stable. Lastly, a high frequency (HF) C-V

measurement can be started by sweeping the DC voltage from inversion to

accumulation. This procedure ensures that the inversion charge can be generated and

presented in the high frequency measurement [16].

A typical High frequency C-V curve for an n-type MOS capacitor is shown in Fig

4.11.

Figure 4.11. Typical high frequency C-V curve for an n-type MOS capacitor.

- 24 -

5. Experimental results

5.1 Introduction

Aluminum oxide (Al2O3) is a candidate for high-k dielectric materials in SiC

manufacturing processes, which possibly replaces silicon dioxide (SiO2) as insulating

layers in MOS capacitors. The effects of nitrogen implantation and annealing process

on the Al2O3/SiC samples are studied in this thesis in order to better understand and

improve the performance of Al2O3/SiC MOS capacitors.

Since the quality of the dielectric/SiC interface determines much of the electronic

properties of the SiC-based MOS capacitor, and the quality of the interface is mainly

determined by parameters such as interface states density (Dit), oxide trapped charge,

and fixed oxide charge. These parameters were extracted by using the

Capacitance-Voltage (C-V) measurement and Terman‟s method for all the investigated

samples. Finally, the electrical parameters of the implanted Al2O3/SiC MOS

capacitors were derived and compared among each other in terms of different

epi-types (n- or p-type), dose of implantation, and ion species. All these results were

compared with those of the unimplanted Al2O3/SiC MOS capacitors reference

samples.

As it is mentioned in previous chapter, Terman‟s method was used to extract interface

states density (Dit) in this study. In general, interface traps cause a non-parallel shift of

the C-V curve, leading to the C-V “stretch out” [6]. Fixed oxide charges cause a

parallel voltage shift along the x-axis (gate voltage). The direction of this voltage shift

only depends on the sign of oxide charge and not on the donor or acceptor dopant

impurities [18]. Oxide trapped charges cause so-called hysteresis. All of these effects

will be illustrated by the following results part.

- 25 -

5.2 Electrical analysis of n-type Al2O3/SiC MOS capacitors

(Reference samples)

There are two unimplanted n-type Al2O3/SiC MOS capacitors used as reference

samples. The experimental high frequency (1 MHz) C-V characteristics of these two

reference samples are shown in Fig.5.1. It clearly shows that the reference sample

annealed in Ar at 950 oC for 1 hour has less voltage shift and lower flat band voltage

compared with the sample without annealing process. It is seen that the flat band

voltage shift along the gate voltage axis to negative voltage. This phenomenon

indicates that the annealing process induced more positive charges (or reduced

negative charges) to offset the large flat band voltage shift compared to the sample

without annealing process.

Figure 5.1. High frequency C-V curves for reference samples with and without annealing process.

The theoretical and experimental normalized C-V curves plotted for the reference

samples are shown in Figure 5.2 and 5.3 in order to determine flat-band voltage.

Theoretical C-V curve is calculated by using the equations explained in Chapter 4.

The values of flat band voltage are 25.1 V and 13.6 V for samples before and after the

annealing process respectively. Using this voltage shift, the effective oxide charges

( eff

oxQ ) and their density numbers per unit area (Neff) are calculated by using equation

(16) in Chapter 4. It is reasonable that smaller flat band voltage, corresponding to

smaller Neff for the sample after annealing compared to the one without annealing

shown in the table 5.1.

- 26 -

Figure 5.2. Theoretical and experimental high frequency normalized C-V curves for

reference sample before annealing process (2RN).

Figure 5.3. Theoretical and experimental high frequency normalized C-V curves for

reference sample after annealing (1RN).

During high frequency measurement, oxide traps are not fast enough to respond to the

fast AC signal, but they are able to follow and be charged or discharged by the slowly

varying DC gate voltage. It turns out that the C-V curve sweep from accumulation to

depletion (AD) can not overlap with that sweep back from depletion to accumulation

(DA) for the same sample. This phenomenon is called „hysteresis‟. Figure 5.4 and 5.5

illustrate hysteresis behavior for the two reference samples along the voltage axis.

This observation shows that non-negligible oxide traps exist in the oxide layer in these

samples.

- 27 -

Figure 5.4. Hysteresis curve of MOS device without annealing (2RN) measured from

accumulation to inversion and from inversion to accumulation.

Figure 5.5. Hysteresis curve of MOS device after annealing (1RN) measured from

accumulation to inversion and from inversion to accumulation.

Finally, the density of interface states (Dit) is evaluated by using procedures and

equations explained according to Terman‟s method in Chapter 4. Fig.5.6 and 5.7 show

the density of interface states as a function of gate voltage of SiC. The average value

of Dit is found to be 2.9×1012

eV-1

cm-2

for the sample before annealing process. It is

lower for the sample after annealing process as it is shown in Fig.5.7. The average Dit

is 2.5×1012

eV-1

cm-2

. These results indicate that annealing process conducted in Ar

ambient is effective to reduce Dit.

- 28 -

Figure 5.6. Interface states density (Dit) of n-type unimplanted reference sample

before annealing (2RN).

Figure 5.7. Interface states density (Dit) of n-type unimplanted reference sample after annealing (1RN).

All the parameters extracted above for reference samples are summarized in the table

below. The values of Dit are averaged over the measurement points for easier

comparison.

Samples Nimpl(cm-2

) ND(cm-3

) Cox(pF) VFB (V) Neff(cm-2

) Dit(eV-1

cm-2

)

2RN (not annealed) No 5.0×1015

8.0×10-12

25.1 -2.3×1012

2.9×1012

1RN (annealed) No 5.0×1015

8.7 ×10-12

13.6 -1.8×1012

2.5×1012

Table 5.1 Summary of the parameters extracted from the high frequency C-V measurements for n-type

reference samples.

Dit (

eV-1

cm-2

)

Gate voltage (V)

Dit (

eV-1

cm-2

)

Gate voltage (V)

- 29 -

5.3 Electrical analysis of n-type Al2O3/SiC MOS capacitors

(N- or C-implanted samples)

It has been reported that a nitrogen ion implantation process at the SiO2/SiC interface

before oxidation of SiC produced a strong reduction of Dit [4]. However, the

disadvantage of this implantation process is the increase of fixed positive charges in

the oxide which cause an unwanted shift of the flat-band voltage (VFB) [19]. We

prepared three implanted n-type Al2O3/SiC MOS capacitors, two samples were

implanted by nitrogen ions with different doses and one was implanted by Carbon

ions to study the effects of implantation process on the samples.

Figure 5.8. High frequency C-V curves for sample implanted by nitrogen ions with

dose of 5×1013

and 5×1014

cm-2

.

The theoretical and experimental normalized C-V curves plotted for the same MOS

capacitor structure in Figure 5.9 and 5.11 in order to determine flat band voltage of

these two reference samples. Theoretical C-V curve is calculated by using the

equations explained in Chapter 4. The values of flat band voltage are -25.2 V and

-22.6 V for sample before/after annealing process respectively. Using this voltage

shift, the effective oxide charges ( eff

oxQ ) and their density numbers per unit area (Neff)

are calculated by using equation (16). It is seen that the flat band voltage for the

- 30 -

sample implanted with higher dose (5×1014

cm-2

) of N+ is a bit lower that of lower

implantation dose. Although flat band voltage shift of samples named 1N3 and 2N4 is

very large, but the Dit of them are smaller than that of reference samples as shown in

Fig. 5.10 and Fig. 5.12. This indicates that there exists considerable oxide charges but

much less interface traps in samples 1N3 and 2N4. It is reasonable to see that Dit of

2N4 is larger than that of 1N3 because of the larger damage caused by higher dose of

N+ implantation.

Figure 5.9. Theoretical and experimental high frequency normalized C-V curves for

sample implanted by nitrogen ions with dose of 5×1013

cm-2

(1N3).

Figure 5.10. Interface states density (Dit) of sample implanted by nitrogen ions with

dose of 5×1013

cm-2

(1N3).

Dit (

eV-1

cm-2

)

Gate voltage (V)

- 31 -

Figure 5.11. Theoretical and experimental high frequency normalized C-V curves for

sample implanted by nitrogen ions with dose of 5×1014

cm-2

(2N4).

Figure 5.12. Interface states density (Dit) of sample implanted by nitrogen ions with

dose of 5×1014

cm-2

(2N4).

For the sample implanted with Carbon ions, we obtained a substantially better C-V

curve which indicates a small flat band voltage -1.59 V and a very low average

density of interface states Dit= 5.6×1011

. All these parameters indicate that Carbon

implantation is effective to reduce both oxide charges and interface states and thus to

improve electrical property of the n-type Al2O3/SiC MOS capacitor.

Dit (

eV-1

cm-2

)

Gate voltage (V)

- 32 -

Figure 5.13. High frequency C-V curves for sample implanted by carbon ions with

dose of 5×1013

cm-2（3N3）

Figure 5.14. Theoretical and experimental high frequency normalized C-V curves for

sample implanted by carbon ions with dose of 5×1013

cm-2（3N3）

Figure 5.15. Interface states density (Dit) of sample implanted by carbon ions with

dose of 5×1013 cm

-2 (3N3).

Gate voltage (V)

Dit (

eV-1

cm-2

)

- 33 -

All the parameters extracted above for implanted N-type samples are summarized in

the table below.

Samples Nimpl(cm-2

) ND(cm-3

) Cox(pF) VFB (V) Neff(cm-2

) Dit(eV-1

cm-2

)

1N3 (Nitrogen) 5.0×1013

5.0×1015

5.4×10-13

-25.2 6.5×1012

2.0×1011

2N4 (Nitrogen) 5.0×1014

5.0×1015

6.1×10-12

-22.6 4.4×1013

9.6×1011

3N3 (Carbon) 5.0×1013

5.0×1015

4.7 ×10-12

-1.59 1.8×1011

5.6×1011

Table 5.2 Summary of the parameters extracted from the high frequency C-V measurements for N- and

C- implanted n-type samples.

5.4 Electrical analysis of p-type Al2O3/SiC MOS capacitors

(Reference samples)

Similar to the analysis used for n-type Al2O3/SiC MOS capacitors, two p-type

epi-layer reference samples have also been studied. For most of p-type samples used

in this study, no obvious hysteresis behavior is observed. However, large flat band

voltage shift has been found by most of p-type samples which indicates that Nitrogen

implantation introduced large amount of positive oxide charges (or a large reduction

in negative charges) to these samples. It is worth to mention that the flat-band voltage

for the sample without annealing process is smaller than the one after the annealing

process. This indicates that the annealing process may also introduce negative oxide

charge to p-type reference samples. On the contrary, the annealing process may

introduce positive oxide charge according to the flat-band voltage shift observed for

n-type reference samples. Interface state density (Dit) was not extracted for p-type

samples due to the bad results obtained and difficulty to extract according to Terman‟s

method.

Figure 5.16. High frequency C-V curves for reference samples with and without annealing process.

- 34 -

Figure 5.17. Theoretical and experimental high frequency normalized C-V curves for

reference sample after annealing.

Figure 5.18. Theoretical and experimental high frequency normalized C-V curves for

reference sample without annealing.

Samples Nimpl(cm-2

) NA(cm-3

) Cox(pF) VFB (V) Neff(cm-2

)

1RP (annealed) No 5.0×1015

4.4×10-11

15 -2.8×1013

2RP(not annealed) No 5.0×1015

3.2×10-11

11.7 -1.0×1013

Table 5.3 Summary of the parameters extracted from the high frequency C-V measurements for p-type

reference samples.

- 35 -

5.5 Electrical analysis of p-type Al2O3/SiC MOS capacitors

(N- implanted samples)

Similar to n-type samples, there are two p-type Al2O3/SiC MOS capacitors samples

were implanted with nitrogen ions. Their C-V curves and important parameters were

extracted and summarized in the following figures and table.

Figure 5.19. High frequency C-V curves for sample implanted by nitrogen ions with

dose of 5×1013

cm-2

and 5×1014

cm-2

.

Figure 5.20. Theoretical and experimental high frequency normalized C-V curves for

sample implanted by nitrogen ions with dose of 5×1013

cm-2

.

- 36 -

Figure 5.21. Theoretical and experimental high frequency normalized C-V curves for

sample implanted by nitrogen ions with dose of 5×1014

cm-2

.

Samples Nimpl(cm-2

) NA(cm-2

) Cox(pF) VFB (V) Neff(cm-2

)

1P3 5.0 x1013

5.0 x1015

2.3 x10-11

>>8 >>-8.4x1012

2P4 5.0 x1014

5.0 x1015

2.2 x10-11

20.2 -1.8x1013

Table 5.4 Summary of the parameters extracted from the high frequency C-V measurements for

p-type N implanted samples

- 37 -

6. Discussion

In this thesis, the investigation of MOS capacitor utilizing Al2O3 as gate dielectrics on

4H-SiC shows that the type of epitaxial layer, dielectric material, and process

technique influence the electrical behavior of the MOS capacitors. The results of the

study, summarized in the previous chapter, illustrate that n-type reference sample after

annealing achieved a strong reduction in both Neff and Dit compared to the values

before annealing. This indicates that the annealing process is effective to improve the

quality of the Al2O3/SiC interface.

For Carbon implanted samples, a strong reduction of both effective oxide charges

(Neff) and Dit have been obtained by using a C implantation before forming the

dielectric layer for the n-type epitaxial layer in the SiO2/SiC MOS structure. It

indicates that the presence of carbon at the Al2O3/SiC interface improves the quality

of this interface in strong contrast to what others have reported. According to this

result, it would be very interesting to employ carbon implantation also to p-type MOS

capacitor. It has been reported that the employment of N+ implantation process before

wet oxidation is effective in reducing the SiO2/SiC interface state density only if a

high N concentrations remains at the oxide-SiC interface [4]. However, differently to

the conclusions reported by [4], the results in this study of samples treated by N

implantation in this study show a reduction of Dit, but a substantial higher effective

oxide charge than the reference samples. The results of effective oxide charge Neff and

Dit obtained from the p-type samples with the same treatments show an even higher

value so it becomes difficult to extract Dit by Terman‟s method. The possible reason

for this could be the different dielectric material and the oxidation process used in this

study and [4]. In this study, Al2O3 layer was deposited on the SiC epitaxial layer by

employing thermal atomic layer deposition (ALD) before the N implantation process

instead of depositing SiO2 by the CVD technique and then carrying out a wet

oxidation process to consume the desired thickness of SiC after N implantation

process reported by [4]. These reasons explain why the results obtained from the N

implanted samples have higher values of effective oxide charge than the reference

samples. The last possible reason is the different annealing processes used in these

two studies. There is no standard annealing process in common for fabricating SiC

MOS capacitors. Many factors, such as temperature, time, and annealing ambient

during the annealing process determine the recovery of the samples and thus the

electrical quality of them.

As it can be seen from the results in Chapter 5, most of the investigated samples

produced very large shift in the flat-band voltage, which could be due to that the C-V

curves go into so-called deep depletion. There are several reasons to explain this

- 38 -

phenomenon. First of all, if the DC voltage is abruptly changed from accumulation to

inversion, the inversion charge cannot follow the DC voltage which forces the

capacitance to be included in the deep depletion part. When the ramp voltage is in

accumulation or depletion, only majority carriers participate and react to the changing

voltage. A large number of minority carriers are needed to achieve an equilibrium

charge distribution within the MOS capacitor. However, the minority carriers are not

present near the surface region of the semiconductor and the generation process for

supplying the minority carriers is rather slow and makes it difficult for the structure to

equilibrate. Thus the semiconductor is in a non-equilibrium condition, the depletion

width becomes greater than the one in equilibrium condition which explains the

reduced values of the capacitance obtained in the depletion region of the C-V curve.

Secondly, if the C-V curve always goes into deep depletion, another possible cause is

that inversion charge leaks away through the oxide. Lastly, if the substrate is not

uniformly doped the doping profile can be obtained from the capacitance in deep

depletion.

The first possible reason for a C-V curve to go into deep depletion can be avoided by

slowing down the step bias of DC sweep in the experiment. However, it is worth to

mention that even using the slowest ramp rate, one does not obtain the inversion part

of the high-frequency characteristic. It is suggested that ‘‘One must stop the ramp in

inversion and allow the device to equilibrate, or slowly sweep the device backward

from inversion toward accumulation, to accurately record the high-frequency

inversion capacitance.’’ [16]. It is seen from the results that the depletion region of the

C-V curve can only be obtained under a very high applied voltage for most samples.

The second and third explanations should be the reasons why the C-V curves go into

deep depletion for most of these samples. Although high-k material (Al2O3) was used

as an oxide layer instead of SiO2 for these samples, the thickness of the oxide layer is

still not thick enough to prevent that charge leaks away through oxide layer and thus

the sample goes into deep depletion. This problem makes it very difficult to extract

parameters and analyze the experimental C-V curve, for instance, some important

parameters such as flat-band voltage and Dit, by comparing it with the ideal C-V

curve.

In future work, I-V measurement of these samples can be used to obtain information

about leakage current in order to find a solution to this problem. Also, the results tend

to vary between different dots on the same wafer. Only a few dots on each wafer show

good results which indicate that the quality of these samples are not as good as what

was expected. Therefore some improvements should be made during the sample

preparation process in further studies.

- 39 -

7. Conclusion

In this thesis, characterization of N- and C- implanted Al2O3/SiC MOS capacitors

fabricated on 4H-SiC epitaxial layers was analyzed and the results of some important

parameters are presented.

For the n-type implanted samples, the employment of N implantation to Al2O3/SiC

MOS capacitor is not that effective to reduce the effective oxide charge (Neff), but the

interface state density (Dit) is indeed reduced. However, the employment of C ion

implantation to Al2O3/SiC interface is remarkably effective in reducing the effective

oxide charge (Neff) as well as the interface state density (Dit).

It is generally known and proved by previous studies that the p-type SiO2/SiC MOS

capacitor shows significantly higher effective fixed charge and Dit than n-type

SiO2/SiC MOS capacitor [6]. The conclusion is similar for Al2O3/SiC MOS capacitor

in this study. Qualitatively, the slope of the C-V curve obtained from ion implanted

p-type samples is much higher than that for n-type samples with the same treatment

which implies that the p-type Al2O3/SiC samples fabricated by the process in this

study have significantly higher Dit than that of the n-type. The ion implanted samples

with Al2O3 deposited on the n-type 4H-SiC show superior C-V characteristics

compared to those on the p-type 4H-SiC. Two samples treated by N ion implantation

with doses of 5×1013

cm-2

and 5×1014

cm-2

after annealing in Ar ambient have Dit

values in the order of magnitude of 1011

cm-2

which shows that our goal to reduce Dit

by ion implantation is achieved. The carbon ion implanted sample shows the best

quality in terms of very low effective oxide charge Neff (1.8×1011

cm-2

) and Dit

(5.6×1011

eV-1

cm-2

) and indicates a new approach to improve the characteristics of

least the n-type 4H-SiC MOS capacitors. However, future investigation is required to

understand the underlying reasons for the improvements made by C ions at the

Al2O3/SiC interface.

- 40 -

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- 42 -

Appendix

Type of epi Implanted ionsImplantation dosesDielectric Annealing Develop contacts Name(Substr. n-type) (Energy 2 keV) (time:1 hour)(Front/Back side)

Nitrogen 5×1013 Al2O3 Ar 950 °C Al/Ni 1N3

n-type Nitrogen 5×1014 Al2O3 Ar 950 °C Al/Ni 2N4

Carbon 5×1013 Al2O3 Ar 950 °C Al/Ni 3N3

Nitrogen 5×1013 Al2O3 Ar 950 °C Al/Ni 1P3

p-type Nitrogen 5×1014 Al2O3 Ar 950 °C Al/Ni 2P4

Reference Dielectric Annealing Develop contacts Name(time:1 hour)(Front/Back side)

Al2O3 Ar 950 °C Al/Ni 1RN

n-typeAl2O3 Not annealed Al/Ni 2RN

Al2O3 Ar 950 °C Al/Ni 1RP

p-typeAl2O3 Not annealed Al/Ni 2RP

Implantation

non-implanted

non-implanted

non-implanted

non-implanted