Review: MOS Capacitor with External Bias

1

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Lec 5: January 28, 2016 MOS Operating Regions, pt. 1

Penn ESE 570 Spring 2016 – Khanna

Lecture Outline

!  3 Regions of operation for MOSFET "  Subthreshold "  Linear "  Saturation

!  Level 1 Model

2 Penn ESE370 Fall2015 – Khanna

- - - - -

Review: MOS Capacitor with External Bias

!  Three Regions of Operation: "  Accumulation Region – VG < 0 "  Depletion Region – VG > 0, small "  Inversion Region – VG ≥ VT, large

3 Penn ESE 570 Spring 2016 - Khanna

- - - - -

Subthreshold/cut-off Above threshold

- - - - -

Review: MOS Capacitor with External Bias

!  Three Regions of Operation: "  Accumulation Region – VG < 0 "  Depletion Region – VG > 0, small "  Inversion Region – VG ≥ VT, large


- - - - -

Subthreshold/cut-off Above threshold

Review: nMOS = MOS cap + source/drain

5

VSB = 0

-

- - - - - -

- - -

-

VG VD VS

xd =2εSi 2ΦFp −VSB

q ⋅NA

Penn ESE 570 Spring 2016 - Khanna

Review: Threshold Voltage

6

for VSB = 0 VT =VT 0 =VFB − 2ΦF −QB0

Cox

for VSB != 0 VT =VT 0 +γ 2ΦF −VSB − 2ΦF( )

Penn ESE 570 Spring 2016 - Khanna

γ =2qNAεSiCox

2

MOSFET – IV Characteristics

VGS

IDS

0

10

20

30

40

50

0 2 4 6 8 10

Dra

in c

urr

ent

[arb

itra

ry u

nit

]

Gate to source voltage [V]

VDS

Define:Vth = Threshold Voltage


MOSFET – IV Characteristics

VDS

IDSVGS -Vth

VDS ≥VGS -VTH

VDS <VGS -VTH


Cutoff Region

9

VGS << VT0

Substrate or Bulk B p

Depletion region

-

-

-

- -

-

- - -

-

Immobile acceptor

ions

VS

VG VD

NMOS TRANSISTOR IN CUTOFF REGION

No depletion or inversion layer under oxide, no current flow


Onset of Inversion Region

10

QB0 QI

-

- -

- - - - - -

-

- - -

-

VG VD

VGS = VT0n + δVDS = 0

Depletion region, and thin inversion layer (aka channel) Thermal equilibrium in channel, no current flow


Linear Region

11

n+ n+ -

- - -

- - - -

- -

-

VGS > VT0 VDS small, VDS < VGS - VT0

Channel acts like voltage controlled resistor Current flows proportional to VDS ( )

As VD increases, channel depth at the drain decreases

ID ∝VDS


Channel Voltage

!  Voltage varies along channel !  Channel acts as a resistor

"  Serves as a voltage divider between VS and VD

12 Penn ESE 570 Spring 2016 – Khanna

3

Voltage along Channel

y=0 y=L

y V(y)

13

!  Voltage divider between VS and VD




y=0 y=L

y V(y)

Vs

Vd




y=0 y=L

y V(y)

Vs

Vd




y=0 y=L

y V(y)

Vs

Vd


Linear/Saturation Region Edge

17

n+ n+ -

- - -

- - - - -

- - -

-

VGS > VT0 VDS = VGS – VT0

Voltage divider along channel, until pinch off As VD increases, channel depth at the drain decreases


Channel Field

!  When voltage gap VG - Vy drops below Vth, channel drops out of inversion "  If VDS = VGS – Vth #VGS – VDS =VG – VD = Vth


4

Saturation Region

19

V(x) = VDSAT

VDS - VDSAT

n+ n+

z -

- -

- - - - -

- - -

-

VGS > VT0 VDS > VGS – VT0


Channel Field

!  When voltage gap VG - Vy drops below Vth, drops out of inversion "  What if VDS > VGS – Vth #VDS – VGS > Vth?

"  Upper limit on current, channel is “pinched off” "  nMOS current saturated


MOSFET IV Characteristics

21

zn+ n+



22

xy

z y

µn = electron mobility = cm2/(V sec)

MOSFET IV Characteristics – Linear Region

dR = − dyW ⋅µn ⋅QI (y)


23

z

Mobile charge in inverted channel:

n+ n+

QI(y) = - Cox [VGS – V(y) - VT0]

V(y)



V(y=0) = VS = 0, V(y=L) = VDS Boundary Conditions:



24

dVCS

QI(y) = - Cox [VGS – V(y) - VT0] dR = − dyW ⋅µn ⋅QI (y)

dVC = ID ⋅dR = −ID

W ⋅µn ⋅QI (y)dy

−W ⋅µn ⋅QI (y) ⋅dVC = ID ⋅dy

ID ⋅dy0

L

∫ = −W ⋅µn ⋅QI (y) ⋅dVC0

VDS

∫

ID ⋅L =W ⋅µn ⋅Cox (VGS −VC −VT 0 ) ⋅dVC0

VDS

∫

ID = µn ⋅CoxWL(VGS −VT 0 )VDS −

V 2DS

2$

%&

'

()

V(y=0) = VS = 0, V(y=L) = VDS Integrate along the channel:


5


25


V 2DS

2#

$%

&

'(

ID =k22(VGS −VT 0 )VDS −V

2DS( )

k ' = µn ⋅Cox k = k 'WL

ID =k '2WL2(VGS −VT 0 )VDS −V

2DS( )



26

ID(VDS = VDSAT) and VDSAT = VGS - VT0

Assumptions:



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ID(VDS = VDSAT) = ID(sat)

@VDS = VDSAT = VGS - VT0

SAT LINEAR ID(sat)

IN GENERAL

IDSAT =µn ⋅Cox

2WLVGS −VT 0( )2


28

VDSAT

n+ n+

VGS > VT0 VDS > VGS – VT0

ΔL

IDSAT =µn ⋅Cox

2WL '

VGS −VT 0( )2 = µn ⋅Cox

2W

L 1− ΔLL

$

%&

'

()VGS −VT 0( )2

ΔL∝ VDS −VDSAT 1− ΔLL≈1−λ ⋅VDS

empirically

If λ$VDS<<1, 1− ΔLL≈1−λ ⋅VDS ≈1+λ ⋅VDS

MOSFET IV Characteristics - Saturation


29

IDSAT =µn ⋅Cox

2WL '

VGS −VT 0( )2 = µn ⋅Cox

2W

L 1− ΔLL

$

%&

'

()VGS −VT 0( )2

ΔL∝ VDS −VDSAT 1− ΔLL≈1−λ ⋅VDS

emprically

If λ$VDS<<1, 1− ΔLL≈1−λ ⋅VDS ≈1+λ ⋅VDS

MOSFET IV Characteristics - Saturation

ID =µn ⋅Cox

2WLVGS −VT 0( )2 (1+λ ⋅VDS )


30

ID =µn ⋅Cox

2WLVGS −VT 0( )2 (1+λ ⋅VDS )

λ≠0 λ=0


V 2DS

2#

$%

&

'(

Saturation Region:

Linear Region:



6

31

ID =µn ⋅Cox

2WLVGS −VT 0( )2 (1+λ ⋅VDS )

λ≠0 λ=0


V 2DS

2#

$%

&

'(

Saturation Region:

Linear Region:


DISCONTINUOUS! @ VDS = VDSAT


32

ID =µn ⋅Cox

2WLVGS −VT 0( )2 (1+λ ⋅VDS )

λ≠0 λ=0


V 2DS

2#

$%

&

'((1+λ ⋅VDS )

Saturation Region:

Linear Region:




33

ID =µn ⋅Cox

2WLVGS −VT 0( )2 (1+λ ⋅VDS )

λ≠0 λ=0


V 2DS

2#

$%

&

'((1+λ ⋅VDS )

Saturation Region:

Linear Region:



Level 1 model λ$VDS<<1


34

ID =µn ⋅Cox

2WLVGS −VT (VSB )( )2 (1+λ ⋅VDS )

ID = µn ⋅CoxWL(VGS −VT (VSB ))VDS −

V 2DS

2#

$%

&

'((1+λ ⋅VDS )

Saturation Region:

Linear Region:

MOSFET IV Characteristics, VSB≠0

VT =VT 0 +γ 2ΦF −VSB − 2ΦF( )

ID = f (VGS,VDS,VSB )


35

ID =

0 VGS ≤VTnµn ⋅Cox

2WL2 VGS −VTn (VSB )( )VDS −V 2

DS( )(1+λ ⋅VDS ) VGS >VTn,VDS <VGS −VTn

µn ⋅Cox

2WLVGS −VTn (VSB )( )2 (1+λ ⋅VDS ) VGS >VTn,VDS ≥VGS −VTn

%

&

'''

(

'''

nMOS IV Characteristics


Cutoff/Subthreshold

Linear/Resistive

Saturation

36

ID =

0 VGS ≥VTpµp ⋅Cox

2WL2 VGS −VTp(VSB )( )VDS −V 2

DS( )(1+λ ⋅VDS ) VGS <VTp,VDS >VGS −VTp

µp ⋅Cox

2WLVGS −VTp(VSB )( )

2(1+λ ⋅VDS ) VGS <VTp,VDS ≤VGS −VTp

%

&

'''

(

'''

pMOS IV Characteristics


Cutoff/Subthreshold

Linear/Resistive

Saturation

7

Measurement of Parameters – k, γ

37

=> SAT

B

S

G

D


Measurement of Parameters – λ

38

=> SAT


Big Idea

!  3 Regions of operation for MOSFET "  Subthreshold "  Linear "  Saturation

"  Pinch Off "  Channel length modulation

!  Level 1 Model "  ID=f (VGS, VDS, VSB) "  Empirical parameters: k, γ,λ

39 Penn ESE370 Fall2015 – Khanna

Admin

!  HW 1 grades available !  HW 3 due Thursday, 2/4

"  Posted tonight after class

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Review: MOS Capacitor with External Bias

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