ww1.microchip.comww1.microchip.com/downloads/en/DeviceDoc/KSZ8873MLL_FLL_RLL_DS.pdfPK :n3E...

June 2004 1 M9999-062204

Application Note 111 Micrel

Application Note 111General PCB Design and Layout Guidelines

Micrel 10/100 Switches and PHYs

General DescriptionThis application note assists in designing products thatcomply with both EMI and ESD standards using Micrels10/100 family of switches and PHYs.

The printed circuit board (PCB) is the single most importantfactor affecting EMI, ESD, and overall performance. Meetingthese requirements depends on good PCB design practices.The goal here is to minimize digital and common mode noiseas well as to provide shielding between the PCBs internalcircuitry and the external environment. These PCB designpractices should apply to the entire PCB design, not just toMicrel's Ethernet products.

General Rules Position components so as to avoid long loop traces.

Choose a metal box to shield the circuit board.

Use a ferrite core on the DC power cord to reduce EMI.

Follow layout guidelines for differential pairs, groundplane, and high-speed signals.

Provide termination on clock lines and high-speed digitalsignals.

Provide impedance matching on high-speed signaltraces to prevent reflections.

Keep power and ground noise under 50mV peak-to-peak.

Ensure that the power supply is rated for the application.

Ensure that switching converters are filtered and properlyshielded as these power converters can produce a greatdeal of EMI noise.

Power and Ground Planes Do not split the ground plane into separate planes for

analog, digital, and power pins. A single ground plane isrecommended for Micrels 10/100 Ethernet products.

Route high-speed signals above a continuous unbrokenground plane.

Fill copper in the unused area of signal planes, andconnect these copper fills to the ground plane with vias.

Stagger the placement of vias to avoid creating longgaps in the planes due to via voids.

Analog VCC Planes Place and route the analog components within the

analog VCC plane.

Digital VCC Planes Place and route the digital components within the digital

VCC plane.

Micrel, Inc. 1849 Fortune Drive San Jose, CA 95131 USA tel + 1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com

Signal Ground Plane

Chassis Ground Plane

Void area to preventloop antenna effect.

RJ-45

RJ-45

RJ-45

RJ-45

Figure 1. Ground Planes

Magnetic Noise Zone Void power and ground planes on all PCB layers directly

under the magnetics.

Extend the chassis ground from the magnetics to theRJ-45 connectors.

Do not route any digital signals between the PHY andRJ-45 connectors.

Signal GroundThe signal ground region should be one continuous,unbroken plane.

Connect GNDD, GNDA, and GNDS directly to the signalground plane for Micrels 10/100 Ethernet products.

Chassis GroundThe chassis ground and magnetics serve two purposes: theyhelp to reduce EMI noise emissions from the signal groundplane to the PCBs external environment and also act as ashield to protect the PCB components from ESD.

Place the chassis ground on all PCB layers except forthe power plane layer(s).

Use super vias to join the chassis ground on differentPCB layers.

Connect the chassis ground at multi-points to theexternal chassis and/or metal frame.

Use a trench/moat to isolate the chassis ground planefrom the signal ground plane.

The chassis ground region extends from the front edgeof the PCB board (RJ-45 connectors) to the magneticsand around the edge of the board. See Figure 1.


M9999-062204 2 June 2004

PCB Layer Stacking6-Layer Example

Layer 1 component side (short traces), 1-oz copper

Layer 2 ground plane, 1-oz copper

Layer 3 signal, 1-oz copper


Layer 5 power plane, 1-oz copper


Keep Layers 3 and 4 as far apart as possible.

4-Layer Example

Layer 1 component side, 1-oz copper

Layer 2 ground plane, 1-oz copper

Layer 3 power plane, 1-oz copper


Clock Layout Guidelines Keep clock traces as short as possible.

Ensure that all clock traces have an unbroken referenceground plane.

Use a clock driver when driving multiple loads from asingle oscillator.

Terminate all clock signals.

For example, place a 33 50 series resistor close tothe clock source.

ESD ProtectionVarious ESD protection methods and devices can be used.The level of ESD protection provided by each method variesand depends on the type of protection device used. Consultthe specific manufacturers data sheet to determine the levelof ESD protection and proper connection. Figures 3 and 4show examples of two ESD protection methods.

PCB

5 mil 15 mil5 mil5 mil 5 mil 5 mil 5 mil 15 mil15 mil

keep out TX+ TX- keep out RX+ RX- keep out

Figure 2. Transmit/Receive Differential Pair

Differential Signal Layout Route differential pairs close together and away from all

other signals. Route each differential pair on the same PCB layer. Keep both traces of each differential pair as identical to

each other as possible. Keep transmit (TX) and receive (RX) pairs at least three

times the distance from each other. Route TX and RX differential pairs using 5-mil trace

width and 5-mil spacing. See Figure 2.

Place transient voltage suppressor (TVS) devices on theTX and RX differential pair I/Os to help increase ESDprotection.

These devices are connected in parallel with the I/Olines to be protected.

Connect all unused inputs to either ground with a 1Kresistor or power with a 10K resistor, depending on thedesired strap-in setting of the chip.

Place termination resistors for the TX and RX differen-tial pairs close to the Micrel chip. See Figure 5.

During FCC or ESD tests, remove all unused headerspins, jumpers, test point pins, etc. These parts act asantennas and can degrade test results.

Ferrite Bead

Ferrite Bead

MicrelEthernet

Device

To RJ-45

To RJ-45

Example of alow-capacitancesteering diode/TVS.

Figure 3. ESD Protection on the RJ-45 Side

MicrelEthernet Device

Example of alow-capacitancesteering diode/TVS.

Ferrite Bead

Ferrite BeadTo

RJ-45

Signal Ground

Vcc (Micrel Transceiver)

ToRJ-45

Figure 4. ESD Protection on Micrel's EthernetDevice Side

49.9

49.9

49.9

49.9

0.1F

0.1F

RXP

RXM

TXM

TXP

MicrelEthernetDevice

Figure 5. Termination of TX and RX Differential Pairs

For additional support, contact your local Micrel FieldApplication Engineer or salesperson.

June 2004 3 M9999-062204


MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USATEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product canreasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into thebody or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchasers use orsale of Micrel Products for use in life support appliances, devices, or systems is at Purchasers own risk and Purchaser agrees to fully indemnify Micrel for

any damages resulting from such use or sale.

2004 Micrel, Incorporated

KSZ8873MLL_FLL_RLL_DP1.5/App Note/App Note QoS and Rate_Limit in 8873_8863 Family.pdf

Application Note QoS Priority and Rate Limit Support

for the KSZ8873/8863 Family

Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com

June 2011 M9999-060811-A

Introduction Latency critical applications such as Voice over IP (VoIP) and video typically need to guarantee a high quality of service (QoS) throughout the network. QoS can be supported by various priority schemes offered by the switches and routers. This application note describes the different priority schemes supported by the KSZ8873/8863 family of switches and how they are configured. There are three different priority schemes supported by the devices: Port-based priority, 802.1p Tag-based Priority and DiffServ-based priority. The mechanisms for each of these priority schemes differ only with respect to the ingress port. The egress port buffer scheme is common to all three priority schemes.

Common Settings for Port Based, 802.1p Tag Based and DiffServ Based Priorities The KSZ8873/8863 family of devices offers four priority transmits queues per port. Queue 3 is the highest priority queue as priority 3 and Queue 0 is the lowest priority queue as priority 0 in 4 queue mode. The bits 0 of the port registers control 0 are used to enable splitting transmit 4 queues for egress port 1, port 2 and host port respectively. The bits 7 of the port registers control 2 are used to enable splitting transmit 2 queues for egress port 1, port 2 and host port respectively (4Q and 2Q can not be set at same time).

Priority Scheme Priority transmit queuing allows a switch to define two

priority schemes. One is always transmit higher priority packets first mode. The other is the weighted fair queuing (WFQ) mode. When the transmit queue is set to WFQ mode, the transmit queue will follow a scale for the four queues and the bandwidth allocation is Q3:Q2:Q1:Q0=8:4:2:1. If any queue is empty, the highest non-empty queue will get one more weighting. For example, if Q2 is empty, Q3:Q2:Q1:Q0 will become (8+1):0:2:1. This mechanism assures that during congestion, the higher-priority data does not get delayed by lower-priority traffic. Some examples of priority level are: Important Voice and video packets are assigned a

highest-priority level 3. General Voice and video packets are assigned a

higher-priority level 2. Web traffic is assigned a lower-priority level 1. Back-up data traffic is assigned the lowest-priority

level 0. The Weighted Fair Queuing (WFQ) mode tries to ensure that the lower-priority packets will not be starved during congestion. WFQ is implemented in the KSZ8873/8863 three ports switches; with a host bus as the host port, by controlling the priority scheme select bit 3 in the global register 5. These related registers as shown in table 1. All datasheets and support documentation can be found on Micrels web site at: www.micrel.com.

Register Bit Name Description Default Global register 5 bit 3=0 and the port registers 175 to 186 bit7=0

3/7 Priority Scheme select

Always high priority packets first. 1

Global register 5 bit 3=1 or 0 and the port registers 175 to 186 bit7=1

3/7 Priority Scheme Select

. 4Q: Weighted Fair Queuing (WFQ) is enabled, Q3,Q2,Q1,Q0 = 8:4:2:1. 2Q: Weighted Fair Queuing (WFQ) is enabled, Q1,Q0 = 2:1.

0

Table 1. Registers are used for the priority Schemes Notes: 1. If the TX Multiple Queues Select Enable bit is not enabled in port register control 0 bit0 and control 3 bit7, then only a single output queue will be

present at the egress port. Hence, the priority scheme selection will have no effect, irrespective of the other settings for the ingress and egress ports.

2. The settings highlighted in Note 1 above will be used for all Port based priorities, 802.1p based priorities and DiffServ based priorities.

Micrel, Inc. App. Note

June 2011 2 M9999-060811-A

Port Based Priority Port based priority is the simplest form of QoS. Each ingress port can be individually classified as one of the priorities 0-3. All packets arriving at the ingress port will be passed to any of the four priority queues at the egress port, depending upon the configuration of the ingress port. Each ingress port can be configured as one of the priorities 0-3 by using the Port Based Priority Classification Enable bit shown in Table 2. For example, if the port register control 0 bit 4-3 is set to 10, all of packets from ingress port 2 will be treated as priority 2 level packets and go to priority 2 transmit queue on the egress port which has set into four priority queues.

Register Bit Name Description Default Port registers control 0 4-3 Port based

priority classification

00 = ingress packets on port n will be classified as priority 0 queue. 01 = ingress packets on port n will be classified as priority 1 queue. 10 = ingress packets on port n will be classified as priority 2 queue. 11 = ingress packets on port n will be classified as priority 3 queue.

00

Table 2. Registers are used for Port Based Priority Note: Diffserv, 802.1p and port priority can be enabled at the same time. The ORed result of 802.1p and DSCP overwrites the port based priority.

802.1p Tag Based Priority 802.1p priority can be enabled by the 802.1p Priority Classification Enable bit in the Port Registers Control 0 bit 5. Ethernet packets can have an optional 4-byte 802.1q VLAN tag inserted between the source address (SA) and the length/type fields. As shown in Figure 1, there is a 3-bit priority field embedded in the 4-byte tag, the 3-bit priority field is used for 802.1p priority classification.

Figure 1. Ethernet Packet with 802.1q VLAN Tag The 3-bit priority field in the VLAN tag is used to set the priority level (0-3) for each packet. The number value from 0 to 7 is configured in the switch and compared to the binary equivalent of the incoming packets priority field in the VLAN tag. The 3-bit priority field value (0-7) can be decoded as priority level (0-3) by the global register 12 and register 13, they can be programmed by the user (See Table 3 for details). The priority field value of the incoming tagged packets will be re-classified to four priority levels based on the global register 12 and register 13 setting. The related registers are as shown in Table 3 for 802.1p based priority.


June 2011 3 M9999-060811-A

Register Bit Name Description Default Port Register Control 0 bits 5

5 Priority Classification Enable

1 = Enable 802.1p priority classification for ingress packets on port. 0 = Disable 802.1p priority.

0

7-6 Tag_0x7 IEEE 802.1p mapping. The value is used as the frames priority when its IEEE Tag has a value of 0x7.

0X3 for priority 3


0X3 for priority 3


0X2 for priority 2

Global Register 13


0X2 for priority 2


0X1 for priority 1


0X1 for priority 1


0X0 for priority 0

Global Register 12


0X0 for priority 0

Port Register Control 1 bit 3

3 User Priority Field (Ceiling)

1 = If the packets priority field is greater than the user priority bits in port ns VID Control register bits [15:13], replace the packets priority field with the user priority bits in port ns VID Control register bits [15:13]. 0 = Do not compare and replace the packets user priority field.

0

Port Register Control 3 bits [7:5]

7-5 User Priority bits

Port n tag [7-5] is for priority field of ingress tagged packet to be compared or replaced.

000

Table 3. Registers are used for Tag Based Priority Note: The ORed result of 802.1p and DSCP (see below) priority classification overrides any port priority.

Priority Re-Mapping The KSZ8873/8863 family of devices has the ability to re-map the ingress packets 802.1p priority field by setting bit 3 of User Priority Field in the port registers control 1 and bits [7-5] of User Priority Bits in the port registers control 3. An example of the importance of priority re-mapping is shown as follows. In the case that port 1 is connected to a PC and port 2 is connected to a VoIP router, a problem may occur if you have a corrupt PC transmitting data packets containing high priority 802.1p tags. This causes the VoIP and PC (data) packets to both be tagged as high priority and hence, there is no differentiation between them. Acceptable QoS for the voice traffic can no longer be guaranteed. Priority re-mapping is available on the KSZ8873/8863 family of ports. Each ingress port can be set as specified in the User Priority Bits in the port registers control 3. If the incoming packets 802.1p priority field is greater than the user defined value in the User Priority Bits in the port register control 3, then the packets priority field is replaced with the user defined value in the User Priority Bits. Priority re-mapping is enabled using the User Priority Field (Ceiling) bit in the port register control 1 bit 3 as shown in Table 3.


June 2011 4 M9999-060811-A

DSCP (DiffServ-based) Priority The KSZ8873/8863 devices support DiffServ-based priority in IPv4 and IPv6 IP packets. In this note, IPv4 packets are used as an example. The differentiated service code point (DSCP) priority operates in the Layer 3, IP protocol. The IP datagram header is embedded within the Ethernet data field (see Figure 2). The DSCP priority bits are located inside the type of service (TOS) field, within the standard IPv4 header. The IPv4 header is shown below in more detail. The TOS byte is the second byte located after the header length field (HLEN).

0 4 8 15 16 19 24 31

Version HLEN Type of Service Total Length Identification Flags Fragment Offset

Time to Live Protocol Header Checksum Source IP Address

Destination IP Address IP Options (if any) Padding

Figure 2. Format of IPv4 Datagram Header

Bits 0 to 5 of the ToS field are then taken and fully decoded in 64 separate QoS service codes as shown in Figure 3.

0 5 6 7

DS Field, DSCP ECN Field

DSCP: Differentiated Services Code Point ECN: Explicit Congestion Notification (Unused)

Figure 3. Differential Services (DS) Code Point within the ToS Field of an IP Datagram

The Differentiated Service Code is then compared against the corresponding bit in the Priority Control Registers 0 to 15 (REG96-REG111) of the KSZ8873/8863 devices (8 bits x 16 registers = 128 bits totally). The corresponding 2-bits in REG96-REG111registers stands for one code point of DSCP. 2-Bits have 4 priority levels, where 00 is priority 0, 01 is priority 1, 10 is priority 2 and 11 is priority 3. Using the 128-bits with 2-bit as a DSCP in the TOS Priority Control registers, it is possible to make 64 DSCP code points with 4 priority levels for each DSCP. DSCP priority is enabled using the DiffServ Priority Classification Enable bit 6 in each Port Register Control 0. They are shown in Table 4.

Register Bit Name Description Default Port register control 0 bit 6

6 Diffserv Priority Classification Enable

1 = Enable diffserv priority classification for ingress packets on port. 0 = Disable diffserv priority.

0

Table 4. Registers are used for DiffServ Priority

Note: The ORed result of 802.1p and DSCP priority classification overrides any port priority.


June 2011 5 M9999-060811-A

TOS Register DSCP # (Dec) Bits Priority Level Default 0 [1-0] = 00, 01, 10, 11 0-3 00 1 [3-2] = 00, 01, 10, 11 0-3 00 2 [5-4] = 00, 01, 10, 11 0-3 00

Register 96

3 [7-6] = 00, 01, 10, 11 0-3 00 4 [1-0] = 00, 01, 10, 11 0-3 00 5 [3-2] = 00, 01, 10, 11 0-3 00 6 [5-4] = 00, 01, 10, 11 0-3 00

Register 97

7 [7-6] = 00, 01, 10, 11 0-3 00 8 [1-0] = 00, 01, 10, 11 0-3 00 9 [3-2] = 00, 01, 10, 11 0-3 00 11 [5-4] = 00, 01, 10, 11 0-3 00

Register 98

12 [7-6] = 00, 01, 10, 11 0-3 00 13 [1-0] = 00, 01, 10, 11 0-3 00 14 [3-2] = 00, 01, 10, 11 0-3 00 15 [5-4] = 00, 01, 10, 11 0-3 00

Register 99

16 [7-6] = 00, 01, 10, 11 0-3 00 17 [1-0] = 00, 01, 10, 11 0-3 00 18 [3-2] = 00, 01, 10, 11 0-3 00 19 [5-4] = 00, 01, 10, 11 0-3 00

Register 100

20 [7-6] = 00, 01, 10, 11 0-3 00

. . . . .

. . . . .

. . . . .

. . . . . 56 [1-0] = 00, 01, 10, 11 0-3 00 57 [3-2] = 00, 01, 10, 11 0-3 00 58 [5-4] = 00, 01, 10, 11 0-3 00

Register 110

59 [7-6] = 00, 01, 10, 11 0-3 00 60 [1-0] = 00, 01, 10, 11 0-3 00 61 [3-2] = 00, 01, 10, 11 0-3 00 62 [5-4] = 00, 01, 10, 11 0-3 00

Register 111

63 [7-6] = 00, 01, 10, 11 0-3 00

Table 5. Registers are used for 64 DSCP Priority Level Settings

All Priority Control Registers (REG96 REG111) are as shown in Table 5 for detail priority levels. For example, If DSCP=001000 (Bin) = 8 (Dec) in IP TOS field, this implies that TOS Priority Control Register 98, bits 1-0 will be examined, and the priority of those bits will set as the priority level of the packets.


June 2011 6 M9999-060811-A

Ingress Rate limit for Priority There are 0-3 four priority levels for Port based, 802.1p based and DiffServ based priorities for the ingress packets. The register 22/38/54 bits [6-0] are for priority 0 ingress packets rate limit. The register 23/39/55 bits [6-0] are for priority 1 ingress packets rate limit. The register 24/40/56 bits [6-0] are for priority 2 ingress packets rate limit. The register 25/41/57 bits [6-0] are for priority 3 ingress packets rate limit. The rate step is 64Kbps when the rate limit is less than 1Mbps, the rate step is 1Mbps when the rate limit is from 1Mbps to 10Mbps (10BT) and 1Mbps to 100Mbps (100BT). Please refer to Data Rate Limit Table 6 below.

100BT Register bit[6:0]

10BT Register bit[6:0]

0x01 to 0x63 for the Rate 1Mbps to 99Mbps.

0x01 to 0x09 for the rate 1Mbps to 9Mbps

Data Rate Limit for ingress or egress

0 or 0x64 for the rate 100Mbps

0 or 0x0A for the rate 10Mbps

The rate steps below are used less than 1Mbps Hex value for register bit[6:0] 64 Kbps 0x65 128 Kbps 0x66 192 Kbps 0x67 256 Kbps 0x68 320 Kbps 0x69 384 Kbps 0x6A 448 Kbps 0x6B 512 Kbps 0x6C 576 Kbps 0x6D 640 Kbps 0x6E 704 Kbps 0x6F 768 Kbps 0x70 832 Kbps 0x71 896 Kbps 0x72 960 Kbps 0x73

Table 6. Data Rate Limit Table

For ingress rate limiting, KSZ8873/8863 provides options to selectively choose frames from all types, multicast, broadcast, and flooded unicast frames. The KSZ8873/8863 counts the data rate from those selected type of frames. Packets are dropped at the ingress port when the data rate exceeds the specified rate limit.

Register Bit Name Description Default Port register control 5 bit 3-2

3-2 Limit mode Ingress Limit Mode These bits determine what kinds of frames are limited and counted against ingress rate limiting. = 00, limit and count all frames = 01, limit and count Broadcast, Multicast, and flooded unicast frames = 10, limit and count Broadcast and Multicast frames only = 11, limit and count Broadcast frames only

00

Table 7. Limit Mode Select


June 2011 7 M9999-060811-A

Egress Rate limit for Priority Queues There are 0-3 four priority levels for Port based, 802.1p based and DiffServ based priorities for 4 queues of egress packets. On the transmit side, the data transmit rate for each priority queue at each port can be limited by setting up Egress Rate Control Registers. The register 154/158/162 bits [6-0] are for priority 0 egress packets rate limit at transmit queue Q0. The register 155/159/163 bits [6-0] are for priority 1 egress packets rate limit at transmit queue Q1. The register 156/160/164 bits [6-0] are for priority 2 egress packets rate limit at transmit queue Q2. The register 157/161/165 bits [6-0] are for priority 3 egress packets rate limit at transmit queue Q3. The rate step is same as Table 6 and description above. The port register 154/158/162 bit 7 should be set to take effect for the egress packets rate limit.

Register Bit Name Description Default Port register 154/158/162 bit 7

7 Egress Rate Limit Flow Control Enable

1 = Enable egress rate limit flow control 0 = Disable

0

Table 8. Enable Egress Rate Limit Flow Control

Conclusion The KSZ8873/8863 family of switches is ideal for handling Quality of Service requirements. With emerging applications such VoIP and Video Broadcasting, the network must be ready to handle different type of services in a cost effective manner. The KSZ8873/8863 also provides a fine resolution rate limiting at different priority levels for ingress and egress packets. The network should be designed with an end-to-end QoS capability for the future. As shown in this paper, Micrels Ethernet product family of switches provides a rich set of QoS functionality to meet the needs for emerging triple play applications.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its

use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical

implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchasers use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchasers own risk and Purchaser agrees to

fully indemnify Micrel for any damages resulting from such use or sale.

2011 Micrel, Incorporated.

KSZ8873MLL_FLL_RLL_DP1.5/App Note/App Note-RMII Connections for KSZ8863RLL_73RLL.pdf

Mxxxx-083011 August 2011

Application Note

RMII Connections for

KSZ8863RLL and KSZ8873RLL

IntroductionThe KSZ8863RLL and KSZ8873RLL are a highly integrated Layer 2 managed 3-port switch, Port 3 of KSZ8863RLL and KSZ8873RLL support MAC3 RMII interface. In this app note, we describe RMII interface connections in the different modes and applications for the KSZ8863RLL and KSZ8873RLL.

RMII clock connection For pins (SPIQ, SMTXD2, and SMTXD3) with internal pull-up, the external pull-up resistor can be removed if the pin request to have logic one. Pull-up and pull-down In the figures below, all pull-up request 4.7Kohm pull-up resistors, all pull-down request 1Kohm pull-down resistors. 50 MHz Refclk Input to K8863RLL

X1 SMRXD3 SMTXC SMTXD2 SMTXD3

REFCLK (50 MHz)

K8863RLL

Other Chip

SMTXD2 has internal pull-up SMTXD3 has internal pull-up

Application Note

M9999-083011

2August 2011

50 MHz Output from K8863RLL

X1/X2 SMRXD3 SMTXC SMTXD2 SMTXD3

REFCLK (50 MHz)

K8863RLL

Other Chip

25 MHz


X1/X2 SMRXD3 SMTXC SMTXD2 SMTXD3

REFCLK (50 MHz)

K8863RLL

Other Chip

50 MHz


Application Note

M9999-083011

3August 2011

50 MHz Refclk Input to K8873RLL

50 MHz Output from K8873RLL

X1/X2 SMRXD3 SMTXC SPIQ SMTXD3

REFCLK (50 MHz)

K8873RLL

Other Chip

50 MHz

SPIQ has internal pull-up SMTXD3 has internal pull-up

X1 SMRXD3 SMTXC SPIQ SMTXD3

REFCLK (50 MHz)

K8873RLL

Other Chip


Application Note

M9999-083011

4August 2011

Conclusion By the above describes for the KSZ8863RLL and KSZ8873RLL, we have known KSZ8863RLL and KSZ8873RLL support both providing 50MHz RMII reference clock and receiving 50MHz RMII reference clock, They can be used flexible in RMII connection for data transfer between microprocessors to Ethernet switch MAC layer. The reduced pin count MII interface can be used widely in current new products and your Ethernet applications. For the detail device information, please see their datasheets in www.micrel.com

MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended

for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchasers use or sale of Micrel Products for use in life support appliances, devices or systems is a

Purchasers own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.

2011 Micrel, Incorporated.

X1/X2 SMRXD3 SMTXC SPIQ SMTXD3

REFCLK (50 MHz)

K8873RLL

Other Chip

25 MHz


KSZ8873MLL_FLL_RLL_DP1.5/App Note/Application Note_8863_73 MLL Power2.pdf

Application Note KSZ8873/63 MLL Demo Board Current Consumption Introduction This application note provides the procedure required to measure the power of the 8873/63MLL in 4 modes of operation using the KSZ8873/63/MLL/FLL/RLL Demo board. The numbers reported on the data sheet are typical numbers. The current numbers actually measured can vary up to +- 10% from those reported on the data sheet due to process variation. Also note that the data sheet numbers are at 25C and nominal voltage These numbers are useful in creating a power budget and designing the power circuit Operation and Measurement conditions The KSZ8873/63MLL operates using 3 different voltage inputs as listed below:

- VDDIO can be 3.3, 2.5 or 1.8V (3.3V is used for this AN) - VDDA_3.3 is the analog 3.3V input - VDDC powers the internal digital core and must be 1.8V - VDDA_1.8 is the analog 1.8 input

Note the part has one on board 1.8V regulator that can supply both 1.8V inputs. This regulator output is called VDDCO. All measurements assume the onboard regulator is used. The tests below will describe the voltage measurement under 5 conditions

- 100BT running traffic on port 1, port 2 and port 3 - 10BT running traffic on port 1, port 2 and port 3 - Power saving mode - Soft power down mode - Energy Detect mode

See KSZ8873/63MLL_FLL_RLL data sheet for explanation of power modes Test Equipment Required

- 8873/63MLL/FLL/RLL Evaluation board kit. Including Evaluation board populated with 8873/63MLL

- PC with USB port and Win2000/XP operating system - Micrel Switch Configuration SW installed onto your PC - USB cable - 5 Volt power supply provided with Evaluation kit - Fluke 173 Multi-meter or similar, need 2

General Setup Figure 1 shows the overall setup. Figure 2 shows the power detail. Table 1 shows the jumper configurations. Power to the part is isolated as 3.3V and 3.3A and is measured across JP 404 and 403 respectively. Register setting are default except as otherwise noted below.

Figure 1. General Setup

Figure 2. Power measurement detail

Jumper(JP) Pin to Pin Comments 405 1 2 40 1 2 30 1 2 12 4 3 13 1 2

2 3 MII MAC mode 26(Only for KSZ8873)

1 2 MII PHY mode

34 1 2 35 1 2 21 1 2 25 2 3 5 1 1

external TP6 JP27-3 Need to tie TXEN low since non PHY tied to

MII connector Table 1. Jumper setting in Evaluation Board (All other jumper open except listed in the table)

Measurement in 100/10 Base TX all Ports Linked at 100% Line-Rate Normal operating Register 0xC3=0x00 MII in MAC mode (register 0x35 bit 7 =1) Switch clock = 31.25MHz (register 0x0B bit [7:6] = [0,0]) CPU interface clock = 31.25MHz (register 0x0B bit [5:4] = [0,0])

1. Connect the Evaluation Board to the Smartbits as below

Figure 3. System connection

KSZ8873/63 Evaluation Board Port 1 Port 2 Port 3(MII)

KSZ8041 Evaluation Board

Port 1 Port 2 Port 3 Smartbits Tester

2. Set up the Smartbits as below:

Port 1 Port 2 Port 3

Figure 4. Smartbits setup

Transmit Mode: Single Burst 10,000 Data Length : Random Load (IPG) : 100% (0.96uS) Background : Random

3. Results:

KSZ8863 KSZ8873 100 Base 108mA (112mA in DS) 105mA (123mA in DS) 10 Base 78mA (92mA in DS) 78mA (88mA in DS)

Measurement in Power Saving Mode Register 0xC3=0x03 100BT with auto-negotiation enable MII in MAC mode (register 0x35 bit 7 =1) Switch clock = 31.25MHz (register 0x0B bit [7:6] = [0,0]) CPU interface clock = 31.25MHz (register 0x0B bit [5:4] = [0,0]) Results: KSZ8863 KSZ8873 No Cable on All ports 84 mA (89mA in DS) 80mA (90mA in DS) Only port 1 connected 95 mA 89mA Only port 2 connected 92 mA 89mA Both port 1 and port 2 connected

105 mA 99mA

Measurement in Soft Power Down Mode Register 0xC3 =0x02 Result: KSZ8863 KSZ8873 8.7mA (6.2mA in DS) 6.5mA (6.5mA in DS) Measurement in Energy Detect Mode Register 0xC3=0x05 100BT with auto-negotiation enable MII in MAC mode (register 0x35 bit 7 =1) Switch clock = 31.25MHz (register 0x0B bit [7:6] = [0,0]) CPU interface clock = 31.25MHz (register 0x0B bit [5:4] = [0,0]) KSZ8863 KSZ8873 Switch

OFF(24s) Switch ON(8s)

Average Switch OFF(24s)

Switch ON(8s)

Average

No Cable on All ports

48 mA 66 mA 53 mA 44mA 62mA 46mA

Only port 1 connected

68 mA 87 mA 73 mA 62mA 80mA 67mA

Only port 2 connected

66 mA 84 mA 71 mA 63mA 81mA 68mA

Both port 1 and port 2 connected

84 mA 106 mA 106 mA 81mA 99mA 86mA

Register 0xC3=0x05 100BT with auto-negotiation enable MII in PHY mode (register 0x35 bit 7 =0), SMTXER3 connect to HIGH

Switch clock = 31.25MHz (register 0x0B bit [7:6] = [0,0]) CPU interface clock = 31.25MHz (register 0x0B bit [5:4] = [0,0])

KSZ8863 KSZ8873 Switch is

OFF(24s)/ON(8s) Switch is OFF(24s)/ON(8s)

No Cable on All ports 17/69mA (Off/On) 30mA(average) (42mA in DS)

10/63mA (Off/On) 24mA(Average) (35mA in DS)

Only port 1 connected 92mA 85mA Only port 2 connected 89mA 86mA Both port 1 and port 2 connected

110mA 104mA

KSZ8873MLL_FLL_RLL_DP1.5/Board User Guide/KS8873MLL_FLL_RLL Eval Board User's Guide v1.1.pdf

Micrel, Inc. 1849 Fortune Drive San Jose, CA 95131 U.S.A.

408-955-0800 (voice) 408-955-1577 (fax) http://www.Micrel.com

KSZ8873MLL/FLL/RLL Evaluation Board Users Guide KSZ8873MLL/FLL/RLL Integrated 3-Port 10/100 Managed Switch with PHYs Revision 1.1 January 2011

Micrel, Inc. 2011 All rights reserved

Micrel is a registered trademark of Micrel and its subsidiaries in the

United States and certain other countries. All other trademarks are the property of their respective owners.

The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.

KSZ8873MLL/FLL/RLL Evaluation Board Users Guide

Micrel, Inc. January 11, 2011 Confidential Rev. 1.1

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Revision History

Revision Date Summary of Changes

1.0 06/30/09 Initial Release

1.1 01/11/11 Update description



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Table of Contents 1.0 Introduction ............................................................................ 4 2.0 Board Features....................................................................... 4 3.0 Evaluation Kit Contents......................................................... 4 4.0 Hardware Description ............................................................ 4

4.1 Strap In Mode .......................................................................................................... 5 4.1.1 Feature Setting Jumpers........................................................................... 6

4.2 I2C Master (EEPROM) Mode .................................................................................. 7 4.3 SPI Slave Mode ....................................................................................................... 8 4.4 10/100 Ethernet PHY Ports (KSZ8873MLL/RLL) .................................................. 9 4.5 100FX Fiber Port (KSZ8873FLL) ............................................................................ 9 4.6 LED Indicators......................................................................................................... 9 4.7 MII Port Configuration (KSZ8873MLL/FLL) .......................................................... 9 4.8 RMII Port Configuration (KSZ8873RLL).............................................................. 10

5.0 Reference Documents ......................................................... 10

List of Tables Table 1: Feature Setting Jumpers .................................................................................................. 6 Table 2: Reserved Jumpers ............................................................................................................ 7 Table 3: EEPROM Mode Settings ................................................................................................... 8 Table 4: SPI Slave Mode Settings................................................................................................... 8 Table 5: LED Modes....................................................................................................................... 9 Table 6: RMII Clock Setting........................................................................................................... 10

List of Figures Figure 1: KSZ8873MLL/FLL/RLL Evaluation Board Block Diagram .............................................. 5



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1.0 Introduction The KSZ8873MLL/FLL/RLL is Micrels third generation fully integrated 3-port switch. The two PHY units of KSZ8873MLL/RLL support 10BASE-T and 100BASE-TX. The KSZ8873FLL supports 100BASE-FX. The devices have been designed for cost sensitive systems, however, still offer a multitude of features, such as switch management, port and tag based VLAN, QoS priority, one MII interfaces and CPU control and data interfaces.

The KSZ8873MLL/FLL/RLL is an excellent choice for VoIP Phone, Set-top/Game Box, SOHO Residential Gateway, industrial Ethernet systems and as a standalone 3-port switch. The KSZ8873MLL/FLL/RLL Evaluation Board provides a convenient means to evaluate the KSZ8873MLL/FLL/RLLs rich feature set. Easy access is provided to all of the KSZ8873MLL/FLL/RLL pins, with jumpers and interface connectors allowing quick configuration and re-configuration of the board. MIIM, EEPROM programming, SPI emulation software are also provided to access the more extensive features of the KSZ8873MLL/FLL/RLL, via a PC USB port.

2.0 Board Features

Micrels KSZ8873MLL/FLL/RLL Integrated 3-Port 10/100 Managed Ethernet Switch

Two RJ-45 Jacks for Ethernet LAN Interfaces with corresponding Isolation Magnetics (KSZ8873MLL/RLL)

Auto MDI/MDI-X on the PHY port

1 PHY Mode and 1 MAC Mode MII Connectors for the Switch RMII/MII Interface

2 100Base-FX fiber interface(KSZ8873FLL)

1 USB port to emulate an MIIM, EEPROM, SPI Interface

On board EEPROM

2 LEDs per port to Indicate the Status and Activity of the RJ45 port

1 power jack for 5VDC Universal Power Supply

3.0 Evaluation Kit Contents The KSZ8873MLL/FLL/RLL Evaluation kit includes the following:

KSZ8873MLL/FLL/RLL Evaluation Board Revision 1.0


Micrel Switch Configuration Software Version 1.0.5

Micrel Switch Configuration Software User Guide

KSZ8873MLL/FLL/RLL Evaluation Board Schematic Revision 1.0 (Contact your Micrel FAE for the latest schematic)

Note: USB cable and 5V DC Wall Power Supply is not included in the design kit (the dimension of the output plug of 5V DC wall power supply is 2.5x5.5x9.5mm or 0.1x0.218x0.375inch)

4.0 Hardware Description The KSZ8873MLL/FLL/RLL Evaluation Board is in a compact form factor and can sit on a bench near a computer. There are three options for configuration: strap in mode, EEPROM mode, and SPI mode. Strap in mode configuration is easily done with on board jumper options. EEPROM mode and SPI mode are accomplished through a built in USB port interface. With the Micrel software and your PC, you can use the USB port to reprogram the EEPROM on board, or use the SPI interface to access the KSZ8873MLL/FLL/RLLs full feature set. The board also features one



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MII connector for the Switch MII interface. It is to facilitate connection from the switch to either the external CPU or the external PHY.

Figure 1: KSZ8873MLL/FLL/RLL Evaluation Board Block Diagram

The KSZ8873MLL/FLL/RLL evaluation board is easy to use. There are programmable LED indicators for link and activity on the PHY ports and a power LED. A manual reset button allows the user to reset the board without removing the power plug. The 5V power on the board can be supplied by a standard 5VDC power supply (close pin 1-2 of JP400 jumper) or by the USB cable (close pin 2-3 of JP400 jumper) which is used to access the registers in SPI mode. A standard 5VDC power supply is included so that the user can supply power from any 110 Volt AC wall or bench socket. Before to start to use the evaluation board, make sure the power connectors JP403, JP404, JP405 and JP31 are connected, and close pin 1-2 of J14.

4.1 Strap In Mode Strap in configuration mode is the quickest and easiest way to get started. In this mode, the KSZ8873MLL/FLL/RLL acts as a standalone 3-port switch. Simply set the boards configuration jumpers to the desired settings and apply power to the board. The configuration can be changed while power is applied to the board by changing the jumper settings and pressing the convenient manual reset button for the new settings to take effect. Note that even if no external strap in values are set, internal pull up and pull down resistors will set the KSZ8873MLL/FLL/RLL default configuration. Section 4.1.1 covers each jumper on the board and describes its function. To start in strap in configuration mode, make sure that the USB cable is unplugged, JP34, JP35, JP3 and JP9 are connected, JP21, JP25 have jumpers fitted between pins 2 to 3.



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4.1.1 Feature Setting Jumpers The evaluation board provides jumpers to allow easy setting of strap in configurations for the KSZ8873MLL/FLL/RLL. Table 1 describes the jumpers and their functionalities.

Table 1: Feature Setting Jumpers

JUMPER KSZ8873MLL/FLL/RLL SIGNAL

OPEN CLOSED

JP3 SPIQ SPI EEPROM

JP25 P2LED0 EEPROM/SPI Setting. See Section 4.2 and 4.3

JP21 P2LED1 EEPROM/SPI Setting. See Section 4.2 and 4.3

JP26 SMRXDV3 P3 MII Setting. Pull Up: PHY mode, Pull Down: MAC mode

JP78 FXSD1 Pins 1-2 closed : Disable FEF feature of FX. Pins 5-6 closed : Force port 1 TX mode For KSZ8873MLL/RLL, close 5-6 since this device doesnt support FX mode. For KSZ8873FLL, open JP77

JP77 FXSD2 Pins 1-2 closed : Disable FEF feature of FX. Pins 5-6 closed : Force port 1 TX mode For KSZ8873MLL/RLL, close 5-6 since this device doesnt support FX mode. For KSZ8873FLL, open JP77

JP2 PWRDN Normal Operation KSZ8873MLL/FLL/RLL Chip Power Down

JP101

P1FFC Pull Down = Disable Pull Up(default) = Enable

JP102

P1DPX Pull Down = Half Duplex Pull Up(default) = Full Duplex

JP103

P1SPD Pull Down = 10BT Pull Up(default) = 100BT

JP104 P1ANEN Pull Down = Disable Pull Up(default) = Enable

JP201

SMRXD30(P2FFC) Pull Down = Disable Pull Up(default) = Enable

JP202

SMRXD31(P2DPX) Pull Down = Half Duplex Pull Up(default) = Full Duplex

JP203

SMRXD32(P2SPD) Pull Down = 10BT Pull Up(default) = 100BT

JP204

SMRXD33(P2ANEN) Pull Down = Disable Pull Up(default) = Enable

JP301

P1LED1(P3FFC) Pull Down = Disable Pull Up(default) = Enable

JP302

P1LED0(P3DPX) Pull Down(default) = Full Duplex Pull Up = Half Duplex

JP303

P3SPD Pull Down(default) = 100BT Pull Up = 10BT

JP304

SPIQ(XCLK) Pull Down = 50MHz Pull Up(default) = 25MHz

Note: JP101, JP102, JP103, JP201, JP202, JP203 are only valid if Auto-Negotiation is disabled.



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The following table shows the recommended settings for the evaluation board reserved jumpers.

Table 2: Reserved Jumpers

JUMPER Description Recommended Setting

JP79 MDC_PHY,MDIO_PHY Open

JP27 P3 MII configuration (For test only)

Open

JP30 3.3V Biased of transformer Center (For test only)

Open

JP11 Power for Fiber Module. (Port 2)

KSZ8873MLL/RLL: Open For KSZ8873FLL: Close pin 1-2 for 3.3V Fiber Module. Close pin 3-2 for 5.0V Fiber Module.

JP10 Power for Fiber Module. (Port 1)

KSZ8873MLL/RLL: Open For KSZ8873FLL: Close pin 1-2 for 3.3V Fiber Module. Close pin 3-2 for 5.0V Fiber Module.

JP28 REFCLKO3 enable.

KSZ8873MLL/FLL: Open KSZ8873RLL: Close pin 1-2: Enable REFCLKO Close pin 2-3: Disable REFCLKO

4.2 I2C Master (EEPROM) Mode

The evaluation board has an EEPROM to allow the user to explore more extensive

capabilities of the KSZ8873MLL/FLL/RLL. The user can conveniently program the

EEPROM on board using the USB port from any computer with a WIN 2000/XP

environment and the Micrel provided software. This makes it easy for the user to

evaluate features like broadcast storm protection and rate control.

To prepare the KSZ8873MLL/FLL/RLL evaluation board for EEPROM configuration

follow these steps:

1. Install the Micrel Switch Configuration Software to your computer. 2. Set JP3, JP9, JP21, JP25, JP34 and JP35 as specified in Table 3 for EEPROM mode

configuration. Make sure that the EEPROM is installed on the board.

3. Connect the computers USB port to the KSZ8873MLL/FLL/RLL board with a USB port cable.

4. There are two way to power up the evaluation board:

a). Connect the 5 VDC power supply to the KSZ8873MLL/FLL/RLL when JP400

pin1-2 is closed.

b). 5 VDC power source from the USB port when JP400 pin 2-3 is closed.



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5. The KSZ8873MLL/FLL/RLL will power up in its default configuration if there is no information in the EEPROM.

6. Click the software icon to invoke the software to program the desired settings into the EEPROM. See the Micrel Switch Configuration Software User Guide for details.

7. Press the manual reset button. The KSZ8873MLL/FLL/RLL will reset and read the new configuration in the EEPROM. After reset, the KSZ8873MLL/FLL/RLL is ready for normal operation.

Table 3: EEPROM Mode Settings

Jumper Description Setting

JP9 SPIQ Closed

JP3 SCL_MDC_SW Closed

JP34 SCL_MDC Closed

JP35 SDA_MDIO Closed

JP25 Serial Bus Config. (P2LED0) Pins 2-3 closed


4.3 SPI Slave Mode

From SPI interface to the KSZ8873MLL/FLL/RLL, use a USB to SPI converter that

allows accessing all of the KSZ8873MLL/FLL/RLL features and registers. The user can

easily access the SPI interface using a computer connected to the evaluation boards USB

port interface. Micrel provides a Windows 2000/XP based program for the user to

evaluate the KSZ8873MLL/FLL/RLLs full feature set. In addition to all the registers

available via EEPROM programming, a host CPU connected to the

KSZ8873MLL/FLL/RLLs SPI interface will be able to access all static MAC entries, the

VLAN table, dynamic MAC address table and the MIB counters.

To prepare the KSZ8873MLL/FLL/RLL evaluation board for SPI mode

configuration follow these steps:

1. Install the Micrel Switch Configuration Software on your computer.

2. Set JP3, JP9, JP21, JP25, JP34 and JP35 as specified in Table 4 for SPI mode

configuration.

Table 4: SPI Slave Mode Settings

Jumper Description Setting

JP9 SPIQ Open

JP3 SCL_MDC_SW Open

JP34 SCL_MDC Closed

JP35 SDA_MDIO Closed



3. Connect the computers USB port to the KSZ8873MLL/FLL/RLL board with a



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USB port cable.

4. There are two way to power up the evaluation board: a). Connect the 5 VDC power supply to the KSZ8873MLL/FLL/RLL when JP400

pin1-2 is closed.

b). 5 VDC power source from the USB port when JP400 pin 2-3 is closed.

5. The KSZ8873MLL/FLL/RLL will power up in its default configuration 6. Click the software icon to invoke the software to program the desired settings.

See the Micrel Switch Configuration Software User Guide for details.

4.4 10/100 Ethernet PHY Ports (KSZ8873MLL/RLL) There are two 10/100 Ethernet PHY ports on the KSZ8873MLL/RLL evaluation board. The ports can be connected to an Ethernet traffic generator or analyzer via standard RJ-45 connectors using CAT-5 cables. Each port can be used as either an uplink or downlink. Both ports support auto MDI/MDI-X, eliminating the need for cross over cables.

4.5 100FX Fiber Port (KSZ8873FLL) There are two 100FX PHY ports on the KSZ8873FLL evaluation board. The ports can be connected to an Ethernet traffic generator or analyzer via fiber transceiver and fiber cable. The fiber signal threshold can be set by register 192 bit 6(Port1) and bit 7(Port2). If the bits are 1, the threshold will be set to 2.0V, Otherwise it is 1.25V.The resister R76 also need to be adjusted if the FXSD signal value from the fiber module doesnt meet the fiber signal threshold spec.

4.6 LED Indicators There is one column of LED indicator for one column for port 2. The LED indicators are programmable to three different modes. LED mode is selected through register 195 bit [5:4] setting. The LED mode definitions are specified in Table 5. See Figure 1 for the LEDs orientation on the KSZ8873MLL/FLL/RLL evaluation board.

Table 5: LED Modes

Register 195 Bit[5:4]

00 01 10 11

PxLED1 = Speed PxLED1 = Active PxLED1 = Duplex PxLED1 = Duplex

PxLED0 = Link/Active PxLED0 = Link PxLED0 = Link/Active PxLED0 = Link

The KSZ8873MLL/FLL/RLL evaluation board provides two LEDs (PxLED1, PxLED0) for each PHY port. The KSZ8873MLL/FLL/RLL evaluation board also has a power LED (D3) for the 3.3V power supply. When D3 is lit, the boards 3.3V power supply is on.

4.7 MII Port Configuration (KSZ8873MLL/FLL) The evaluation board provides access to the KSZ8873MMLs MAC via the MII port interfaces. The MAC can be configured to MII PHY mode and MII MAC mode. To configure the MAC, the boards jumpers JP27 is set as specified in Table 6.



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Table 6: MII Mode Settings

MII Mode MII PHY mode MII PHY mode

JP27 for Port 1 Pins 1-2 closed Pins 2-3 closed

In MII PHY mode, the MII transmit and receive signals will be on J3, the male MII port connectors. This mode is usually used to connect the KSZ8873MML to an external MAC processor. In MII MAC mode, the MII transmit and receive signals will be on J4, the female MII port connector. This interface is normally used to connect the KSZ8873MML to an external PHY, for example the Micrel KSZ8041NL.

4.8 RMII Port Configuration (KSZ8873RLL) In RMII interface, the 50MHz reference clock can be provide by the KSZ8873RLL or by the link partner. When pin 1-2 of JP28 is closed, the reference clock will be output from REFCLKO on KSZ8873RLL. Register 198 bit[3] is used to select internal or external reference clock for the KSZ8873RLL RMII interface. If pin 2-3 of JP28 is closed, the REFCLKO disable.

Table 7: RMII Clock Setting

5.0 Reference Documents KSZ8873MLL/FLL/RLL Datasheet Rev. 1.1 (Contact Micrel for latest Datasheet) KSZ8873MLL/FLL/RLL Evaluation Board Schematic Rev. 1.0 (Contact Micrel for latest Schematic) KSZ8873MLL/FLL/RLL Evaluation Board Gerber files Micrel Switch Configuration Software User Guide

Reg198[3] EN_REFCLKO_3 Clock Source Note

0 0 External 50MHz OSC input to REFCLKI_3

EN_REFCLKO_3 = 0 to Disable REFCLKO_3 for better EMI

0 1 REFCLKO_3 Output Is Feedback to REFCLKI_3

EN_REFCLKO_3 = 1 to Enable REFCLKO_3

1 1 Internal Clock Source

REFCLKI_3 is unconnected

EN_REFCLKO_3 = 1 to Enable REFCLKO_3

1 0 Not suggest

KSZ8873MLL_FLL_RLL_DP1.5/BOM/KSZ8873FLL_USB_BOM_V1.0_100509_ALL.xlsSheet1

KSZ8873FLL DEMO BOARD Revision: 1.0 April 1, 2009

MICREL SEMICONDUCTOR

All components must be Lead free / RoHS compliant

DNI = DO NOT INSTALL

DNI the components in RED colour

Bill Of Materials

ItemQTYReferenceValue / SizeMfgMfg part #Digi-key PartDNI

11CN1CN-USBRight Angle, Thru-Hole USB ConnectorAMP292304-1, Series B

22C1,C218PFPanasonic - ECGECJ-2VC1H180JPCC180CNCT-ND

37C4,C5,C6,C11,C68,C70,C9610uFAVX CorporationTAJB106K020R478-1674-1-ND

42C9,C661000PF / 2KVPanasonic - ECGECK-A3D102KBPP9565-NDDNI

545C10,C12,C13,C15,C16,C17,0.1UF 0603KemetC0603C104J4RACTU399-1097-1-ND

C18,C19,C20,C21,C22,C23,

C24,C25,C26,C30,C31,C33,

C34,C35,C36,C37,C38,C39,

C67,C69,C93,C94,C95,C97,

C100,C101,C102,C103,C106,

C107,C109,C110,C111,C112,

C114,C115,C116,C117,C118

62C14,C3247UF / 16VAVX CorporationTAJD476K016R478-1739-1-ND

73C71,C98,C1130.01uFPanasonic - ECGECJ-2VB1H103KPCC103BNCT-ND

82C87,C881000pf/2KVPanasonic - ECGECK-A3D102KBPP9565-ND

92C104,C10547pF 0603

101C10833nFYageoCC1206KRX7R9BB332311-1172-2-ND

117C123,C127,C130,C132,C133,100UF / 16VAVX CorporationTAJD107K016RNJ478-1723-2-ND

C135,C136

124C124,C128,C131,C13422UF / 20VAVX CorporationTAJB226K020R478-1683-1-ND

131C144470UF/16VPanasonicECA-1CM471Digi-key

141D21N4148 DIODE/400Fairchild1N41481N4148FS-ND

154D5,D6,D9,D10PLC03-3.3 8SOICBournsCDNBS08-PLC03-3.3DNI

164D7,D8,D11,D12SR3.3 IC SOT-143SemtechSR3.3.TCTDNI

171D13POWER LEDPanasonic - SSGLN28RCPXP606-ND

182D14,D15LED 3MM RA 2-HI GRN/GRN PC MNTLumex Opto/Components IncSSF-LXH240GGD67-1321-ND

1918X1,TP1,EXT_V1,X2,TP2,TestPoint

Ext_V2,TP3,TP4,TP5,TP6,

TP7,TP8,TP9,TP10,TP21,

TP22,TP23,TP24

2013FB3,FB4,FB5,FB6,FB7,FB12,FERRITE 6A 50 OHM 1206StewardHI1206T500R-10240-2412-1-ND

FB13,FB16,FB19,FB20,FB21,

FB22,FB23

2112JP2,JP32,JP33,JP34,JP35,2X1

JP403,JP404,JP405,JP30,

JP31,JP40,JP41

222JP3,JP9JP

2319JP10,JP11,JP21,JP25,JP26,3X1

JP27,JP28,JP101,JP103,JP104,

JP201,JP202,JP203,JP204,JP303,

JP304,JP301,JP302,JP102

241JP4003X1

252JP77,JP78HEADER 4X2

262J1,J2RJ45 ConnertorTyco5558342-1A31466-NDDNI

271J3Male MII ConnectorTaiwan/Goal RayMDS-40M/M-5-C1 new part: MDS-40M/M-3-C2

281J4Female MII ConnectorTyco5787170-4A31806-NDDNI

291J55X1

301J11POWER JACKSwitchcraft Inc.RAPC712XSC237-ND

312J12,J13CON4A

321J143X1

337R1,R5,R7,10K 0603Panasonic - ECGERJ-3EKF1002VP10.0KHCT-ND

R190,R192,R193,R194

341R411.8K 1% 0603Panasonic - ECGERJ-3EKF1182VP11.8KHTR-ND

3525R6,R9,R11,R108,R109,R110,1K 0603Panasonic - ECGERJ-3EKF1001VP1.00KHCT-ND

R112,R113,R114,R115,R116,

R117,R119,R121,R123,R125,

R127,R129,R131,R133,R191

3623R15,R2144.7K 0603

R8,R10,R12,R13,

R100,R101,R102,R103,R104,

R105,R106,R107,R111,R118,

R120,R122,R124,R126,R128,

R130,R132,

3712R18,R19,R21,R23,R24,R25,51 0603Panasonic - ECGERJ-3EKF51R1VP51.1HCT-NDDNI

R171,R174,R183,R184,R185,

R186

382R20,R17275 0603Panasonic - ECGERJ-3EKF75R0VP75.0HCT-NDDNI

3937R22,R26,R27,R28,R37,R38,49.9 1% 0603Panasonic - ECGERJ-3EKF49R9VP49.9HCT-ND

R39,R40,R41,R42,R43,R44,

R45,R46,R47,R48,R49,R50,

R51,R52,R53,R54,R55,R62,

R63,R72,R73,R78,R84,R85,

R90,R173,R175,R176,R177,

R181,R187

405R31,R34,R60,R178,R188220 0603Panasonic - ECGERJ-3EKF2210VP221HCT-ND

4113R56,R57,R58,R164,R199,0

R200,R201,R202,R205,R208,

R210,R211,R213

428R64,R65,R68,R69,R79,R80,82 0603Panasonic - ECGERJ-3EKF82R0VP82.0HCT-ND

R81,R93

4310R66,R67,R70,R71,R77,R82,130 1% 0603Panasonic - ECGERJ-3EKF1300VP130HCT-ND

R87,R88,R89,R92

444R74,R75,R83,R91NC

452R76,R860

461R165470 0603

472R166,R18227 0603

481R1792.49K 1% 0603

491R1801.50K 1% 0603

501R1891.50K 1% 0603

518R195,R196,R197,R198,R206,0

R207,R209,R212

521R21533 0603

531S2SW PUSHBUTTONPanasonic - ECGEVQ-PHP03TP8002SCT-ND

542T1,T2H1102NLPULSEH1102NL553-1323-NDDNI

551U2AT24C02 PDIP + DIP8AATMEL1825093-2 socketAT24C02B-PU for IC

561U4MIC29302WT TO220-5PMicrelMIC29302WT576-1124-ND

572U6,U10AFBR-5803Z (Install the 9X1connector)AVAGOAFBR-5803ZOption for FQLDNI

581U11KSZ8873FLL64PIN-LQFPMicrel

591U18FT2232D USB ControllerFDTI ChipFT2232D768-1010-2-ND

601Y125MHZ CrystalCSA309-25.000MABJ-UB

611Y250.000 MHz +/-50ppm Y-Half sizeOptionalDNI

621Y36MHz CrystalEpson ElectronicCA-301 6.0000M-C:PBFREE

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - SSG

Lumex Opto/Components Inc

Switchcraft Inc.

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Sheet2

Sheet3

KSZ8873MLL_FLL_RLL_DP1.5/BOM/KSZ8873MLL_USB_BOM_V1.0_100509_ALL.xlsSheet1

KSZ8873MLL DEMO BOARD Revision: 1.0 April 1, 2009




DNI all the components in RED colour

Bill Of Materials





42C9,C661000PF / 2KVPanasonic - ECGECK-A3D102KBPP9565-ND


C18,C19,C20,C21,C22,C23,

C24,C25,C26,C30,C31,C33,

C34,C35,C36,C37,C38,C39,

C67,C69,C93,C94,C95,C97,

C100,C101,C102,C103,C106,

C107,C109,C110,C111,C112,

C114,C115,C116,C117,C118




92C104,C10547pF 0603



C135,C136











TP22,TP23,TP24



FB22,FB23

2112JP2,JP32,JP33,JP34,JP35,2X1

JP403,JP404,JP405,JP30,

JP31,JP40,JP41

222JP3,JP9JP

2319JP10,JP11,JP21,JP25,JP26,3X1

JP27,JP28,JP101,JP103,JP104,

JP201,JP202,JP203,JP204,JP303,

JP304,JP301,JP302,JP102

241JP4003X1


262J1,J2RJ45 ConnertorTyco5558342-1A31466-ND



291J55X1


312J12,J13CON4A

321J143X1


R190,R192,R193,R194



R112,R113,R114,R115,R116,

R117,R119,R121,R123,R125,

R127,R129,R131,R133,R191,R167,R168,R169,R170

3623R15,R2144.7K 0603

R8,R10,R12,R13,

R100,R101,R102,R103,R104,

R105,R106,R107,R111,R118,

R120,R122,R124,R126,R128,

R130,R132,


R171,R174,R183,R184,R185,

R186

382R20,R17275 0603Panasonic - ECGERJ-3EKF75R0VP75.0HCT-ND


R39,R40,R41,R42,R43,R44,

R45,R46,R47,R48,R49,R50,

R51,R52,R53,R54,R55,R62,

R63,R72,R73,R78,R84,R85,

R90,R173,R175,R176,R177,

R181,R187


4113R56,R57,R58,R164,R199,0

R200,R201,R202,R205,R208,

R210,R211,R213


R81,R93

4310R66,R67,R70,R71,R77,R82,130 1% 0603Panasonic - ECGERJ-3EKF1300VP130HCT-NDDNI

R87,R88,R89,R92

444R74,R75,R83,R91NC

452R76,R860

461R165470 0603

472R166,R18227 0603

481R1792.49K 1% 0603

491R1801.50K 1% 0603

501R1891.50K 1% 0603

518R195,R196,R197,R198,R206,0

R207,R209,R212

521R21533 0603


542T1,T2H1102NLPULSEH1102NL553-1323-ND



572U6,U10AFBR-5803ZAVAGOAFBR-5803ZOption for FQLDNI

581U11KSZ8873MLL64PIN-LQFPMicrel





Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - SSG


Switchcraft Inc.

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Sheet2

Sheet3

KSZ8873MLL_FLL_RLL_DP1.5/BOM/KSZ8873RLL_USB_BOM_V1.0_100509_ALL.xlsSheet1

KSZ8873RLL DEMO BOARD Revision: 1.0 April 1, 2009




DNI all the components in RED colour

Bill Of Materials





42C9,C661000PF / 2KVPanasonic - ECGECK-A3D102KBPP9565-ND


C18,C19,C20,C21,C22,C23,

C24,C25,C26,C30,C31,C33,

C34,C35,C36,C37,C38,C39,

C67,C69,C93,C94,C95,C97,

C100,C101,C102,C103,C106,

C107,C109,C110,C111,C112,

C114,C115,C116,C117,C118




92C104,C10547pF 0603



C135,C136











TP22,TP23,TP24



FB22,FB23

2112JP2,JP32,JP33,JP34,JP35,2X1

JP403,JP404,JP405,JP30,

JP31,JP40,JP41

222JP3,JP9JP

2319JP10,JP11,JP21,JP25,JP26,3X1

JP27,JP28,JP101,JP103,JP104,

JP201,JP202,JP203,JP204,JP303,

JP304,JP301,JP302,JP102

241JP4003X1


262J1,J2RJ45 ConnertorTyco5558342-1A31466-ND



291J55X1


312J12,J13CON4A

321J143X1


R190,R192,R193,R194



R112,R113,R114,R115,R116,

R117,R119,R121,R123,R125,

R127,R129,R131,R133,R191,167,168,169,170

3623R15,R2144.7K 0603

R8,R10,R12,R13,

R100,R101,R102,R103,R104,

R105,R106,R107,R111,R118,

R120,R122,R124,R126,R128,

R130,R132,


R171,R174,R183,R184,R185,

R186

382R20,R17275 0603Panasonic - ECGERJ-3EKF75R0VP75.0HCT-ND


R39,R40,R41,R42,R43,R44,

R45,R46,R47,R48,R49,R50,

R51,R52,R53,R54,R55,R62,

R63,R72,R73,R78,R84,R85,

R90,R173,R175,R176,R177,

R181,R187


4113R56,R57,R58,R164,R199,0

R200,R201,R202,R205,R208,

R210,R211,R213


R81,R93

4310R66,R67,R70,R71,R77,R82,130 1% 0603Panasonic - ECGERJ-3EKF1300VP130HCT-NDDNI

R87,R88,R89,R92

444R74,R75,R83,R91NC

452R76,R860

461R165470 0603

472R166,R18227 0603

481R1792.49K 1% 0603

491R1801.50K 1% 0603

501R1891.50K 1% 0603

518R195,R196,R197,R198,R206,0

R207,R209,R212

521R21533 0603


542T1,T2H1102NLPULSEH1102NL553-1323-ND



572U6,U10AFBR-5803ZAVAGOAFBR-5803ZOption for FQLDNI

581U11KSZ8873MLL64PIN-LQFPMicrel





Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - SSG


Switchcraft Inc.

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Panasonic - ECG

Sheet2

Sheet3

KSZ8873MLL_FLL_RLL_DP1.5/Errata/KS8873 rev_A2 Errata.pdf

MICREL CONFIDENTIAL Page1 08/02/2013

KSZ8873 Rev.A2 Errata Sheet Dear Customer, The following is the errata for the currently sampling KSZ8873, 3-Port Switch family. The following issues currently exhibited on the Revision-A2 silicon. Item Symptom Comment Solution/Workaround 1 LinkMD not working in the Port 1

Can not get the right LinkMD status in the register.

Will be fixed in next revision

2 The rate will be double with tag insertion

In the egress port rate limiting with tag insertion, the rate will be double


3 MDC/MDIO cant write MIIM register 0 bit 8, 12, 13

Those bits are reserved in current datasheet.


4 RMII transmit timing is out of max delay time specification in the KSZ8873RLL

The data delay time is 18ns, it is doesnt affect to transfer data on RMII


5 Upon reset or warm reset, the start switch bit in Register 1 is cleared to 0 in I2C master mode.

As the result, the switch doesnt work in the I2C master mode.

Workaround solution: Set Register 78 (0x4E) bit 0 = 1 when program the EEPROM. The I2C master mode will work fine.

6 Port 1 Receiving Flow Control doesnt take effect when port 1 receives Pause frame.

As the result, the port 1 still transmit normal packets when receive pause frame.

Workaround solution: Set Register 21 Port 1 Control 5 bit [7] = 1 (this is a reserved bit). Port 1 Receiving Flow Control will work fine.

KSZ8873MLL_FLL_RLL_DP1.5/Gerber/KSZ8873FLL_MLL_RLL_gbr.zip

art004.pho

**G04 PADS Layout (Build Number 2007.21.1) generated Gerber (RS-274-X) file*G04 PC Version=2.1**%IN "81202Capr01.pcb"*%*%MOIN*%*%FSLAX35Y35*%****G04 PC Standard Apertures***G04 Thermal Relief Aperture macro.*%AMTER*1,1,$1,0,0*1,0,$1-$2,0,0*21,0,$3,$4,0,0,45*21,0,$3,$4,0,0,135*%**G04 Annular Aperture macro.*%AMANN*1,1,$1,0,0*1,0,$2,0,0*%**G04 Odd Aperture macro.*%AMODD*1,1,$1,0,0*1,0,$1-0.005,0,0*%**G04 PC Custom Aperture Macros*******G04 PC Aperture Table**%ADD011C,0.008*%%ADD012C,0.025*%%ADD013C,0.02*%%ADD014C,0.01*%%ADD015C,0.015*%%ADD017R,0.03X0.03*%%ADD019C,0.05*%%ADD020C,0.055*%%ADD024R,0.06X0.06*%%ADD025R,0.035X0.035*%%ADD027C,0.035*%%ADD028C,0.04*%%ADD029C,0.12*%%ADD033C,0.005*%%ADD036C,0.03*%%ADD040C,0.06*%%ADD041C,0.065*%%ADD044R,0.07X0.07*%%ADD045R,0.045X0.045*%%ADD047C,0.045*%%ADD054R,0.08X0.08*%%ADD058C,0.006*%%ADD062C,0.07*%%ADD066C,0.08*%%ADD077C,0.001*%%ADD078R,0.075X0.075*%%ADD079R,0.055X0.055*%%ADD080C,0.087*%%ADD081C,0.153*%%ADD082C,0.177*%%ADD086C,0.18*%%ADD087R,0.065X0.065*%%ADD091C,0.25079*%%ADD092C,0.06614*%%ADD093C,0.157*%%ADD095C,0.016*%****G04 PC Circuitry*G04 Layer Name 81202Capr01.pcb - circuitry*%LPD*%**G04 PC Custom Flashes*G04 Layer Name 81202Capr01.pcb - flashes*%LPD*%**G04 PC Circuitry*G04 Layer Name 81202Capr01.pcb - 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