William Stallings Computer Organization and Architecture

PARTⅡ THE COMPUTER SYSTEMPARTⅡ THE COMPUTER SYSTEM

Chapter 3 System BusesChapter 4 Internal MemoryChapter 5 External MemoryChapter 6 Input/OutputChapter 7 Operating System Support

PARTⅡ THE COMPUTER SYSTEMPARTⅡ THE COMPUTER SYSTEM

Chapter 3 System Buses

3.1 Computer Components3.2 Computer Function3.3 Interconnection Structures3.4 Bus Interconnection3.5 PCI (Peripheral component interconnect)

Computer Components

At a top level, a computer consists of CPU, memory, and I/O components, with one or more modules of each type. These components are interconnected by bus to achieve the basic function of the computer.

3.1 COMPUTER COMPONENTS

Von Neumann architecture Stored Program concept

Data and instructions are stored in a single read-write memory.

The contents of this memory are addressable by location, without regard to the type of data contained there.

Execution occurs in a sequential (unless explicitly modified) from one instruction to the next.

Program Concept

Hardwired program the process of connection together the various

components in the desired configuration as a form of programming, called hardwired program.

Inflexible

Instead of re-wiring, supply a new sequence of codes, called programming in software, as shown in figure 3.1 (p54). General purpose hardware can do different

tasks, given correct control signals

Figure 3.1 Hardware and Software Approaches

What is a program?

A sequence of stepsFor each step, an arithmetic or logical

operation is doneFor each operation, a different set of

control signals is needed

Function of Control Unit

For each operation a unique code is provided e.g. ADD, MOVE

A hardware segment accepts the code and issues the control signals

Computer Components

Central Processing Unit (CPU) The Control Unit and the Arithmetic and Logic

Unit (ALU) constitute the Central Processing Unit (CPU)

Main memory Temporary storage of code and results is

needed

Input/output Data and instructions need to get into the

system and results out

Computer Components:Top Level View

MAR specifies the address in memory for the next read or write;

MBR contains the data to be written into memory or receives the data read from memory;

I/OAR specifies a particular I/O device.Program Counter (PC) :Address of the next Instruction

Instruction Register (IR) : Instruction Being Executed

Accumulator (AC): Temporary Storage

3.2 COMPUTER FUNCTION

Instruction Cycle Two steps:

Fetch Execute

Program execution consists of repeating the process of instruction fetch and instruction execution.

Fetch Cycle

Program Counter (PC) holds address of next instruction to fetch

Processor fetches instruction from memory location pointed to by PC

Increment PC Unless told otherwise

Instruction loaded into Instruction Register (IR)Processor interprets instruction and performs

required actions

Execute Cycle

Processor-memory data transfer between CPU and main memory

Processor- I/O Data transfer between CPU and I/O module

Data processing Some arithmetic or logical operation on data

Control Alteration of sequence of operations

e.g. jump

Combination of above

0 3 4 15

Opcode Address

S Magnitude

0 1 15

(a) Instruction Format

(b) Integer Format

0001=Load AC from Memory

0010= Store AC to Memory

0101=Add to AC from Memory

(d) Partial List of Opcodes

Fig. 3.4 Characteristics of a Hypothetical Machine

Example of Program ExecutionP57 Figure 3.4

1. The PC contains 300, the address of the first instruction. This instruction is loaded into the instruction register, IP.

2. The first 4 bits in the IR indicate that the AC is to be loaded. The remaining 12 bits specify the address, which is 940.

3. The PC incremented and the next instruction is fetched.

4. The old contents of the AC and the contents the AC and the contents of location 941 are added and the result is stored in the AC.

5, 6

Instruction Cycle - State Diagram Instruction address

calculation (iac): Determine the address of the next instruction to be executed.

Instruction fetch (if): Read instruction from its memory location into the processor.

Instruction operation decoding (iod): Analyze instruction to determine type of operation to be performed and operand(s) to be used.

Operand address calculation (oac)

Operand fetch (of) Data operation (do) Operand store (os)

InterruptsMechanism by which other modules (e.g. I/O) may

interrupt normal sequence of processingClasses of Interrupts

◊ Program e.g. overflow, division by zero

◊Timer Generated by internal processor timer Used in pre-emptive multi-tasking

◊I/O from I/O controller

◊ Hardware failure e.g. memory parity error

补充 : 中断系统1. 中断概念的引入

图 运用中断技术输入数据的示意图

1. 现行程序执行时 , 首先通过输入接口启动输入设备工作 .

2. CPU 执行现行程序并等待中断

3. 输入设备组织了一个数据存入输入接口电路

4. 接口电路向 CPU 发出“中断请求” , 请求 CPU 中断现行程序 .

5. CPU 满足一定条件后 , 向接口发出中断响应信号 .

6. CPU 中断现行程序 , 转向预先设计好的”中断服务程序” .

7. CPU 执行服务程序 , 从接口电路中取走输入数据 .

8. 中断服务程序执行完毕 , 返回现行程序的断点 , 继续执行被中断的程序

补充 : 中断向量的引导作用

图 . 中断向量的引导作用

If interrupt pending:Suspend execution of current program Save contextSet PC to start address of interrupt handler interrupt handler routineroutine Process interrupt Restore context and continue interrupted program

Transfer of Control via Interrupts

Program Flow Control Figure 3.7 illustrates the user program performs a series of WRITE calls interleaved with processing.

Figure 3.7 Program Flow of control(a) No Interrupt

The WRITE calls are to an I/O program that is a system utility and that will perform the actual I/O operation.

I/O program A sequence of instructions, labeled

4 in the figure, to prepare for the actual I/O operation. This may include copying the data to be output into a special buffer and preparing the parameters for a device command.

The actual I/O command. Without the use of interrupts, once this command is issued, the program must wait for the I/O device to perform the requested function. The program might wait by simply repeatedly performing a test operation to determine if the I/O operation is done.

A sequence of instructions, labeled 5 in the figure, to complete the operation. This may include setting a flag indicating the success or failure of the operation

Figure 3.7 Program Flow of control(b) Interrupts: short I/O Wait

With interrupts, the processor can be With interrupts, the processor can be engaged in executing other engaged in executing other instructions while an I/O operation is in instructions while an I/O operation is in progress. progress.

A WRITE call is the I/O program that is invoked in this case consists only of the preparation code and the actual I/O command.

When the external device becomes ready to be serviced, that is , when it is ready to accept more data from the processor: the I/O module for the external device sends an interrupt request signal to the processor. The processor responds by suspending operation of the current program, branching off to a program to service that particular I/O device (known as an interrupt handler), and resuming the original execution after the device is serviced. The points at which such interrupts occur are indicated by an asterisk in Figure 3.7b

Figure 3.7 Program Flow of controlwith interrupts

Figure (b) Interrupt: short I/O Wait assumes that the time

required for the I/O operation is relatively short: less than the time to complete the execution of instructions between operations in the user program.

Figure (c) Interrupt: long I/O Wait indicates that the user

program reaches the second WRITE call before the I/O operation spawned by the first call is complete. The result is that the user program is hung up at that point.

Figure (c) Interrupt: long I/O Wait indicates that the

user program reaches the second WRITE call before the I/O operation spawned by the first call is complete. The result is that the user program is hung up at that point.

Figure 3.10 Program Timing:

Short I/O Wait

Figure 3.10 Program Timing:

Long I/O Wait

· The timing for this situation with interrupts has a gain in efficiency because part of the time during which the I/O operation is underway overlaps with the execution of user instructions

·

Interrupt Cycle

Added to instruction cycleProcessor checks for interrupt

Indicated by an interrupt signal

If no interrupt, fetch next instruction If interrupt pending:

Suspend execution of current program Save context Set PC to start address of interrupt handler routine Process interrupt Restore context and continue interrupted program

Instruction Cycle (with Interrupts) - State Diagram

Multiple InterruptsDisable interrupts

Processor will ignore further interrupts whilst processing one interrupt

Interrupts remain pending and are checked after first interrupt has been processed

Interrupts handled in sequence as they occur The drawback is that it does not take into account relative

priority or time-critical needs.

Define priorities Low priority interrupts can be interrupted by higher priority

interrupts When higher priority interrupt has been processed, processor

returns to previous interrupt

Multiple Interrupts - Sequential

(a) Sequential Interrupt Processing

Multiple Interrupts - Nested

(b) Nested Interrupted Processing

Time Sequence of Multiple Interrupts

3.3 INTERCONNECTION STRUCTURES

All the units must be connectedDifferent type of connection for different

type of unit (Figure 3.15) Memory Input/Output CPU

Computer Modules

Memory Connection

Receives and sends dataReceives addresses (of locations)Receives control signals

Read Write Timing

Input/Output Connection(1)

Similar to memory from computer’s viewpoint

Output Receive data from computer Send data to peripheral

Input Receive data from peripheral Send data to computer

Input/Output Connection(2)

Receive control signals from computerSend control signals to peripherals

e.g. spin disk

Receive addresses from computer e.g. port number to identify peripheral

Send interrupt signals (control)

补充补充 : : 输入输入 // 输出端口输出端口

端口 / 口 : 接口电路中包含的一组能与 CPU 交换信息的寄存器，称为 I/O 端口寄存器或端口。端口分为三类：

1 ．数据端口 : 用于存放数据信息（通常为 8 位或 16 位） 输入过程：数据由外设→数据端口→数据总线 DB→CPU 输出过程：数据从 CPU→ 数据总线 DB→ 数据端口经数据线→外

设。2 ．状态端口 : 存放外设当前工作状态的信息 . 作为一种输入数据

CPU 可读取。 输入接口电路——反映输入数据是否准备好。 输出接口电路——反映输出设备的忙、闲状态。

3 ．控制端口 : 存放控制信息。作为一种输出数据由 CPU 通过接口电路→外设，控制外设工作。

接口 : 若干端口加上相应控制电路 .

补充 : 端口地址

当计算机系统中有多个外设时， CPU 在某个时刻只能与一个外设打交道。为了确定此刻哪一个外设可以与计算机打交道，采取与内存同样的处理方法，利用二进制编码为外设编号，该编号被称为外设地址 ( 又称 I/O 地址 / 端口地址 ) 。

多外设情况下 ,CPU 通过为每个外设规定不同的地址来管理外设 . 因外设是通过 I/O 接口的端口与系统相连 , 故对外设寻址 , 实为与外设相连的 I/O 接口的相应端口寻址 .

CPU 寻址的是端口寄存器 .

CPU Connection

Reads instruction and dataWrites out data (after processing)Sends control signals to other unitsReceives (& acts on) interrupts

3.4 BUS INTERCONNECTION

Bus is a shared transmission medium.A bus that connects major computer

components ( processor, memory, I/O) is called a system system

busbus.

BusesBuses

There are a number of possible interconnection systems

Single and multiple BUS structures are most common e.g. Control/Address/Data bus (PC) e.g. Unibus (DEC-PDP)

What is a Bus?

A communication pathway connecting two or more devices

Usually broadcast Often grouped

A number of channels in one bus e.g. 32 bit data bus is 32 separate single bit

channels

Power lines may not be shown

Data Bus

Carries data Remember that there is no difference between

“data” and “instruction” at this level

The number of lines (the width of the The number of lines (the width of the data bus) determines how many bits can data bus) determines how many bits can be transferred at a time.be transferred at a time.

WidthWidth is a key determinant of system performance 8, 16, 32, 64 bit

Address bus

Identify the source or destination of data e.g. CPU needs to read an instruction (data)

from a given location in memory

Address Bus width determines maximum memory capacity of system If bus address width is x bits, the

maximum memory capacity is 2x.

e.g. 8080 has 16 bit address bus giving 64k address space

Control Bus Control and timing information Timing signals indicate the validity of data and address

information. Command signals specify operation to be performed.

Typical control lines Memory read/write signal I/O write/read Interrupt request Interrupt ACK Bus request: Indicates that a module needs to gain control of the bus Bus grant: Indicates that a requesting module has been granted

control of the bus Transfer ACK: Indicates that data have been accepted from or placed

on the bus Clock signals: used to synchronize operation Reset: Initializes all modules Clock: Used to synchronize operations

Bus Interconnection Scheme

Big and Yellow?

What do buses look like? Parallel lines on circuit boards Ribbon cables Strip connectors on mother boards

e.g. PCI (Peripheral Component Interconnection )

Sets of wires

Single Bus Problems

Lots of devices on one bus leads to: Propagation delays

This delay determines the time it takes for devices to coordinate the use of the bus.

Long data paths mean that co-ordination of bus use can adversely affect performance

The bus may become a bottleneck as a aggregate data transfer approaches bus capacity

Most systems use multiple buses to overcome these problems

Traditional (ISA)(with cache) ＊ An expansion bus interface buffers

data transfers between system bus and the I/O controller on the expansion bus.

＊ Advantages of this arrangement

support a wide variety of I/O device

insulate memory-to-processor traffic from I/O traffic.

High Performance Bus

＊ The cache controller is integrated into a bridge, or buffering device, that connects to the high-speed bus.

＊ The advantage of high-performance architecture is that the high-speed bus brings high-demand devices into closer integration with the processor and at the same time is independent of the processor.

Type Dedicated Multiplexed

Method of Arbitration Centralized Distributed

Timing Synchronous Asynchronous

BUS Width Address Data

Data Transfer Type Read Write Read-modify-write (a read followed immediately by a write to the same address) Read-after-write (a write followed immediately by a read to the same address)

Block

Elements of Bus DesignElements of Bus Design

Bus Types

Dedicated Separate data & address lines A dedicated bus line is permanently assigned

either to one function or to a physical subset of computer components.

Multiplexed Shared lines Address valid or data valid control line Advantage - fewer lines Disadvantages

More complex controlReduction ultimate performance

Bus Arbitration

More than one module controlling the buse.g. CPU and DMA controller

Only one module may control bus at one time

Arbitration may be centralised or centralised or distributeddistributed.

Centralised Arbitration

Single hardware device controlling bus access Bus Controller Arbiter

May be part of CPU or separate

Distributed Arbitration

Each module may claim the busControl logic on all modules

Timing

Co-ordination of events on bus SynchronousSynchronous

Events determined by clock signals Control Bus includes clock line A single 1-0 is a bus cycle or clock cycle All devices can read clock line Usually sync on leading edge Usually a single cycle for an event Simple and less flexible

Synchronous Timing Diagram― Example of read operation

Leading Edge Trailing Edge

a delay of one cycle

AsynchronousAsynchronous With asynchronous timing, the occurrence of

one event on a bus follows and depends on the occurrence of a previous event.

MSYN (master sync) SSYN (slave sync)

Asynchronous Timing DiagramThe processor places address address and read signalread signal on the bus. After pausing for these signal to stabilize, it issues an MSYN MSYN indicating the presence of valid address and control signals.

The memory module responds with datadata and an SSYNSSYN signal.

Once the master has read the data from the data lines, it deserts the MSYN signal. This causes the memory module to drop the data and SSYN lines.

Finally, once the SSYN line is dropped, the master removes the read signal and address information.

3.5 PCI Bus

Peripheral Component InterconnectionPeripheral Component Interconnection ( (PCIPCI)) High-bandwidth, processor-independent bus Better performance for high-speed I/O subsystems 64 data lines at 66 MHz, raw transfer rate of 528Mbyte/s,

or 4.224Gbps.

Intel releases all the patent to public domain PCI SIG (an industry association)

To develop further and maintain the compatibility of the PCI specifications.

PCI widely adopted

BUS Structure PCI configured as a 32 or 64 bit bus 50 lines

PCI Bus Lines (required) (table 3.3)

Function groups Systems lines

Including clock and reset Address & Data

32 time multiplexed lines for address/data Interrupt & validate lines

Interface Control Control the timing of transactions Provide coordination among initiators and targets

Arbitration Not shared Direct connection to PCI bus arbiter

Error lines Used to report parity and other errors

PCI Bus Lines (Optional ) (table3.4)

Interrupt lines Not shared, each PCI has its own interrupt lines or lines to

an interrupt controller.

Cache support 64-bit Bus Extension

Additional 32 lines Time multiplexed Interrupt & validate lines 2 lines to enable devices to agree to use 64-bit transfer

JTAG/Boundary Scan For testing procedures

PCI Commands

Transaction between initiator (master) and target

Master claims busDetermine type of transaction

e.g. I/O read/write

Address phase The C/BE lines used to signal the transaction type

One or more data phases

Table3.3 Mandatory PCI Signal Lines CLK

Provides timing for all transactions and is sampled by all inputs on the rising edge. Clock rates up to 33MHz are supported.

AD Multiplexed lines used for address and data.

C/BE (Command/ Byte Enable signal) Multiplexed bus command and byte enable signals. During the data

phase, the lines indicate which of the four byte lanes carry meaningful data.

FRAME Driven by current master to indicate the start and duration of a

transaction. It is asserted at the start and deserted when the initiator is ready to begin the final data phases.

IRDY#: Initiator Ready TRDY#: Target Ready DEVSEL#: Device Select.

Asserted by target when it has recognized its address. Indicates to current initiator whether any device has been selected

Data TransfersData TransfersEvery data transfer on the PCI bus is single transaction consisting of one address phase and one and more data phases.

PCI Read Timing Diagram a. Once a bus master has gained control of the bus, it may begin the transaction by asserting FRAMEFRAME. The line remains asserted until the initiator is ready to complete the last data phase.

b. At the start of clock 2, the target device will recognize its address on the AD lines

c. The initiator ceases driving the AD bus. The initiator changes information on the C/BE# C/BE# lines to designate which AD lines are to be used for transfer for the currently addressed data.

d. DEVSEL#DEVSEL# to indicate that it has recognized its address and will respond. It places the requested data on the AD lines and assert TRDY#TRDY# to indicate that valid data is present on the bus.

e. The initiator reads the data at the beginning of clock and change the byte enable lines as needed in preparation for the next read.

f. In this example, the target needs time to prepare.

g. During clock 6, the target places the third data item on the bus. However in this example, initiator is not yet ready. This will cause the target to maintain the third data item on the bus for an extra clock cycle.

h. The last data transfer

i. The initiator deasserts IRDY, returning the bus to the idle state, and the target deasserts TRDY and DEVSEL.

ArbitrationArbitration

PCI makes use of a centralized, synchronous arbitration scheme. Each master has a unique request (REQ) and

grant (GNT) signal. These signal lines are attached to a central arbiter.

request-grant handshakerequest-grant handshake used to grant access to the bus.

PCI Bus Arbitration (p89)a. At some point prior to the start of clock 1, A has

asserted its REQ signal.

b. During clock cycle 1, B requests use of the bus by asserting its REQ signal.

c. At the same time, the arbiter assert GNT-A to grant bus access to A.

d. Bus master A samples GNT-A at the beginning of clock 2 and learns that it has been granted bus access. It also finds IRDY and TRDY deasserted, indicating that the bus is idle. Accordingly, it asserts FRAME and places the address information on the address bus and the command on the C/BE bus. It also continues to asserts REQ-A, because it has a second transaction to perform after this one.

e. The bus arbiter samples all the GNT lines at the beginning of clock 3 and makes an arbitration decision to grant the bus to B for the next transaction. It then assert GNT-B and deasserts GNT-A. B will not be able to use the bus until it returns to an idle state.

f. A deasserts FRAME to indicate the last data transfer is in progress

g. At the beginning of clock5, B finds IRDY and FRAME deasserts and so it able to take control of the bus by asserting FRAME. It also deasserts its REQ line, because it only wants to perform one transaction.

Exercises Exercises

P47 E2.1P90 3.2

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