UNIT-3 rd

Quine-McCluskey minimization technique:-

This is basically a tabular method of minimization and as much it is suitable for computer applications. The procedure for optimization as follows:

Step 1: Describe individual minterms of the given expression by their equivalent binary numbers.

Step 2: Form a table by grouping numbers with equivalent number of 1’s in them, i.e. first numbers with no 1’s, then numbers with one 1, and then numbers with two 1’s, … etc.

Step 3: Compare each number in the top group with each minterm in the next lower group. If the two numbers are the same in every position but one, place a check sign () to the right of both numbers to show that they have been paired and covered. Then enter the newly formed number in the next column (a new table). The new number is the old numbers but where the literal differ, an “x” is placed in the position of that literal.

Step 4: Using (3) above, form a second table and repeat the process again until no further pairing is possible. (On second repeat, compare numbers to numbers in the next group that have the same “x” position.

Step 5: Terms which were not covered are the prime implicants and are ORed and ANDed together to form final function.

Combinational Circuits:-

Combinational circuit is a circuit in which we combine the different gates in the circuit, for example encoder, decoder, multiplexer and demultiplexer. Some of the characteristics of combinational circuits are following −

The output of combinational circuit at any instant of time, depends only on the levels present at input terminals.

The combinational circuit do not use any memory. The previous state of input does not have any effect on the present state of the circuit.

A combinational circuit can have an n number of inputs and m number of outputs.

1. Multiplexer

Multiplexer is a device that has multiple inputs and a single line output. The select lines determine which input is connected to the output, and also to increase the amount of data that can be sent over a network within certain time. It is also called a data selector.

Multiplexer Types

Multiplexers are classified into four types:

2-1 multiplexer ( 1select line)

4-1 multiplexer (2 select lines)

8-1 multiplexer(3 select lines)

16-1 multiplexer (4 select lines)

Following figure shows the general idea of a multiplexer with n input signal, m control signals and one output signal.

4-to-1 Multiplexer:

The 4-to-1 multiplexer has 4 input bit, 2 control bits, and 1 output bit. The four input bits are

D0,D1,D2 and D3. only one of this is transmitted to the output y. The output depends on the value of

AB which is the control input. The control input determines which of the input data bit is transmitted

to the output.

For instance, as shown in fig. when AB = 00, the upper AND gate is enabled while all other AND

gates are disabled. Therefore, data bit D0 is transmitted to the output, giving Y = Do.

If the control input is changed to AB =11, all gates are disabled except the bottom AND gate. In this

case, D3 is transmitted to the output and Y = D3.

An example of 4-to-1 multiplexer is IC 74153 in which the output is same as the input.

Another example of 4-to-1 multiplexer is 45352 in which the output is the compliment of the

input.

2. Demultiplexer:-Demultiplexer means one to many. A demultiplexer is a circuit with one input and many output. By applying control signal, we can steer any input to the output. Few types of demultiplexer are 1-to 2, 1-to-4, 1-to-8 and 1-to 16 demultiplexer. Following figure illustrate the general idea of a demultiplexer with 1 input signal, m control signals, and n output signals.

1-to-4 Demultiplexer:

The 1-to-4 demultiplexer has 1 input bit, 2 control bit, and 4 output bits. An example of 1-to-4 demultiplexer is IC 74155.

The 1-to-4 demultiplexer is shown in figure below.

The input bit is labelled as Data D. This data bit is transmitted to the data bit of the output lines.

This depends on the value of AB, the control input.

When AB = 01, the upper second AND gate is enabled while other AND gates are disabled.

Therefore, only data bit D is transmitted to the output, giving Y1 = Data.

If D is low, Y1 is low. IF D is high,Y1 is high. The value of Y1 depends upon the value of D. All

other outputs are in low state.

If the control input is changed to AB = 10, all the gates are disabled except the third AND gate

from the top. Then, D is transmitted only to the Y2 output, and Y2 = Data.

Example of 1-to-16 demultiplexer is IC 74154 it has 1 input bit, 4 control bits and 16 output bit.

3. Decoder:- Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2noutput lines. One of

these outputs will be active High based on the combination of inputs present, when the decoder is

enabled. That means decoder detects a particular code. The outputs of the decoder are nothing but

the min terms of ‘n’ input variables (lines), when it is enabled.

Decoder is identical to a demultiplexer without any data input. It performs operations which are

exactly opposite to those of an encoder.

2 to 4 DecoderLet 2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3, Y2, Y1 & Y0.

The block diagram of 2 to 4 decoder is shown in the following figure.

One of these four outputs will be ‘1’ for each combination of inputs when enable, E is ‘1’.

The Truth table of 2 to 4 decoder is shown below.

Enable Inputs Outputs

E A1 A0 Y3 Y2 Y1 Y0

0 x x 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

From Truth table, we can write the Boolean functions for each output as

Y3=E.A1.A0Y2=E.A1.A0′Y1=E.A1′.A0Y0=E.A1′.A0′

Each output is having one product term. So, there are four product terms in total. We can

implement these four product terms by using four AND gates having three inputs each & two

inverters.

The circuit diagram of 2 to 4 decoder is shown in the following figure.

Therefore, the outputs of 2 to 4 decoder are nothing but the min terms of two input variables A1 &

A0, when enable, E is equal to one. If enable, E is zero, then all the outputs of decoder will be

equal to zero.

Similarly, 3 to 8 decoder produces eight min terms of three input variables A2, A1 & A0 and 4 to 16

decoder produces sixteen min terms of four input variables A3, A2, A1 & A0.

4. Encoder:

An Encoder is a combinational circuit that performs the reverse operation of Decoder. It has

maximum of 2n input lines and ‘n’ output lines. It will produce a binary code equivalent to the

input, which is active High. Therefore, the encoder encodes 2n input lines with ‘n’ bits. It is

optional to represent the enable signal in encoders.

4 to 2 EncoderLet 4 to 2 Encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0.

The block diagram of 4 to 2 Encoder is shown in the following figure.

At any time, only one of these 4 inputs can be ‘1’ in order to get the respective binary code at the

output.

The Truth table of 4 to 2 encoder is shown below.

Inputs Outputs

Y3 Y2 Y1 Y0 A1 A0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

From Truth table, we can write the Boolean functions for each output as

A1=Y3+Y2A0=Y3+Y1

We can implement the above two Boolean functions by using two input OR gates. The circuit diagram of 4 to 2 encoder is shown in the following figure.

The above circuit diagram contains two OR gates. These OR gates encode the four inputs with two

bits.

5. Binary Adder:- The most basic arithmetic operation is addition. The circuit, which performs the addition of two

binary numbers is known as Binary adder. Implementation of an adder, which performs the

addition of two bits.

Half AdderHalf adder is a combinational circuit, which performs the addition of two binary numbers A and B

are of single bit. It produces two outputs sum, S & carry, C.

The Truth table of Half adder is shown below.

Inputs Outputs

A B C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

When we do the addition of two bits, the resultant sum can have the values ranging from 0 to 2 in

decimal. We can represent the decimal digits 0 and 1 with single bit in binary. But, we can’t

represent decimal digit 2 with single bit in binary. So, we require two bits for representing it in

binary.

Let, sum, S is the Least significant bit and carry, C is the Most significant bit of the resultant sum.

For first three combinations of inputs, carry, C is zero and the value of S will be either zero or one

based on the number of onespresent at the inputs. But, for last combination of inputs, carry, C is

one and sum, S is zero, since the resultant sum is two.

From Truth table, we can directly write the Boolean functions for each output as

S=A⊕B

C=AB

We can implement the above functions with 2-input Ex-OR gate & 2-input AND gate.

The circuit diagram of Half adder is shown in the following figure.

In the above circuit, a two input Ex-OR gate & two input AND gate produces sum, S & carry, C

respectively. Therefore, Half-adder performs the addition of two bits.

4-bit Binary Adder:-The 4-bit binary adder performs the addition of two 4-bit numbers. Let the 4-bit binary numbers, A

= A3 A2 A1 A0 and B = B3 B2 B1 B0 We can implement 4-bit binary adder in one of the two

following ways.

Use one Half adder for doing the addition of two Least significant bits and three Full adders for

doing the addition of three higher significant bits.

Use four Full adders for uniformity. Since, initial carry C in is zero, the Full adder which is used

for adding the least significant bits becomes Half adder.

For the time being, we considered second approach.

The block diagram of 4-bit binary adder is shown in the following figure.

Here, the 4 Full adders are cascaded. Each Full adder is getting the respective bits of two parallel

inputs A & B. The carry output of one Full adder will be the carry input of subsequent higher order

Full adder. This 4-bit binary adder produces the resultant sum having at most 5 bits. So, carry out

of last stage Full adder will be the MSB.

In this way, we can implement any higher order binary adder just by cascading the required

number of Full adders. This binary adder is also called as ripple carry (binary) adder because the

carry propagates (ripples) from one stage to the next stage.

6. Binary adder as subtractor:- The circuit, which performs the subtraction of two binary numbers is known as Binary

subtractor. We can implement Binary subtractor in following two methods.

Cascade Full subtractors

2’s complement method

In first method, we will get an n-bit binary subtractor by cascading ‘n’ Full subtractors. So, first

you can implement Half subtractor and Full subtractor, similar to Half adder & Full adder. Then,

you can implement an n-bit binary subtractor, by cascading ‘n’ Full subtractors. So, we will be

having two separate circuits for binary addition and subtraction of two binary numbers.

4-bit Binary Subtractor:-The 4-bit binary subtractor produces the subtraction of two 4-bit numbers. Let the 4bit binary

numbers, A = A3 A2 A1 A0 and B = B3 B2 B1 B0 Internally, the operation of 4-bit Binary

subtractor is similar to that of 4-bit Binary adder. If the normal bits of binary number A,

complemented bits of binary number B and initial carry (borrow), Cin as one are applied to 4-bit

Binary adder, then it becomes 4-bit Binary subtractor.

The block diagram of 4-bit binary subtractor is shown in the following figure.

This 4-bit binary subtractor produces an output, which is having at most 5 bits. If Binary number A

is greater than Binary number B, then MSB of the output is zero and the remaining bits hold the

magnitude of A-B. If Binary number A is less than Binary number B, then MSB of the output is

one. So, take the 2’s complement of output in order to get the magnitude of A-B.

In this way, we can implement any higher order binary subtractor just by cascading the required

number of Full adders with necessary modifications.

7. Carry look ahead adder:

A carry-look ahead adder (CLA) or fast adder is a type of adder used in digital logic. A carry-

look ahead adder improves speed by reducing the amount of time required to determine carry

bits. It can be contrasted with the simpler, but usually slower, ripple-carry adder (RCA), for

which the carry bit is calculated alongside the sum bit, and each stage must wait until the

previous carry bit has been calculated to begin calculating its own sum bit and carry bit. The

carry-lookahead adder calculates one or more carry bits before the sum, which reduces the wait

time to calculate the result of the larger-value bits of the adder. 

Carry-look ahead depends on two things:

1. Calculating for each digit position whether that position is going to propagate a carry if one

comes in from the right.

2. Combining these calculated values to be able to deduce quickly whether, for each group of

digits, that group is going to propagate a carry that comes in from the right.

In such adder circuits, it is not possible to produce the sum and carry outputs of any stage until the input carry occurs. So there will be a considerable time delay in the addition process , which is known as , carry propagation delay. In any combinational circuit , signal must propagate through the gates before the correct output sum is available in the output terminals.

Consider the above figure, in which the sum S4 is produced by the corresponding full adder as soon as the input signals are applied to it. But the carry input C4 is not available on its final steady state value until carry c3 is available at its steady state value. Similarly C3 depends on C2 and C2 on C1. Therefore, carry must propagate to all the stages in order that output S4 and carry C5 settle their final steady-state value.

The propagation time is equal to the propagation delay of the typical gate times the number of gate levels in the circuit. For example, if each full adder stage has a propagation delay of 20n seconds, then S4 will reach its final correct value after 80n (20 × 4) seconds. If we extend the number of stages for adding more number of bits then this situation becomes much worse.

So the speed at which the number of bits added in the parallel adder depends on the carry propagation time. However, signals must be propagated through the gates at a given enough time to produce the correct or desired output.

Decimal adder:-

Magnitude Comparator

A magnitude digital Comparator is a combinational circuit that compares two digital or binary numbers in order to find out whether one binary number is equal, less than or greater than the other binary number. We logically design a circuit for which we will have two inputs one for A and other for B and have three output terminals, one for A > B condition, one for A = B condition and one for A < B condition.

1-Bit Magnitude Comparator –

A comparator used to compare two bits is called a single bit comparator. It consists of two inputs each for two single bit numbers and three outputs to generate less than, equal to and greater than between two binary numbers.

The truth table for a 1-bit comparator is given below:

From the above truth table logical expressions for each output can be expressed as follows:

A>B: AB'A<B: A'BA=B: A'B' + AB

From the above expressions we can derive the following formula:

By using these Boolean expressions, we can implement a logic circuit for this comparator as given below:

Read - only memory   ( ROM ):-

ROM stands for Read Only Memory. The memory from which we can only read but cannot write on it. This type of memory is non-volatile. The information is stored permanently in such memories during manufacture. A ROM stores such instructions that are required to start a computer. This operation is referred to as bootstrap. ROM chips are not only used in the computer but also in other electronic items like washing machine and microwave oven.

Various types of ROMs and their characteristics.

MROM (Masked ROM)

The very first ROMs were hard-wired devices that contained a pre-programmed set of data or instructions. These kind of ROMs are known as masked ROMs, which are inexpensive.

PROM (Programmable Read Only Memory)

PROM is read-only memory that can be modified only once by a user. The user buys a blank PROM and enters the desired contents using a PROM program. Inside the PROM chip, there are small fuses which are burnt open during programming. It can be programmed only once and is not erasable.

EPROM (Erasable and Programmable Read Only Memory)

EPROM can be erased by exposing it to ultra-violet light for a duration of up to 40 minutes. Usually, an EPROM eraser achieves this function. During programming, an electrical charge is trapped in an insulated gate region. The charge is retained for more than 10 years because the charge has no leakage path. For erasing this charge, ultra-violet light is passed through a quartz crystal window (lid). This exposure to ultra-violet light dissipates the charge. During normal use, the quartz lid is sealed with a sticker.

EEPROM (Electrically Erasable and Programmable Read Only Memory)

EEPROM is programmed and erased electrically. It can be erased and reprogrammed about ten thousand times. Both erasing and programming take about 4 to 10 ms (millisecond). In EEPROM, any location can be selectively erased and programmed. EEPROMs can be erased one byte at a time, rather than erasing the entire chip. Hence, the process of reprogramming is flexible but slow.

Advantages of ROM

The advantages of ROM are as follows −

Non-volatile in nature

Cannot be accidentally changed

Cheaper than RAMs

Easy to test

More reliable than RAMs

Static and do not require refreshing

Contents are always known and can be verified

Arithmetic logic unit (ALU)   An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and logic operations. It represents the fundamental building block of the central processing unit (CPU) of a computer. Modern CPUs contain very powerful and complex ALUs. In addition to ALUs, modern CPUs contain a control unit (CU).

Most of the operations of a CPU are performed by one or more ALUs, which load data from input registers. A register is a small amount of storage available as part of a CPU. The control unit tells the ALU what operation to perform on that data, and the ALU stores the result in an output register. The control unit moves the data between these registers, the ALU, and memory.

Different operation as carried out by ALU can be categorized as follows –

logical operations: These include operations like AND, OR, NOT, XOR, NOR, NAND, etc. Bit-Shifting Operations: This pertains to shifting the positions of the bits by a certain number

of places either towards the right or left, which is considered a multiplication or division operations.

Arithmetic operations: This refers to bit addition and subtraction. Although multiplication and division are sometimes used, these operations are more expensive to make. Multiplication and subtraction can also be done by repetitive additions and subtractions respectively.

Programmable Logic Array

Programmable Logic Array(PLA) is a fixed architecture logic device with programmable AND gates followed by programmable OR gates. PLA is basically a type of programmable logic device used to build reconfigurable digital circuit. PLDs have undefined function at the time of manufacturing but they are programmed before made into use. PLA is a combination of memory and logic.

PLA is similar to a ROM in concept; however it does not provide full decoding of variables and does not generate all minterms as in the ROM. Though its name consist of word “programmable”, it does not require any type of programming like in C and C++.

Following Truth table will be helpful in understanding function on no of inputs-

F1 = AB’C’ + AB’C + ABC’ + ABCon simplifying we get : F1 = AB’ + AC

F2 = A’BC + AB’C + ABCon simplifying we get: F2 = BC + AC

For realization of above function following circuit diagram will be used.

PLA is used for implementation of various combinational circuits using buffer, AND gate and OR gate. In PLA, all the minterms are not realized but only required minterms are implemented. As PLA has programmable AND gate array and programmable OR gate array, it provides more flexibility but disadvantage is, it is not easy to use.

Applications:

PLA is used to provide control over datapath. PLA is used as a counter. PLA is used as a decoders. PLA is used as a BUS interface in programmed I/O.

HDL Gate and Data Flow modeling:-

Gate level: The module is implemented in terms of logic gates and interconnections between these gates. Designer should know the gate-level diagram of the design.

Gate-level modeling is virtually the lowest-level of abstraction, because the switch-level abstraction is rarely used. In general, gate-level modeling is used for implementing lowest level modules in a design like, full-adder, multiplexers, etc. Verilog HDL has gate primitives for all basic gates.

Data flow level: In this level the module is designed by specifying the data flow. Designer must how data flows between various registers of the design.

Dataflow modeling is a higher level of abstraction. The designer no need have any knowledge of logic circuit. He should be aware of data flow of the design. The gate level modeling becomes very complex for a VLSI circuit. Hence dataflow modeling became a very important way of implementing the design.In dataflow modeling most of the design is implemented using continuous assignments, which are used to drive a value onto a net. The continuous assignments are made using the keyword assign.

In this style of modeling, the internal working of an entity can be implemented using concurrent signal assignment. Let’s take half adder example which is having one XOR gate and a AND gate. 

Library IEEE; IEEE.STD_LOGIC_1164.all; entity ha_en is port (A,B:in bit;S,C:out bit); end ha_en; 

architecture ha_ar of ha_en is begin S<=A xor B; C<=A and B; end ha_ar; 

Here STD_LOGIC_1164 is an IEEE standard which defines a nine-value logic type, called STD_ULOGIC. use is a keyword, which imports all the declarations from this package. The architecture body consists of concurrent signal assignments, which describes the functionality of the design. Whenever there is a change in RHS, the expression is evaluated and the value is assigned to LHS.

HDL Behavioral modeling:-

Behavioral modeling is the highest level of abstraction in the Verilog HDL. The other modeling techniques are relatively detailed. They require some knowledge of how hardware or hardware signals work.

The abstraction in this modeling is as simple as writing the logic in C language.

This is a very powerful abstraction technique.

All that designers needs are the algorithm of the design, which is the basic information for any

design. Most of the behavioral modeling is done using two important constructs: initial and

always.

All the other behavioral statements appear only inside these two structured procedure

constructs.

During simulation of behavioral model, all the flows defined by the ‘always’ and ‘initial’ statements

start together at simulation time ‘zero’. The initial statements are executed once, and the always

statements are executed repetitively. In this model, the register variables a and b are initialized to

binary 1 and 0 respectively at simulation time ‘zero’. The initial statement is then completed and is not

executed again during that simulation run. This initial statement is containing a begin-end block (also

called a sequential block) of statements. In this begin-end type block, a is initialized first followed by

b.

Behavioral description use the keyword always followed by a list of procedural assignment statements.

The target output of procedural assignment statement must be of the reg data type.

The behavioral description of 2-to-1 line multiplexer in HDL is given below.

// Behavioral description of 2-to-1 line multiplexer

module mux2x1_bh (A,B,select,OUT);

input A,B,select;

output OUT; reg OUT;

always @(select or A or B)

if (select==1) OUT=A;

else OUT=B;

endmodule