yoginandha.files.wordpress.com · Web view2016. 10. 13. · NARASARAOPETA ENGINEERING COLLEGE....

NARASARAOPETA ENGINEERING COLLEGE

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

VLSI LAB

LIST OF EXPERIMENTS

1. Design and Implementation of an Inverter

1. Design and Implementation of Universal Gates

1. Design and Implementation of Full Adder

1. Design and Implementation of Full Subtractor

1. Design and Implementation of RS-Latch

1. Design and Implementation of D-Latch

1. Design and Implementation of Asynchronous Counter

1. Design and Implementation of Static RAM Cell

1. Design and Implementation of Differential Amplifier

1. Design and Implementation of Ring Oscillator

1. DESIGN & IMPLEMENT CMOS INVERTER

AIM: To design and implement CMOS inverter

SOFTWARES: Mentor Graphics HEP-1, Personal computer

CIRCUIT DIAGRAM OF CMOS INVERTER

SYMBOL:

SIMULATION CIRCUIT:

PROCEDURE:

1. Create a schematic cell named ‘inv1’ in already created project.

2. Create a new pyxis schematic ‘inv1’ in schematic cell.

3. Open schematic window and draw the cmos logic circuit. Check and save the design of cmos inverter.

4. Generate symbol. Check and save the symbol.

5. Create new test bench cell named ‘inv1_tb’. Create new test bench schematic named ‘inv1_sim’.

6. Draw the test bench. Check and save the test bench.

7. Set up the probes for DC, TRANSIENT and POWER analysis.

8. Run ELDO and display the waveforms on EZWAVES.

9. Verify the wave forms with truth table.

10. Open new layout named ‘inv1’ in schematic cell. Draw the layout

11. After implementing the layout go to tools –caliber-run DRC, LVS, and PEX.

12. Open test bench and enter into the simulation mode.

13. Assign .pex file to the test bench symbol.

14. Repeat the steps 8 & 9 for post layout results.

15. Compare the schematic and layout results.

LAYOUT:

SIMULATION RESULTS:

DC Analysis Result:

Transient Analysis Result:

Power calculation:

LAYOUT WAVEFORMS OF CMOS INVERTER

Result:

2. DESIGN AND IMPLEMENT UNIVERSAL GATES

AIM: To design and implement Universal gates.

a) NAND Gate.

b) NOR Gate.

SOFTWARES: Mentor Graphics Back End Tool - HEP-1, Personal computer.

CIRCUIT DIAGRAM:

a). NAND GATE

SYMBOL:

SIMULATION CIRCUIT:

PROCEDURE:

1. Create a schematic cell named ‘nand1’ in already created project.

2. Create a new pyxis schematic ‘nand1’ in schematic cell.



5. Create new test bench cell named ‘nand1_tb’. Create new test bench schematic named ‘nand1_sim’.





10. Open new layout named ‘nand1’ in schematic cell. Draw the layout






LAYOUT:

SIMULATION RESULTS :

Schematic Result:


Layout Result:


Power Calculation :

Result:

b)NOR GATE

CIRCUIT DIAGRAM:

SYMBOL:

SIMULATION CIRCUIT:

PROCEDURE:

1. Create a schematic cell named ‘nor1’ in already created project.

2. Create a new pyxis schematic ‘nor1’ in schematic cell.



5. Create new test bench cell named ‘nor1_tb’. Create new test bench schematic named ‘nor1_sim’.





10. Open new layout named ‘nor1’ in schematic cell. Draw the layout






LAYOUT:


Schematic Result:


Layout Result:


Power Calculation:

Result:

3. DESIGN AND IMPLEMENT FULL ADDER

AIM: To design and implement Full Adder


CIRCUIT DIAGRAM:

XOR GATE

CIRCUIT DIAGRAM:

SYMBOL:

SIMULATION CIRCUIT:

LAYOUT:

AND GATE

CIRCUIT DIAGRAM:

SYMBOL:

SIMULATION CIRCUIT:

LAYOUT:

OR GATE

CIRCUIT DIAGRAM:

SYMBOL:

SIMULATION CIRCUIT:

LAYOUT:

Symbol:

Full Adder Test Bench:

PROCEDURE:

1. Create a schematic cell named ‘fa1’ in already created project.

2. Create a new pyxis schematic ‘fa1’ in schematic cell.



5. Create new test bench cell named ‘fa1_tb’. Create new test bench schematic named ‘fa1_sim’.





10. Open new layout named ‘fa1’ in schematic cell. Draw the layout






LAYOUT:


Schematic Results: Transient Analysis Result:

Result:

4. DESIGN AND IMPLEMENT FULL SUBTRACTOR

AIM: To design and simulate the Full Subtractor


CIRCUIT DIAGRAM:

XOR GATE

CIRCUIT DIAGRAM:

SYMBOL:

SIMULATION CIRCUIT:

LAYOUT:

AND GATE

CIRCUIT DIAGRAM:

SYMBOL:

SIMULATION CIRCUIT:

LAYOUT:

OR GATE

CIRCUIT DIAGRAM:

SYMBOL:

SIMULATION CIRCUIT:

LAYOUT:


SYMBOL:

LAYOUT:

Full Subtractor: Symbol:

SIMULATION CIRCUIT:

PROCEDURE:

1. Create a schematic cell named ‘fs1’ in already created project.

2. Create a new pyxis schematic ‘fs1’ in schematic cell.



5. Create new test bench cell named ‘fs1_tb’. Create new test bench schematic named ‘fs1_sim’.





10. Open new layout named ‘fs1’ in schematic cell. Draw the layout






LAYOUT:


Schematic Results:Transient Analysis Result:

Result:

5. DESIGN AND IMPLEMENT RS-LATCH

AIM: To design and simulate the RS-Latch


CIRCUIT DIAGRAM:

NAND GATE

SYMBOL:

LAYOUT:

SYMBOL:

SIMULATION CIRCUIT:

PROCEDURE:

1. Create a schematic cell named ‘rsl1’ in already created project.

2. Create a new pyxis schematic ‘rsl1’ in schematic cell.



5. Create new test bench cell named ‘rsl1_tb’. Create new test bench schematic named ‘rsl1_sim’.





10. Open new layout named ‘rsl1’ in schematic cell. Draw the layout






LAYOUT:


Schematic Results:Transient Analysis Result:


Result :

6. DESIGN AND IMPLEMENT D-LATCH

AIM: To design and simulate the D-Latch


CIRCUIT DIAGRAM:

NAND GATE

SYMBOL:

LAYOUT:


SYMBOL:

LAYOUT:

D- latch SYMBOL :

SYMBOL:

SIMULATION CIRCUIT:

PROCEDURE:

1. Create a schematic cell named ‘dl1’ in already created project.

2. Create a new pyxis schematic ‘dl1’ in schematic cell.



5. Create new test bench cell named ‘dl1_tb’. Create new test bench schematic named ‘dl1_sim’.





10. Open new layout named ‘dl1’ in schematic cell. Draw the layout






LAYOUT;

SIMULATION WAVEFORMS: Transient Analysis

Result:

7. DESIGN AND IMPLEMENT ASYNCHRONOUS COUNTER

AIM: To design and implement asynchronous counter


LOGIC CIRCUIT:

SYMBOL:

TEST BENCH:

PROCEDURE:

1. Create a schematic cell named ‘asc1’ in already created project.

2. Create a new pyxis schematic ‘asc1’ in schematic cell.



5. Create new test bench cell named ‘asc1_tb’. Create new test bench schematic named ‘asc1_sim’.





10. Open new layout named ‘asc1’ in schematic cell. Draw the layout






SIMULATION RESULTS:

Result:

8. DESIGN AND IMPLEMENT STATIC RAM CELL

AIM: To design and simulate the Static RAM Cell


.

CIRCUIT DIAGRAM:

SYMBOL:

SIMULATION CIRCUIT:

PROCEDURE:

1. Create a schematic cell named ‘src1’ in already created project.

2. Create a new pyxis schematic ‘src1’ in schematic cell.



5. Create new test bench cell named ‘src1_tb’. Create new test bench schematic named ‘src1_sim’.





10. Open new layout named ‘src1’ in schematic cell. Draw the layout






LAYOUT:


Schematic Results:


Power Calculation Result:

Result:

9. DESIGN AND IMPLEMENT DIFFERENTIAL AMPLIFIER

AIM: To design and implement Differential Amplifier.l


.

CIRCUIT DIAGRAM:

PROCEDURE:

1. Create a schematic cell named ‘damp1’ in already created project.

2. Create a new pyxis schematic ‘damp1’ in schematic cell.



5. Create new test bench cell named ‘damp1_tb’. Create new test bench schematic named ‘damp1_sim’.





10. Open new layout named ‘damp1’ in schematic cell. Draw the layout






Result :

10. DESIGN AND IMPLEMENT RING OSCILLATOR

AIM: To design and simulate the Ring Oscillator


CIRCUIT DIAGRAM:

SYMBOL:

SIMULATION CIRCUIT:

PROCEDURE:

1. Create a schematic cell named ‘rosc1’ in already created project.

2. Create a new pyxis schematic ‘rosc1’ in schematic cell.



5. Create new test bench cell named ‘rosc1_tb’. Create new test bench schematic named ‘rosc1_sim’.





10. Open new layout named ‘rosc1’ in schematic cell. Draw the layout






LAYOUT :


Schematic Results:

Transient Analysis result:

Result:

COMMON SOURCE AMPLIFIER

AIM: To design and simulate the Common Source Amplifier.

TOOLS: Pyxis Schematic, Pyxis Layout, Eldo, Ezwave, Calibre.

CIRCUIT DIAGRAM:

SIMULATION CIRCUIT:

PROCEDURE:

1. Create a schematic cell named ‘csa1’ in already created project.

2. Create a new pyxis schematic ‘csa1’ in schematic cell.



5. Create new test bench cell named ‘csa1_tb’. Create new test bench schematic named ‘csa1_sim’.





10. Open new layout named ‘csa1’ in schematic cell. Draw the layout






1. .

LAYOUT :

AC ANALYSIS:

· Click on Simulation button form palette area and enter into simulation mode.

· Select the analysis option and specify the below options as given in image.

· Now select the input net and output net and click on Outputs button on palette area and add the below parameters

Analaysis --> AC

Type--> Voltage

Task--> Plot

Modifier --> Magnitude (dB)

Click on OK

again add one more output parameter for phase as below Analaysis --> AC

Type--> Voltage

Task--> Plot

Modifier --> Phase

Click ok

· click on run eldo and view waves to see the results

RESULTS:

AC Analysis result:


Result:

COMMON DRAIN AMPLIFIER

AIM: To design and simulate the Common Drain Amplifier.

TOOLS: Pyxis Schematic, Pyxis Layout, Eldo, Ezwave, Calibre.

CIRCUIT DIAGRAM:

SIMULATION CIRCUIT:

PROCEDURE:

1. Create a schematic cell named ‘cda1’ in already created project.

2. Create a new pyxis schematic ‘cda1’ in schematic cell.



5. Create new test bench cell named ‘cda1_tb’. Create new test bench schematic named ‘cda1_sim’.





10. Open new layout named ‘cda1’ in schematic cell. Draw the layout






LAYOUT:

RESULTS:

AC Analysis result:


SPICE MODEL:

.subckt INV Y A

M2 Y A VDD VDD PMOS L=0.13u W=0.42u M=1

M1 Y A GROUND GROUND NMOS L=0.13u W=0.26u M=1

.ends INV

V2 VDD GROUND DC 5V

V1 A GROUND PULSE ( 0V 5V 0S 1nS 1nS 20nS 50nS )

X_INV1 Y A INV

.DC V1 0.0 5.0 0.1

.TRAN 0 1000N

.PLOT DC V(A) V(Y)

.PLOT TRAN V(A) V(Y)

.TEMP 27

.LIB KEY=MOS /home/software/FOUNDRY/GDK/Pyxis_SPT_HEP/ic_reflibs/tech_libs/generic13/models/lib

.eldo TT

.CONNECT GROUND 0

.global GROUND VDD

.end

PROCESS:

· Create a folder for spice model and create a document with *.cir extension and type the above spice model file.

· open the terminal and navigate to the created folder and run below commands

eldo filename.cir

this will create the necessary files to visualise the output parameters, then run the below command to invoke ezwave and see the simulation results.

ezwave filename.wdb

RESULT:

Result:

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