VLSI PROCESS TECHNOLOGY By - MullanaA Modern CMOS Process p-p-epi p well n well n+ p+ gate oxide Al...
Transcript of VLSI PROCESS TECHNOLOGY By - MullanaA Modern CMOS Process p-p-epi p well n well n+ p+ gate oxide Al...
VLSI PROCESS TECHNOLOGYBy
ER. HIMANSHU SHARMA
Fabrication
WafersProcessing
Processed
Wafer
Chips
Masks
Traditional CMOS Process
A Modern CMOS Process
p-
p-epi
p well n well
p+n+
gate oxide
Al (Cu)
tungsten
SiO2
SiO2
TiSi2
Dual-Well Trench-Isolated CMOS
field oxide
Epi-layer is a high quality crystal grown on the polished surface of pre-doped silicon wafers for making CMOS nano devices.
oxidation
opticalmask
processstep
photoresist coatingphotoresistremoval (ashing)
spin, rinse, dryacid etch
photoresist
stepper exposure
development
Typical operations in a single
photolithographic cycle (from [Fullman]).
Photo-Lithographic Process
Growing the Silicon Ingot
From Smithsonian, 2000
E-Beam Lithography
As the miniaturization of
IC devices continues,
electron beam exposure
technology is gaining
prominence as a
technology for next-
generation design rules
From: ADVANTEST CORPORATION
Silicon Oxidation
The oxide is grown by
exposing the silicon surface
to high temperature steam.
As the oxide grows, the
silicon is consumed. The
arrows represent the direction
of motion of each surface of
the oxide.
Underneath the nitride mask,
the growth is suppressed,
and these areas will become
the active transistor area. Source: Bell Laboratories
Patterning - Photolithography
1. Oxidation
2. Photoresist (PR) coating
3. Stepper exposure
4. Photoresist development and bake
5. Acid etchingUnexposed (negative PR)Exposed (positive PR)
6. Spin, rinse, and dry
7. Processing stepIon implantationPlasma etchingMetal deposition
8. Photoresist removal (ashing)
mask
SiO2 PR
UV light
CMOS Process at a Glance
Define active areas
Etch and fill trenches
Implant well regions
Deposit and patternpolysilicon layer
Implant source and drainregions and substrate contacts
Create contact and via windowsDeposit and pattern metal layers
One full photolithography
sequence per layer
(mask)
Built (roughly) from the
bottom up
5 metal 2
4 metal 1
2 polysilicon
3 source and drain
diffusions
1 tubs (aka wells,
active areas)
exception!
Example of Patterning of SiO2
Si-substrate
Silicon base material
Si-substrate
3. Stepper exposure
UV-light
Patternedoptical mask
Exposed resist
1&2. After oxidation and
deposition of negative
photoresist
PhotoresistSiO2
Si-substrate
Si-substrate
SiO2
8. Final result after
removal of resist
Si-substrate
SiO2
5. After etching
Hardened resist
SiO2
Si-substrate
4. After development and
etching of resist, chemical or
plasma etch of SiO2
Hardened resist
Chemical or plasmaetch
Diffusion and Ion Implantation
1. Area to be doped is
exposed
(photolithography)
2. Diffusion
or
Ion implantation
Ion Implantation
1. Dopant atoms are ionized
and then accelerated by an
electric field until they
impinge on the silicon
surface, where they embed
themselves.
2. A polysilicon line crosses
the active area in the upper
left and forms the gate of a
transistor.
Source: Bell Laboratories
Deposition and Etching
1. Pattern masking
(photolithography)
2. Deposit material over
entire waferCVD (Si3N4)
chemical deposition
(polysilicon)
sputtering (Al)
3. Etch away unwanted
materialwet etching
dry (plasma) etching
Metallization
1. First an insulating glass layer is deposited to cover the silicon, then contact holes are cut into the glass layer down to the silicon.
2. Metal is deposited on top of the glass, connecting to the devices through the contact holes.
3. The graphic shows a snapshot during the filling of a contact hole with
aluminum.Source: Bell Laboratories
F5112 E-Beam Lithography
Single-Column System
Minimum Feature Size: 100nm
Overlay Accuracy:
|mean|+3 sigma<=40nm
3 sigma<=15nm
Block Exposure Method:
Max. No. of Block Patterns: 70
Planarization: Polishing the Wafers
From Smithsonian, 2000
Self-Aligned Gates
1. Create thin oxide in the “active” regions, thick elsewhere
2. Deposit polysilicon
3. Etch thin oxide from active region (poly acts as a mask for the diffusion)
4. Implant dopant
Simplified CMOS Inverter P-well Process
cut line
p well
P-Well Mask
Active Mask
Poly Mask
P+ Select Mask
N+ Select Mask
Contact Mask
Metal Mask
VLSI Fabrication: The Cycle
The n-well CMOS process starts with a moderately doped (impurity concentration less than 1015 cm-3) p-type silicon substrate.
Then, an oxide layer is grown on the entire surface. The first lithographic mask defines the n-well region. Donor atoms, usually phosphorus, are implanted through this window in the oxide. This defines, the active areas of the nMOS and pMOS transistors.
Thin gate oxide is grown on top of the active regions. The thickness and the quality of the gate oxide are critical fabrication parameters, since they affect the characteristics of the MOS transistor, and its reliability.
CMOS N-well Process (cont’d)
CMOS N-well Process (cont’d)
The polysilicon layer is
deposited using chemical
vapor deposition (CVD) and
patterned by dry (plasma)
etching.
The created polysilicon lines
will function as the gate
electrodes of the nMOS and the
pMOS transistors and their
interconnects.
Also, the polysilicon gates act
as self-aligned masks for the
source and drain implantations
that follow this step.
CMOS N-well Process (cont’d)
Using a set of two masks, the
n+ and p+ regions are
implanted into the substrate
and into the n- well,
respectively.
The ohmic contacts to the
substrate and to the n-well are
implanted in this process step.
CMOS N-well Process (cont’d)
An insulating silicon dioxide
layer is deposited over the
entire wafer using CVD.
Then, the contacts are defined
and etched away to expose the
silicon or polysilicon contact
windows.
CMOS N-well Process (cont’d)
Metal is deposited over the
entire chip surface using metal
evaporation, and the metal lines
are patterned through etching.
Since the wafer surface is non-
planar, the quality and the
integrity of the metal lines
created in this step are very
critical and are essential for
circuit reliability.
CMOS N-well Process (cont’d)
The composite layout and the
resulting cross-sectional view of
the chip, showing one nMOS
and one pMOS transistor (built-
in n-well), the polysilicon and
metal interconnections.
The final step is to deposit the
passivation layer (overglass -
for protection) over the chip,
except for wire-bonding pad
areas.
Advanced Metallization
From Design to Reality…
Design Rules
CMOS Process LayersLayer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green
Layers in 0.25 mm CMOS process
Design Rules
Interface between the circuit designer and process
engineer
Guidelines for constructing process masks
Unit dimension: minimum line width
» scalable design rules: lambda parameter
» absolute dimensions: micron rules
Rules constructed to ensure that design works even
when small fab errors (within some tolerance) occur
A complete set includes
» set of layers
» intra-layer: relations between objects in the same layer
» inter-layer: relations between objects on different layers
3D Perspective
Polysilicon Aluminum
Why Have Design Rules?
To be able to tolerate some level of fabrication
errors such as
1. Mask misalignment
2. Dust
3. Process parameters
(e.g., lateral diffusion)
4. Rough surfaces
Intra-Layer Design Rule Origins
Minimum dimensions (e.g., widths) of objects on each
layer to maintain that object after fab
» minimum line width is set by the resolution of the
patterning process (photolithography)
Minimum spaces between objects (that are not
related) on the same layer to ensure they will not
short after fab
0.3 micron
0.3 micron
0.15
0.15
Inter-Layer Design Rule Origins
1. Transistor rules – transistor formed by
overlap of active and poly layers
Transistors
Catastrophic error
Unrelated Poly & Diffusion
Thinner diffusion,but still working
Inter-Layer Design Rule Origins, Con’t
2. Contact and via rules
M1 contact to p-diffusion
M1 contact to poly
Mx contact to My
Contact Mask
Via Masks
0.3
0.14
both materialsmask misaligned
M1 contact to n-diffusion
Contact: 0.44 x 0.44
Intra-Layer Design Rules
Metal24
3
10
90
Well
Active3
3
Polysilicon
2
2
Different PotentialSame Potential
Metal13
3
2
Contactor Via
Select
2
or6
2Hole
Transistor Layout
1
2
5
3
Tra
nsi
sto
r
Vias and Contacts
1
2
1
Via
Metal toPoly ContactMetal to
Active Contact
1
2
5
4
3 2
2
Select Layer
1
3 3
2
2
2
WellSubstrate
Select3
5
IC Layout
CMOS Inverter Sticks Diagram
1
3
In Out
VDD
GND
Stick diagram of inverter
• Dimensionless layout entities
• Only topology is important
• Final layout generated by
“compaction” program
CMOS Inverter max Layout
VDD
GND
NMOS (2/.24 = 8/1)
PMOS (4/.24 = 16/1)
metal2
metal1polysilicon
InOut
metal1-poly via
metal2-metal1 via
metal1-diff via
pfet
nfet
pdif
ndif
Layout Editor
Design Rule Checker
poly_not_fet to all_diff minimum spacing = 0.14 um.
CMOS Inverters
Polysilicon
InOut
Metal1
VDD
GND
PMOS
NMOS
1.2 mm=2l
Well-well spacing = 9
M1- M1 spacing = 3
M1width = 4
Active to well edge = 5
Min active width = 3
Poly overlap of active = 2
M2 - M2 spacing = 4
All distances in l
Layout Design Rule Violation
Building an Inverter
A
VCC
VSS
A
Output
Step 1 Step 2
A
OutputP
N
A
P diffusion
N diffusion
Step 3 Step 4
VCC
Output
VSS
With permission of William Bradbury
Building a 2 Input NOR Gate
A A BA B A BB
A
B
Out
P
Output
Shared node
A B
A
B
P
N N
Step 1 Step 3
Output
Output
Shared
node
VSS
VCC
VSS
Step 2
P
N
Step 4
VSS
Output
V
C
C
With permission of William Bradbury
Building a 2 Input NAND Gate
With permission of William Bradbury
A A BA BB
Step 1 Step 3
Output
Output
Shared
node
VSS
VCC
VSS
Step 2
P
N
Step 4
A B
V
S
S
O
u
t
p
u
t
V
C
C
Shared node
Output
P BA P
AN
BN
A
B
Out
Combining Logic Functions
With permission of William Bradbury
A
Out
B
B ’
B ’
B
B
AP
Out
P
B ’
A
B ’N
N
AB ’
VCC
VSSB
B ’
VSS
VCC
Out
AB ’
Out
B
VSS
VCC
Cell Symbol to Logic to Transistor Schematic to Layout
With permission of William Bradbury
INPUT OUTPUT
LD LD’
SRAM
OUTPUT
P 1.4
N 1.4
LD
LD’
P 1.8
N 2.0
P 2.0
N 2.0
P .5/1.0
N .6/1.0
INPUT B
A
SRAM BIT LOGIC
Minimum poly width
“L” = 0.20
OUTPUT
SRAM BIT TRANSISTOR SCHEMATIC
INPUTP2, 1.8
N2, 2.0
P3, .5/1.0
P4, 2.0
N4, 2.0P1, 1.4
N1, 1.4
LD
LD’
B
A
N3 , .6/1.0
Note the listing of the “L” dimension
which is not the minimum defined by
the process
Schematic to Transistor
With permission of William Bradbury
AINPUT
LD
P1
VCC
A
B
P2VCC
OUTPUTB
P4
VCC
A
B
P3
A
INPUT
LD’
N1
VSS
A
B
N2
VSS
B
OUTPUT
N4
VSSA
B
N3
Assembling the Transistors by Type and Node Name
With permission of William BradburyWith permission of William Bradbury
VSS
A
LD’
B
OUTPUT
VSS
A
B
VSS
B
INPUT
VCCAA
INPUT
LD
A
VC
C
B
B
VCC OUTPUT
B
Connecting the Nodes
With permission of William Bradbury
VSS
A
LD’
B
OUTPUT
VSS
A
B
VSS
B
INPUT
VCCAA
INPUT
LD
A
VC
C
B
B
VCC OUTPUT
B
Connecting the Dotes
With permission of William Bradbury
INPUT
V
C
C
A
B
A
I
N
P
U
T
LD
VC
CB
V
C
C
O
U
T
P
U
T
B
V
S
SA
I
N
P
U
T
LD’
V
SS
B
O
U
T
P
U
T
A
B
A
BA
UNMERGED DATA:
Notice the addition of contacts
where necessary and also the use of
redundant contacts to improve
reliability
VSS
Cleaning Connections and Completing the layout
With permission of William Bradbury
.
P-TAP
V
C
CB
A
V
C
C
B
O
U
T
P
U
T
VS
S
A
IN
PU
TVS
S
B
OU
TP
UT
VS
S
B
A
A
B
OUTPUTINPUT
LD’
B
B
B
P-IMPLANT
N-TAPN-WELL
P1
P2
P
3
P4
N1 N3 N4
N-IMPLANT
N2
VC
C
IN
P
U
T
A
LDDD
Added:
1.Taps
2.Implants
3.Cell boundry
Using sticks
With permission of William Bradbury
.
N diffusion
Metal1
P diffusion
Contact
Poly
B AB’
VSS
VCC
Output
Same cell, different shape
With permission of William Bradbury
.
AB’B
VSS
VCC VCC
Out
AB’
VCC
B
OutB’
VSS
B AB’
VSS
VCC
Output
Cells Designed for Sharing
With permission of William Bradbury
.
1 Bit
1 Bit
Memory Row 1
Compare Row 1
Reference VoltageSense
Ckt. for
One Row
Height of 1
Memory Bit
1 Bit
1 Bit
Memory Row 1
Compare Row 1
Reference VoltageDual
Sense Amp
Cell Height
Compare Row 2
Memory Row 2
Reference Voltage
Dual Sense Amps Dual Write Line Ckts
Courtesy Mentor Graphics Corp. Layout created using IC-Station.
Cells Designed for Sharing
With permission of William Bradbury
.
Packaging
Packaging Requirements
Desired package properties
Electrical: Low parasitics
Mechanical: Reliable and robust
Thermal: Efficient heat removal
Economical: Cheap
Wire bonding
–Only periphery of chip available
for IO connections
–Mechanical bonding of one pin
at a time (sequential)
–Cooling from back of chip
–High inductance (~1nH)
http://www.embeddedlinks.com/chipdir/package.htm
More about packaging:
Chip to package connection
Flip-chip
– Whole chip area available for IO connections
– Automatic alignment
– One step process (parallel)
– Cooling via balls (front) and back if required
– Thermal matching between chip and substrate
required
– Low inductance (~0.1nH)
Bonding Techniques
Lead Frame
Substrate
Die
Pad
Wire Bonding
Tape-Automated Bonding (TAB)
(a) Polymer Tape with imprinted
(b) Die attachment using solder bumps.
wiring pattern.
Substrate
Die
Solder BumpFilm + Pattern
Sprocket
hole
Polymer film
Lead
frame
Test
pads
New package types
BGA (Ball Grid Array)
– Small solder balls to connect
to board
– small
– High pin count
– Cheap
– Low inductance
CSP (Chip scale Packaging)
– Similar to BGA
– Very small packages
Package inductance:
1 - 5 nH
Flip-Chip Bonding
Solder bumps
Substrate
Die
Interconnect
layers
Package-to-Board Interconnect
(a) Through-Hole Mounting (b) Surface Mount
Package Types
Through-hole vs. surface mount
From Adnan Aziz http://www.ece.utexas.edu/~adnan/vlsi-05/
Chip-to-Package Bonding
Traditionally, chip is surrounded by pad frame» Metal pads on 100 – 200 mm pitch
» Gold bond wires attach pads to package
» Lead frame distributes signals in package
» Metal heat spreader helps with cooling
From Adnan Aziz http://www.ece.utexas.edu/~adnan/vlsi-05/
Advanced Packages
Bond wires contribute parasitic inductance
Fancy packages have many signal, power layers» Like tiny printed circuit boards
Flip-chip places connections across surface of die rather than around periphery» Top level metal pads covered with solder balls
» Chip flips upside down
» Carefully aligned to package (done blind!)
» Heated to melt balls
» Also called C4 (Controlled Collapse Chip Connection)
From Adnan Aziz http://www.ece.utexas.edu/~adnan/vlsi-05/
Package Parasitics
Chip
Sig
nal P
ins
Package
Capacitor
Sig
nal P
ads
Chip
VDD
Chip
GND
Board
VDD
Board
GND
Bond Wire Lead Frame
Package
Use many VDD, GND in parallel
» Inductance, IDD
From Adnan Aziz http://www.ece.utexas.edu/~adnan/vlsi-05/
Signal Interface
Transfer of IC signals to PCB» Package inductance.
» PCB wire capacitance.
» L - C resonator circuit generating oscillations.
» Transmission line effects may generate reflections
» Cross-talk via mutual inductance
L
C
Package
ChipPCB trace
L-C Oscillation
Z
Transmission line reflections
R
f =1/(2p(LC)1/2)
L = 10 nH
C = 10 pF
f = ~500MHz
Package Parameters
Package Parameters
Package Parameters
2000 Summary of Intel’s Package I/O Lead Electrical Parasitics for Multilayer Packages
Packaging Faults
Small Ball Chip Scale Packages (CSP) Open
CSP Assembly on 6 mil Via in 12 mil padVoid over via structure
Packaging Faults
Miniaturisation of Electronic Systems
Enabling Technologies :
»SOC
»High Density Interconnection
technologies
–SIP – “System-in-a-package”
From ECE 407/507 University of Arizona
http://www.ece.arizona.edu/mailman/listinfo/ece407
The Interconnection gap
Improvement in density of standard interconnection and packaging technologies is much slower than the IC trends
IC scaling
Time
PCB scaling
Interconnect Gap
Advanced PCB
Laser via
From ECE 407/507 University of Arizona
http://www.ece.arizona.edu/mailman/listinfo/ece407
The Interconnection gap
Requires new high density Interconnect technologies
IC scaling
Time
PCB scaling
Advanced PCB
Reduced Gap
Thin film lithography based
Interconnect technology
From ECE 407/507 University of Arizona
http://www.ece.arizona.edu/mailman/listinfo/ece407
SoC has to overcome…
» Technical Challenges:
Increased System Complexity.
Integration of heterogeneous IC technologies.
Lack of design and test methodologies.
» Business Challenges:
Long Design and test cycles
High risk investment
Hence time to market.
» Solution
System-in-a-Package
From ECE 407/507 University of Arizona
http://www.ece.arizona.edu/mailman/listinfo/ece407
Multi-Chip Modules
Multiple Chip Module (MCM) Increase integration level of system (smaller size)
Decrease loading of external signals > higher performance
No packaging of individual chips
Problems with known good die:
» Single chip fault coverage: 95%
» MCM yield with 10 chips: (0.95)10 = 60%
Problems with cooling
Still expensive
Complete PC in MCM