VLSI Fischer 02 DesignFlow - Heidelberg University · Design Hierarchy VLSI Design: Design Flow P....
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Design Flow VLSI Design: Design Flow P. Fischer, ziti, Uni Heidelberg, Seite 1
Transcript of VLSI Fischer 02 DesignFlow - Heidelberg University · Design Hierarchy VLSI Design: Design Flow P....
Design Flow
VLSI Design: Design Flow P. Fischer, ziti, Uni Heidelberg, Seite 1
Levels of Abstraction
VLSI Design: Design Flow P. Fischer, ziti, Uni Heidelberg, Seite 2
system
chip
module
gate
circuit
component
technology
physics
CPU RAM Grafik
Register File ALU Control
This Lecture
Design Hierarchy
VLSI Design: Design Flow P. Fischer, ziti, Uni Heidelberg, Seite 3
'Core'
§ A chip is subdivided in smaller blocks • Described by schematics or hardware description language (HDL)
§ At lowest Level: • simple logic functions (NAND, MUX) + ‘standard cell’ layouts • Analogue 'full custom blocks’
‚top'
IO
A real(y deep) Design Hierarchy
§ The hierarchy has MANY levels
§ In our chips: max. 10-15 levels
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Pentium P6
Top-Down, Bottom-Up
§ I believe: both methods have drawbacks § Try to come from both sides!
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Example: DAC
§ Digital Analogue Converter: Binary Code → Current
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Chip
IO Pads (CMOS in, CMOS out, Power, Analogpads)
Core
Seriall Interface
x-y-Decoder
Current Sources
Reference Output Stage
FFs Gates
Gates
Source Switch
1. Schematic and Symbol
§ Schematic describes circuit with other cells & transistors § A ‚symbol‘ of the cell contains all pins
• It is later used to represent the schematic in the hierarchy
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2. Simulation
§ Mostly analogue (for us)
§ Models are different for each vendor! Are provided by vendor. Should be verified..
§ Optimize circuits
§ Results can be used to parameterize the cell.
§ For instance, digital cells can be modelled by delay (depending on Cload, VDD, Temp,..)
§ ⇒ digital (VERILOG) Model
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Layout, Design Rule Check
§ Layout (mostly by hand) on transistor level § Check of vendor-given rules with Design Rule Check (DRC)
(z.B. conductor widths, spacing,...) § Design rules are different for each technology!
• The are collected in a (text) file.
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Labels
NOR2 MUX2
Standard Cells
§ (Digital) standard cells have equal heights and identical (power) connections, so that the can be arranged in rows.
§ In technologies with >2 metal layers: routing on top of cells § 'Optimal' placement of cell is challenging task! § Wires introduce delays
which are not a priori known by simulation!
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row
Special Layout : Bit-Slice
§ For repetitive structures: pads are arranged so that touching cells connect correctly • compact layout, low delays, best performance
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Full Adder One Bit of a DACs
FA Symbol for 1 bit: A
B
CI
S
CO
FA Geometry for 1 Bit:
CI
A
CO
S
B
FA CI
A0
CO
S0
B0
FA
A1
S1
B1
FA
A2
S2
B2
FA
A3
S3
B3
4 Bit Adder:
Full Chip
§ Standard Cells + Full custom cells (here: RAMs, Delays) + Pads ('frame')
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Design Flow
VLSI Design: Design Flow P. Fischer, ziti, Uni Heidelberg, Seite 13
CCS Lecture
VLSI Lecture
