Readout of DC coupled double sided sensors with CBMXYTER: Some first thoughts Peter Fischer,...

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Readout of DC coupled double sided sensors with CBMXYTER: Some first thoughts Peter Fischer, Heidelberg University

Transcript of Readout of DC coupled double sided sensors with CBMXYTER: Some first thoughts Peter Fischer,...

Page 1: Readout of DC coupled double sided sensors with CBMXYTER: Some first thoughts Peter Fischer, Heidelberg University.

Readout of DC coupled double sided sensors with CBMXYTER:

Some first thoughts

Peter Fischer, Heidelberg University

Page 2: Readout of DC coupled double sided sensors with CBMXYTER: Some first thoughts Peter Fischer, Heidelberg University.

P. Fischer, ziti, HD: dc coupled sensor readout 2

Goal of this talk

Think about consequences of dc coupling for readout chip Start a discussion on system issues

(control, readout, supplies)

This is a first collection of thoughts – to be improved!

This talk:• Sensor model• Connecting CBMXYTERs in dc mode• Fault tolerance approach• Chip connections: Power, Slow/ Fast Control, Data Out• Readout options: Some thoughts (also see Walter’s talk!)

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Sensor Model: Segmentation

implants bottom side

implantstop side

optionalpunch

through bias

Double sided strip sensor

subdivideinto diodes

one diode(vertical)

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N3

Sensor Model: Equivalent Circuit (I)

P1

P2

P3

N1 N2 N3

N2

N1

P3

P2

P1

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Sensor Model: Equivalent Circuit (I)

Observation: Input on one side has no ‘partner’ on other side, it’s a mix of all other inputs (across FE-chips!)

Thinking of a differential input, the ‘partner’ is ill defined Detector Signal is a current pulse in one of the diodes

To be more realistic, must:• Add series resistances of implants / aluminum traces• Add inter strip capacitors

N3

N2

N1

P3

P2

P1

N3

N2

N1

P3

P2

P1

(not all caps on n-side shown)

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Connecting DC coupled chips. (1/N possibilities)

moreanalog

digital

digitalDAQmore

analogdigital

levelshift

HV decouplingHV

powersupply

digitalsupply

analogsupply

Hybrid on detector Cavern Outside

refer single ended signal

to which ground here?

feedback & leakage compensation analog

supply

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Many questions:

Decouple what w.r. to what? Connect which grounds? Where? and how (R, L)? How to connect power supplies?

• Is it allowed to connect grounds in cavern to save cables?

These issues are not related to dc coupling Can be tested with NXYTER. Find out how other

experiments have done. (This stuff is rarely in papers..) Be prepared for several iterations

How to do the level shifting?• optical fibers – elegant!• optical couplers – slow!• inductive couplers – slow!• ac coupling• cascodes – can also be used for analog signals (currents)

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Discussion: Fault tolerance

Question: Is a daisy chain architecture excluded ?• Depends on fault tolerance approach

Should we be prepared to operate a module with single non functioning chips?

• How ‘easy’ is a repair of a bad module (access in fixed target exp. is simple)

• When a chip dies, does this kill the module anyway ?(for instance by shorts in supplies, noise on sensor)

• How often does a chip die during operation?

Is fault tolerance ‘nice to have’ or ‘required’?• This needs a discussion & decision

Note: a good burn-in may catch most ‘early failures’

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IO Signals required

Supply voltages• Connect chip grounds where?• Connect power supply ground in counting room (‘loop’) or on hybrid

(more cables)?

Slow control• best have this independent of readout (→ read back via slow control)• avoid bi-directional signal (simplify level shifting). This rules out I2C• avoid daisy chains for fault tolerance (?) (this rules out JTAG)• Compromise: Unidirectional bus with geographical address: clk, din,

dout, load, (reset). Very simple interface.

Fast control (‘TTC’)• clock, epoch marker (DLM), timestamp fast reset (can we use DLM?)

Data outputs Monitoring of analog signals

• level shifting difficult. Could use cascodes for currents.• Best use on-chip ADC and digital readout

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Readout. Preliminaries.

Use as few cables as possible → fill max. bandwidth Must provide a concept to cope with different occupancies

on different chips

cable data rate distance Connectors driver

optical fiber >2.5Gbps infinite clumsy

or special

Laser (clumsy),

serializer

coax >2Gbps >10m small on chip,

serializer

CAT7 LVDS

250Mbps 10m clumsy on chip,

clk & data

Custom LVDS

100Mbps few m (?) small on chip,

clk & data

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Optical Serial Data Transmission

Assume we have it somewhere in the path for level shift Components required:

Protocol FSM

8B/10B

Serializer

LVDS/CML output

Laser Driver

Laser Diode

Connector

fiber

Laser Package

Chip1

Chip2

Mechanics

digital

analog

difficult

Provided bySFP package!

available

available (?)

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Readout 1: Event Builder on Module

GBT will be developed by CERN. May be suitable. Probably a bit overkill. Still needs many extra radhard components

FE

FE

GBT

Hybrid on detector Cavern Outside

LaserLaserDriver

PiNTIA

clock, epoch

optionalFPGA

80 Mbps

4.8 Gbps

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Readout 2: Event Builder in Cavern

Many ‘LVDS’ cables Number of cables = number of chips

FE

FE

Hybrid on detector Cavern Outside

clock, epoch

FPGA

???

80-250 Mbps

10 m (Walter)

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Readout 3: Share cables

Equalize hit rates between chips with short parallel links Number of cables limited by data rate. May be adapted to Module Multiplicity

FE

FE

Hybrid on detector Cavern Outside

clock, epoch

FPGA

???

250 Mbps

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Readout 4: Integrated serializer, optical

Pass all hits to one (or more) ‘master’ chips Serializers on other chips are disabed Still Laser Driver, rad hard Laser, Package required

FE

FE

Hybrid on detector Cavern Outside

clock, epoch

optionalFPGA

???

serser

serser

ser

LaserLaserDriver

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Readout 5: Integrated serializer, coax

No extra components needed on Hybrid Receiver needed (?) Cost of cables?

FE

FE

Hybrid on detector Cavern Outside

clock, epoch???

serser

serser

ser

FPGA

drv.drv.

drv.drv.

drv.

coax cable rec.

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Some conclusions

Sensor model is complicated. See what we really need. I2C is bad for level shifting Analog monitoring is difficult Ground & Power connections will be big issue

• as usual• Should try some basic configurations with NXYTER, if possible

Best readout concept depends on• data rates• radiation levels• distance to shielded cavern (=10m)

Look at Walter’s numbers & suggestions!

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To do

Evaluate speed of custom LVDS driver (HD) Look for rad hard Laser driver / package / connector

(→ CERN) Try readout chain: Chip → Coax → FPGA Elaborate on chip → chip protocol Study minimum implementation of a FPGA compatible

serial link (in progress @ HD)