VLSI Development:Chip Design Challenges in the “Real World”

EECE 579 - Advanced Topics in VLSI Design

Spring 2009

Brad Quinton

Goal of this Talk

• Building a chip is about far more than circuit design…

– how does an Application Specific Standard Product (ASSP) get built?

– who is involved? (i.e. what jobs are available?)

– what are the challenges?

– what can go wrong?

Scope

• this presentation is based on what I have seen at PMC, Altera, Teradici…

• companies like, AMCC, Broadcom, Vitesse, Cypress, Motorola will be very close to this

• however, other chip design may be quite different (i.e. CPU at Intel, or memory design at Infineon, analog design at TI, etc.)

Key Terminology

• RTL: VHDL or Verilog that can be synthesized to gates

• verification: the process of simulating RTL on a workstation to check functionality

• validation: the process of generating input patterns and evaluating outputs using a real chip

A design team…

• digital designers• analog designers• verification engineers (the biggest group!)• validation engineers (another large group)• physical designers• software/firmware engineers• production engineers• research engineers• marketing

The support team…

• CAD tools support engineers• IP QA engineers• CAD tools QA engineers• packaging/PCB design engineers• field application engineers

Phase 1: Product Research

• goal: identify all the potential applications that could benefit from a ASSP (on going)

• who’s involved:– marketing: talk to customers, look at competition

– research engineers: talk to customer’s customers, go to conferences, participate in standard bodies (SONET, Ethernet), think...

Phase 1: Product Research

• challenges:– customers want you to build a product just for

them– trying to predict the future is always hard– customers like to have ‘second sources’, but this

kills profit margins – there are many potential applications

• what can go wrong?:– you guess wrong about the future, spend a lot of

money and don’t sell anything

Phase 1: Product Research

Phase 2: Feasibility

• decide if it is possible to address the application given the technology available (~ 2 months)

• who’s involved:

– research engineers: perform high level performance, cost and power estimates

– digital, analog, IP QA engineers: perform more detailed performance, cost and power estimates

Phase 2: Feasibility

• challenges:

– it is difficult to estimate a design without actually building it; this requires a lot of experience…

• what can go wrong?:

– it is easy to miss a detail in the design specification that radically changes the cost/power of a design

– sometimes standards change

Phase 2: Feasibility

• IEEE 802.3 Ethernet Collision Detection (150 pages):

Phase 3: Product Planning

• decide how much it will cost to build the chip, how much it will sell for, and how many will sell (6 weeks)

• who’s involved:– marketing: talk to customers, investigate competition,

negotiate with customers

– research engineers: talk to customer’s customers, consider application space

Phase 3: Product Planning

– designers, verification, validation, layout, production: estimate who much time and resources it will take to finish the chip

– executive: compare all of the potential chips, potential profits, resource cost; decide which will be built

Phase 3: Product Planning

• challenges:– everything is based on estimates! if even one of them is wrong the

chip might not make money

– a competitor might have done the same analysis a year ago and will beat you to market

• what can go wrong:– you may decide to build a chip, and commit millions of dollars only

to find out that one of the estimates that you made was wrong

– cancel the project

Phase 4: Design Planning

• need to develop documents, schedules and job descriptions for all the engineers on the team (4-6 weeks)

• who’s involved:– designers: start writing the initial engineering document,

start partitioning the design in smaller blocks

– verification: start reading the engineering document and partitioning the testbench

– validation: start reading the engineering document, and planning the test infastructure

Phase 4: Design Planning

• challenges:– everyone wants to start at once, but they need information from

each other

– communicating between all the design groups is key

– marketing is likely still changing the requirements

• what can go wrong?:– it may take a long time to plan in enough detail to get all the the

team working efficiently

– marketing may change their mind, causing you to rewrite your documents

Phase 4: Design Planning

Phase 5: Documentation

• each member of the team needs to document their part of the design or testbench in detail (6 - 8 weeks)

• who’s involved:– designers: each designer write an ~80 page document describing

every aspect of their design; top level designer writes an ~400 page document describing every function in the entire chip in detail

– verification: read ALL the design documents and write a verification plan describing every test that will be simulated on each block and and the chip level (~200-500 pages)

– validation: read ALL the design documents and write a validation plan describing every test that will be performed in the lab

Phase 5: Documentation

• challenges:

– documents are tedious to read and write, it is easy to miss something

• what can go wrong?:

– again, marketing may change their mind, now you have to rewrite ALL your documents

Phase 6: Document Review

• read each others documents to make sure that everything is consistent (2-3 weeks)

• who’s involved:– designers: each designer needs to read document

verification documents, and all adjacent block documents

– verification: needs to re-read all design documents to make sure no tests are missing

– validation: needs to re-read all design document to make sure no tests are missing

Phase 6: Document Review

• challenges:

– boring…

• what can go wrong?:

– once again, marketing may change their mind, now you have to rewrite ALL your documents

– you may have designed something that is too difficult to verify (random arbiters, asychronous logic, etc.)

Phase 7: Design

• write RTL for the design(s) and create testbench(s) (4-5 weeks)

• who’s involved:

– designers: writes VHDL/Verilog RTL based on documents

– verification: writes testbench in VHDL, tcl, C, Specman

– validation: designs PCB, FPGAs, software

– software/firmware: generates C-based device driver for the chip

Phase 7: Design

• challenges:– keeping design consistent with documentation

• what can go wrong?:

– you may find an error in the documentation when you start to write code

– new features…

Phase 8: Verification

• simulate the RTL view of the design to verify it (8-12 weeks)

• who’s involved:– designers: help to debug problems found by verifiers

– verification: run write test scripts, run tests, debug results

Phase 8: Verification

• challenges:– CPU time becomes a critical resource– debugging can take a long time– long run times (up to 12 hours) slow productivity

• what can go wrong?:

– testbench does not cover all the functionality, and a bug is missed (this is a million dollar mistake !)

Phase 9: Backend Design

• synthesize RTL to gate-level netlist, perform netlist QA (6-8 weeks)

• who’s involved:– designers: synthesize RTL, DFT, check design timing, gate

level sims, generate production vectors, formal verification…

– production engineers: evaluate coverage of production vectors, cost of tester time to run vectors

– CAD tool QA engineers: QA a complete set of CAD tools for a given technology, deal with bugs in CAD tools

Phase 9: Backend Design

• challenges:

– understanding CAD tools

• what can go wrong?:

– if there is a tool bug or other problem then this phase can delay the entire chip schedule

– you may have to pipeline your design to meet timing, this will effect ALL of the other designers...

• << picture from design vision here>>

Phase 10: Physical Design

• place and route the entire design, final design QA (16 weeks)

• who’s involved:– layout engineers: run CAD tools to place and route design

– designers: perform static timing on ‘post-layout’ design to make sure that design goals were met

– IP QA engineers: review final placement and timing of all external IP (RAMs, standard cells, etc)

Phase 10: Physical Design

• challenges:

– timing closure!– manufacturing design rules– CAD tool run time (up to 48 hours..)

• what can go wrong?:

– a single design rule violation that was ignored could make the entire chip useless (another million dollar mistake!)

Milestone: Tapeout!

• once the physical design, verification, QA, documentation, etc is done it is sent to the fab (TSMC), where the masks are created and the wafer are built (16 -18 weeks)

• at this point there is nothing to do but…… celebrate!

Phase 11: Manufacturing Test

• apply a set of vectors to detect manufacturing defects (3 weeks)

• who’s involved:

– production engineers: apply vectors from DFT phase of design to the chip using expensive testers

– designers: debug vector failures, regenerate patters

Phase 11: Manufacturing Test

• challenges:

– when vectors fail, it is hard to know why– the testers are expensive and complicated (they are used 24 hours

a day, so engineers/technicians have to work night shifts.)

• what can go wrong?:

– if a chip that has a manufacturing defect gets accepted, then it may appear as if there is a functional bug

– customers like Cisco will not buy parts unless you can show that you have a high quality process for catching defects

Phase 12: Validation

• run tests to exercise all the features on the chip on the REAL chip (16 -24 weeks)

• who’s involved:

– validation engineers: write test scripts in tcl or C to control signal generators, logic analyzers, microcontrollers, and FPGAs to exercise all functions of the chip

– designers: debug failures, update documentation to clarify functionality

– verifiers: recreate lab problems in simulation to allow observation of internal signals

Phase 12: Validation

• challenges:– debugging is extremely difficult since you can’t see what

happening inside the chip

– deciding what is a bug and what is a feature…

• what can go wrong?:– miss a bug that is later found by a customer

– cause customer to recall their designs (very expensive)

Phase 12: Device Revision

• almost all chips need at least one revision (6-8 months)

• who’s involved?:

– everyone: repeat all the previous tasks, only quicker!

Phase 12: Device Revision

• challenges:– a new set of masks cost ~ $800,000 US (130 nm)– customers want fix right away– executives want to be sure that there will not be another

revision

• what can go wrong?:

– if you try to do your revision too quickly you may make another mistake

Milestone: Release to Production

• make the decision that the device is ready to ship in volume (2 - 2.5 years from project start)

• who’s involved?:– validation engineers: confirm that all test pass

– production engineers: confirm that yield is as expected, performance margins are large enough

– design engineers: documentation, documentation, documentation….

Conclusion

• although circuit design is part of the process, a large amount of work is in the documentation, verification and validation of the chip

• the key skills required for success in this industry are: communication, problem analysis, and attention to detail

Questions?