VLSI DesignLecture 4: Wires and Vias,

ParasiticsShaahin Hessabi

Department of Computer EngineeringSharif University of Technology

Adapted, with modifications, from lecture notes prepared by the author (from Prentice Hall PTR)

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Topics

Wire and via structuresWire parasitics

CapacitanceResistance

Transistor parasitics

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Wires and vias

p-tub

poly poly

n+n+

metal 1

metal 3

metal 2

vias

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Metal migration

Current-carrying capacity of metal wire depends on cross-section. Height is fixed, so width determines current limit.Metal migration: when current is too high, electron flow pushes around metal grains. Higher resistance increases metal migration, leading to destruction of wire.

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Metal migration problems and solutions

Marginal wires will fail after a small operating period—infant mortality.Normal wires must be sized to accommodate maximum current flow:Imax = 1.5 mA/μm of metal width.

Mainly applies to VDD/VSS lines.

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Diffusion wire capacitance

Capacitances formed by p-n junctions:

n+ (ND)

depletion region

substrate (NA)bottomwallcapacitance

sidewallcapacitances

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Typical 0.5 micron diffusion capacitance values

n-type:bottomwall: 0.6 fF/μm2

sidewall: 0.2 fF/μm

p-type:bottomwall: 0.9 fF/μm2

sidewall: 0.3 fF/μm

In 0.5 micron process, λ = 0.25 μm

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Diffusion capacitance example

Perimeter = 32λ area = 52 λ2

sidewall/bottomwall capacitances = ?total capacitance = ?

12 λ

3 λ 4 λ

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Depletion region capacitance

Zero-bias depletion capacitance:Cj0 = εsi/xd.

Depletion region width (zero bias):xd0 = sqrt[(1/NA + 1/ND)2εsiVbi/q].

Junction capacitance is function of voltage across junction:

Cj(Vr) = Cj0/sqrt(1 + Vr/Vbi)

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Poly/metal wire capacitance

Two components:parallel plate;fringe.

plate

fringe

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Typical poly/metal capacitance values for 0.5 micron process

poly:plate: 0.09 fF/μm2

fringe: 0.04 fF/μm

metal 1:plate: 0.04 fF/μm2

fringe: 0.09 fF/μm

metal 2:plate: 0.02 fF/μm2

fringe: 0.06 fF/μm

metal 3:plate: 0.009 fF/μm2

fringe: 0.02 fF/μm

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Metal coupling capacitances

Can couple to adjacent wires on same layer, and to wires on above/below layers:

metal 2

metal 1 metal 1

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Example: parasitic capacitance measurement

n-diffusion: bottomwall=2 fF, sidewall=2 fF.

metal: plate=0.15 fF, fringe=0.72 fF.

3 μm

0.75 μm 1 μm

1.5 μm

2.5 μm

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Wire resistance

Resistance of any size square is constant:

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Typical resistance values for our 0.5 micron process

Poly: 4 ohms/squaremetal 1: 0.08 ohms/squaremetal 2: 0.07 ohms/squaremetal 3: 0.03 ohms/squarendiff: 2 ohms/squarepdiff: 2 ohms/square

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Calculating resistance

Determine current flow, then aspect ratio:

I2

20

vs.

I2

20

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Current around corners

Resistance at corner of two equal-width wires is approximately 1/2 square:

1/2 square

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Via resistance

Determined by current flow through via cut.Typical metal1-poly contact: 2.5 ohms.Typical metal1-metal2 contact: 0.5 ohms.

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Skin effect

At low frequencies, most of copper conductor’s cross section carries current.As frequency increases, current moves to skin of conductor.

Back EMF induces counter-current in body of conductor.

Skin effect most important at gigahertz frequencies.

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Transistor gate parasitics

Gate-source/drain overlap capacitance:

gate

source drain

overlap

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Transistor source/drain parasitics

Source/drain have significant capacitance, resistance.

Significant effect on circuit performance.

Measured same way as for wires.Source/drain R, C may be included in Spice model rather than as separate parasitics.