UNIVERSITY OF MASSACHUSETTS AMHERST

ECE 558 INTRODUCTION TO VLSI DESIGN

ECE 658 VLSI DESIGN PRINCIPLES

Homework 4 Text Name: CMOS VLSI Design: A Circuits and Systems Perspective (3rd Edition) by Neil H. E. Weste & David Harris.

Posted Date: Due Date: NOT DUE Answer the following questions.

1. Identify if there are any hold time problems from FF1 to FF2 in the following circuit. If there are any,

indicate by how much the setup time is violated. Assume that the clock frequency is 10���.

Parameter Rise Fall

��� → �� �� �� �� Flip Flop Setup time �� �� � �� Flip Flop Hold time � �� � ��

AND Gate �� �� �� ��

(SOLUTIONS)

Clock period is:

���� = 110��� = 100��

For rising transition, delay from clock edge at FF1 to the input of FF2 is

����� = ����→ !!" + $%����&'( = 95ps

For falling transition, FF2 input arrival time is �-.�� = ����→ !!/ + $-.��&'( = 80��

For a setup time of 10�� the FF2 is expecting the data before: �" = ���� − ���234 = 90��

Thus the setup time is violated for the falling transition for FF2 by 5����� − �"6 = 5��

2. For a memory containing 4096 word × 2048 bit array of SRAM cells with differential bit-line

architecture, assume that the dynamic power consumption is dominated by charging and

discharging the bit lines. Assume further that the cells are tiled at a vertical pitch of 5 BC and a

FF1 FF2

A

B C

CLK FF1 FF2

A

B C

CLK

horizontal pitch of 3 BC. Also assume that each cell adds a load of 3 EF to BL and BL’. Bit lines are in

metal1 and are 0.6 BC wide. HI��� is 0.1EF/BC. While for the word line the load capacitance per

cell is 6EF and the wire cap is HI��� � 0.2EF/BC.

(SOLUTION)

a. Compute the capacitance loading each bit line and word line. Break it down into contributions

from wiring and from memory cells.

(SOLUTION)

Vertical pitch = 5BC

Horizontal Pitch = 3BC

Load on each of the BL and BL’ lines due to 4096 lines in a column of the bit line

HK� � 4096 ⋅ 3EF # 54096 ⋅ 5BC ⋅ 3EF 6 � 14.2�F

Load on the word line is give by

HI� � 2048 ⋅ 6EF # 2048 ⋅ 3BC ⋅ 0.2EF/BC � 13.5�F

b. Assume that the power supply voltage M(( � 1.1M. If the bit lines are pre-charged to 1.1M and

are allowed to develop a maximum differential voltage of 0.1 M (symmetric around the pre-

charge voltage) during a read operation, what is the power consumption by the memory while

reading at an access rate of 5 N��?

(SOLUTION)

In every cycle, ony one of the BL or BL’ lines will be per-charged and discharged depending on the data

read.

Power can be divided into the following components

• Single word line charging/discharging in on clock cycle. The power is given by:

OI� � HI� ⋅ M((/ ⋅ E

OI� � 13.5�F ⋅ 51.1M6/ ⋅ 5N�� � 81BP

2048

4096

• Either one of the BL or BL’ pre-charging when the clock is low and discharging when the memory

location is read.

OK� � HK�QRQ&S ⋅ M��T��/ ⋅ E

HK�QRQ&S = HK� ⋅ 2048 = 29.4UF

M��T�� = 0.1 M

OK� = 1.47 CP

Total power is given by:

WXYXZ� = W[� + W\� = �. ��]^

3. Calculate the yield of a 45UC SRAM chip of 1 _C × 1 _C with a defect density of 1/_C/. Make an

assumption of cell size and peripheral circuitry to determine the number of bits in this memory. Use

` = 1.2.

(SOLUTION)

Yield is given by the following formula:

a = b1 + cdEd_$ cdU�e$f` g

hi= 0.615

4. Sketch a hierarchical schematic for a 4096 jklm × 16 ne$ SRAM. What is the total number of cells?

Arrange the cells in a square array.

a. Show how the array can be folded?

(SOLUTION)

Total number of bits in the memory is :

oQRQ&S = 4096 ⋅ 16 = 2"p

This memory can be organized as follows:

qkj� × HkrsCU� = 2t × 2t = 256 × 256

b. How many address lines are used for word line selection?

(SOLUTION)

Total number of bits in the input address:

ucQv2.� = log/ 4096 = 12 Out of 12 address lines the lower significant 8 bits are used to access the words in the memory.

ucy�y = 8��K

This fetches 16 data words at the same time. The correct data word is selected by using the 4 higher

significant bits using multiplexers.

ucy3z = 4y�K

Total memory word size is

uc � ucy3z # ucy�y

5. Show how redundant rows and columns can help improve yield. Note that the new columns and

rows will increase the chip area and may have consequent adverse impact.

Redundant rows and columns can help improve memory yield. This can be done by replacing the

defective column (row) with a redundant column (row). Figure below shows an example where two cells

in row 3 and one cell in column 3 are defective. To repair the device, appropriate fuses need to be blown

to replace row 3 with the redundant row RR and column 3 with the redundant column RC.