VLSI- הרצאה 3 | Manufacturing
Transcript of VLSI- הרצאה 3 | Manufacturing
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Introduction to VLSI
The ManufacturingProcess
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What will we learn today?
Basic Process Concepts
Detailed Process Flow
Layout and Design Rules
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Basic Concepts
Detailed Flow
Layout & DRC
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CMOS
ProcessOutline
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Basic Process Flow
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Lightly Doped Wafer
Grow Field Oxide
Define Wells
Grow Gate Oxide
Deposit Poly Gate
Etch Gates
Implant Source/Drain
Deposit Isolation
Oxide and Contacts
Deposit Metal 1
Deposit Isolation
Oxide and Via 1
Deposit Metal 2
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What will we learn today?
Basic Process Concepts
Detailed Process Flow
Layout and Design Rules
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Basic Concepts
Detailed Flow
Layout & DRC
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DetailedProcess Flow
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The Silicon Wafer
Smithsonian (2000)
Lightly Doped Wafer
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Field Oxide The STI Process
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Lightly Doped Wafer
Grow Field Oxide
SiO2
Nitride (Si3N4)
The LOCOS Process has two problems: Birds Beak makes it hard to make transistors close to each other.
A parasitic MOSFET can turn on underneath the FOX.
Solution: Shallow Trench Isolation (STI) and Field Implants
Active
Area
Active
Area
Active
Area
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Well Implantation
Cover wafer with thin layer of oxide.
Implant wells through photolithographic
Process.
After implant we must Annealto fix the
covalent bonds, and Diffuseto get the wells tothe depth we want.
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Lightly Doped Wafer
Grow Field Oxide
Well Implants
Annealing: Heating up the wafer to fix covalent bonds. Done after every ion
implantation or similar damaging step.
Diffusion: Movement of dopants due to heating of the wafer. Usually this is
unwanted, as it changes the implanted doping depth.
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Well Implantation Deep N-Wells
Can we change the body voltage of an nMOS
transistor?
Yes, but it costs a lot of area:
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Lightly Doped Wafer
Grow Field Oxide
Well Implants
P-sub (p-)
p (field implant) p (field implant)
N-well (n-) P-well (p)
Deep N-well (n-)
Isolated
P-well (p)
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Transistor Fabrication: VT Implant
The threshold voltage of a transistor is
approximately:
So the first step is to implant QI.
Random Dopant Fluctuations(RDF) cause aproblematic distribution in VTbetween
devices.
Native Transistorsare transistors that didntgo through this step (i.e. V
T0 Depletion)
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Lightly Doped Wafer
Grow Field Oxide
Well Implants
Transistor Fabrication
2 22
s A fI
TH FB f
ox ox
qN qQV V
C C
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Transistor Fabrication: Gate Oxide
Gate Oxide thickness (tox
) is one of the
most important device parameters.
45 nm technology has a 1.2 nm thick
layer (about 5 atoms!).
Gate oxide growth has to be done in
super-clean conditions to eliminate traps
and defects.
New high-Kmaterials extremelycomplicate this process.
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Lightly Doped Wafer
Grow Field Oxide
Well Implants
Transistor Fabrication
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Transistor Fabrication: Gate Etch
Originally Aluminum was used as the gate
material, then polysilicon, now metal again. The gate is the smallest dimension that is
fabricated through photolithography.
The oxide is self-alignedto the gate through
the etching process.
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Lightly Doped Wafer
Grow Field Oxide
Well Implants
Transistor Fabrication
P-sub (p-)
p (field implant) p (field implant)
P-well (p)
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Photolithography
Photolithographic resolution is set by
Therefore, to get better resolution, we could: Use a smaller wavelength (today 193 nm).
Possibilities are e-beam,
extreme UV (13 nm).
Use wet lithography(nwater
=1.43)
Use mask and layout techniques.
Use nanoimprinting.
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Lightly Doped Wafer
Grow Field Oxide
Well Implants
Transistor Fabrication
1
sinD k
n
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Photolithography
Step and Scan
OPC
Phase Shift Masks
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Lightly Doped Wafer
Grow Field Oxide
Well Implants
Transistor Fabrication
Kahng et. al., 1999 DAC
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Transistor Fabrication: Tip Extension
For various reasons, we need a Lightly DopedDrain(LDD).
But for source/drain resistance, we need a
heavily doped area away from the channel.
Therefore, a TiporSpaceris formed:
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Lightly Doped Wafer
Grow Field Oxide
Well Implants
Transistor Fabrication
P-sub (p-)
p (field implant) p (field implant)
P-well (p)
n implant n implant
n+ n+ implant
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Contacts
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Lightly Doped Wafer
Grow Field Oxide
Well Implants
Transistor Fabrication
P-sub (p-)
FOX
p (field implant) p (field implant)
P-well (p)
n implant n implant
n+ n+ implant
Contacts
A Silicidelayer reduces contact resistance.
A thick isolation oxide is grown.
The bumpy oxide is planarized through CMP.
Contacts are etched, lined and plugged.
This is known as the Damascene Process.
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Planarization
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Contacts
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Metal Layers
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Advanced Metallization
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Hillocking and Electromigration
Hillocking:
The development of small hills in the interconnect due to stress on
the Aluminum.
Can short between metal layers, crack SiO2, cause bumpiness.
Adding Cu to Al helps reduce hillocking.
Electromigration:
Movement of Aluminum atoms due to high current densities that can
eventually cause hillocks (shorts) or voids (opens). Proper design helps prevent electromigration.
Cu interconnect is very efficient against electromigration.
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Antenna Effect
Charge is built up on interconnect layers during deposition.
If enough charge is created, this can cause a high voltage to
breakdown the thin gates.
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m4
m3
m2
m1
gate
100
Safe: m3 is too short toaccumulate very muchcharge; wont kill gate
gate
2000
Dangerous: lots of m3; willprobably accumulate lots ofcharge and then blow oxide
diff diff
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Antenna Effect
Bridging or Antenna Diodes are used to eliminate the
Antenna Effect.
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diff
m4
m3
m2
m1
psub
gate
2000
Bridging keeps gate awayfrom long metals until theydrain through the diffusion
gate ndiff
Node diodes are inactive duringchip operation (reverse-biased p/n);let charge leak away harmlessly
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Layer Density
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resist
ILD
metal
High density Low density
This etching step
takes a lot longer(microloading)
Solution: Add dummymetal structures hereto maintain minimummetal density
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What will we learn today?
Basic Process Concepts
Detailed Process Flow
Layout and Design Rules
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Basic Concepts
Detailed Flow
Layout & DRC
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Layout andDesign Rules
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Transistor Layout
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Design Rules
Interface between designer and process engineer
Guidelines for constructing process masks
Unit dimension: Minimum line width
scalable design rules: lambda parameter
absolute dimensions (micron rules)
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Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green
Layers in our Slides
T i t L t
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Transistor Layout
1
2
5
3
Trans
istor
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I t L D i R l
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Intra-Layer Design Rules
Metal2 4
3
10
90
Well
Active3
3
Polysilicon
2
2
Different PotentialSame Potential
Metal13
3
2
Contactor Via
Select
2
or6
2Hole
Vi d C t t
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Vias and Contacts
1
2
1
Via
Metal toPoly ContactMetal to
Active Contact
1
2
5
4
3 2
2
Select Layer
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Select Layer
1
3 3
2
2
2
Well
Substrate
Select
3
5
CMOS I t L t
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CMOS Inverter Layout
A A
np-substrate Field
Oxidep+n+
In
Out
GND VDD
(a) Layout
(b) Cross-Section along A-A
A A
I t L t
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Inverter Layout
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A t l L t i C d
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Actual Layout in Cadence
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L t h
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Latchup
Thyristors created by parasitic BJT transistors can turn on
and short VDD and GND. This requires power down at the least, and sometimes
causes chip destruction.
To eliminate some latchup, use lots of well/substrate
contacts.
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B lk C t t
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Bulk Contacts
To ensure a constant body voltage across large
areas, Bulk Contacts orTapshave to be addedfrequently.
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N-well P-subP-select N-select
pMOS nMOS
N-select P-select
VDD
VSS
Basic La o t Planning
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Basic Layout Planning
Choose global directions for routing layers
Adjacent levels should route perpendicular Example: m2 horizontal, m1 vertical
Position power lines first in top layer of metal
Cluster together NMOS with NMOS and PMOS with PMOS
Generally keep gate orientation the same Arrange transistors so that common sources/drains can be
shared
Arrange transistors so that common gates line up
Limit lengths of diffusion and poly routing use metal
Try to design/layout as little stuff as possible (use
repetition/tools)
An Example Step 1
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An Example Step 1
Choose global directions for routing layers
Position power lines in top layer of metal
An Example Step 2
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An Example Step 2
Cluster together NMOS with NMOS and PMOS with PMOS
Generally keep gate orientation the same
An Example Step 3
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An Example Step 3
Arrange transistors so that common sources/drains can be
shared Give precedence to shared signals over shared vdd/ground
Arrange transistors so that common gates line up
An Example Step 4
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An Example Step 4
Connect everything up and convert to layout
Further Reading
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Further Reading
J. Plummer Silicon VLSI Technology, 2000 especially Chapter 2
J. Rabaey, Digital Integrated Circuits 2003, Chapters 2.2-2.3
C. Hu, Modern Semiconductor Devices for Integrated Circuits, 2010,Chapter 3 http://www.eecs.berkeley.edu/~hu/Book-Chapters-and-Lecture-Slides-download.html
E. Alon, Berkeley EE-141, Lectures 2,4 (Fall 2009)http://bwrc.eecs.berkeley.edu/classes/icdesign/ee141_f09/
http://www.eecs.berkeley.edu/~hu/Book-Chapters-and-Lecture-Slides-download.htmlhttp://bwrc.eecs.berkeley.edu/classes/icdesign/ee141_f09/http://bwrc.eecs.berkeley.edu/classes/icdesign/ee141_f09/http://bwrc.eecs.berkeley.edu/classes/icdesign/ee141_f09/http://bwrc.eecs.berkeley.edu/classes/icdesign/ee141_f09/http://bwrc.eecs.berkeley.edu/classes/icdesign/ee141_f09/http://bwrc.eecs.berkeley.edu/classes/icdesign/ee141_f09/http://bwrc.eecs.berkeley.edu/classes/icdesign/ee141_f09/http://bwrc.eecs.berkeley.edu/classes/icdesign/ee141_f09/http://www.eecs.berkeley.edu/~hu/Book-Chapters-and-Lecture-Slides-download.htmlhttp://www.eecs.berkeley.edu/~hu/Book-Chapters-and-Lecture-Slides-download.htmlhttp://www.eecs.berkeley.edu/~hu/Book-Chapters-and-Lecture-Slides-download.htmlhttp://www.eecs.berkeley.edu/~hu/Book-Chapters-and-Lecture-Slides-download.htmlhttp://www.eecs.berkeley.edu/~hu/Book-Chapters-and-Lecture-Slides-download.htmlhttp://www.eecs.berkeley.edu/~hu/Book-Chapters-and-Lecture-Slides-download.htmlhttp://www.eecs.berkeley.edu/~hu/Book-Chapters-and-Lecture-Slides-download.htmlhttp://www.eecs.berkeley.edu/~hu/Book-Chapters-and-Lecture-Slides-download.htmlhttp://www.eecs.berkeley.edu/~hu/Book-Chapters-and-Lecture-Slides-download.htmlhttp://www.eecs.berkeley.edu/~hu/Book-Chapters-and-Lecture-Slides-download.htmlhttp://www.eecs.berkeley.edu/~hu/Book-Chapters-and-Lecture-Slides-download.html