Viterbi Decoder: Presentation #10 M1 Overall Project Objective: Design a high speed Viterbi Decoder...
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Transcript of Viterbi Decoder: Presentation #10 M1 Overall Project Objective: Design a high speed Viterbi Decoder...
Viterbi Decoder: Presentation #10
M1
Overall Project Objective:
Design a high speed Viterbi Decoder
Stage 10: 5th April. 2004
Final Design Corrections
Design Manager: Yaping Zhan
Omar Ahmad
Prateek Goenka
Saim Qidwai
Lingyan Sun
Status
18-525, Integrated Circuits Design Project
Design Proposal: (Done)
Architecture Proposal: (Done)
Gate level Design: (Done)
Component Layout (DRC & LVS): (Done)
Component Simulation: (Done)
Chip Layout: (Done)
Critical Path Simulation (Done)
Schematic: top level
18-525, Integrated Circuits Design Project
Viterbi Decoder
clk
rst
In_valid
In_data
Out_valid
Out_data
18-525, Integrated Circuits Design Project
Layout – Entire Chip
Tolerance (Matlab Simulation Result)
18-525, Integrated Circuits Design Project
Signal to Noise Ratio (SNR)
>5dBOr max (noise amplitude level) ~ 40%(1.7V in 4V)
Inter-symbol Interference (ISI)
(or Memory Length)
2~4
Critical Path Extraction I
18-525, Integrated Circuits Design Project
DFF
MUX
COMP
+ +
DFF
+ +
+
Critical Path Extraction II
18-525, Integrated Circuits Design Project
Input Pattern Selection
DFF
MUX
COMP
+ +
Worst case pattern for adder: 011001 and 001001
Worst Case pattern for Comp: two Inputs are the same: 011001 vs. 011001
100111 + 011001
000000
Decision : Use input pattern 011001 and 001001 for both adders
18-525, Integrated Circuits Design Project
Simulation Results (500 Mhz.)
Critical Path I Critical Path II
Propagation Delay
365 390
Rise Time 619 717
Fall Time 327 376
Ratio
(Rise/Fall)1.89 1.90
Note: Time values are in ps.
18-525, Integrated Circuits Design Project
Critical Path I
Testing Speed: 500 MHz18-525, Integrated Circuits Design Project
Critical Path I: Propagation Delay I
18-525, Integrated Circuits Design Project
Propagation Delay: 365ps
Critical Path I: Rise Time
18-525, Integrated Circuits Design Project
Rise Time: 619 ps
Critical Path I: Fall Time
18-525, Integrated Circuits Design ProjectFall Time: 327 ps.
Critical Path II
Testing Speed: 500 MHz18-525, Integrated Circuits Design Project
Critical Path II: Propagation Delay I
18-525, Integrated Circuits Design Project
Propagation Delay: 390 ps.
Critical Path II: Rise Time
18-525, Integrated Circuits Design ProjectRise Time: 717 ps.
Critical Path II: Fall Time
18-525, Integrated Circuits Design Project
Rising Time: 376 ps.
Summary
18-525, Integrated Circuits Design Project
Total Area: 309.96 um x 231.48 um = 71,749.54 sq. um
Transistor Count: 17,857
Transistor Density: 0.249
Aspect Ratio: 1.339
Estimated Clock Speed: 300 MHz.
Clock Speed Achieved: 500 MHz.
18-525, Integrated Circuits Design Project
Questions