Implementation of Viterbi Decoder

7/31/2019 Implementation of Viterbi Decoder

1/27

By:Dipendra Kumar Deo (062BEX409)Krishna Prasad Phelu (062BEX416)

Nikendra Tandukar (062BEX419)

Omi Sunuwar (062BEX422)Date: 18 March, 2010.


2/27

Noise is inherent property of all practical channels.

This noise corrupts our data as it passes through thecommunication channel.

Channel coding is used to increase the reliability ofcommunication system by combating noise.

Convolutional code is the most commonly usedchannel coding technique.

Viterbi decoding algorithm is used to decodeconvolutional codes.

2


3/27

To simulate convolutional encoding and ViterbiDecoding using MATLAB tools.

To implement the Viterbi Decoder on FPGA.

To evaluate the performance improvement of thesystem with channel coding in terms of BER forrandomly generated digital data.

3


4/27

4


5/27

VHDL

MATLAB 7.0

C programming language

Spartan-3E FPGA (XC3S500E)

ModelSim SE 6.4

Xilinx ISE Project Navigator

AT89S52 Microcontroller Keil Vision 3

Proteus VSM 7

5


6/27

Pseudo-random number

Generated using LFSR

6

Fig: Random number generation.


7/27

Present state, s1s0 = 00

input = 1

output = 11

next state = 01

7

Fig: (2,1) Convolutional encoder.

Rate, R=1/2

Constraint Length, K=3

Generator Polynomial:g1=[111]

g2=[101]


8/27

8

Fig: State diagram of (2,1)

encoder of R=1/2,K=3.

Fig: Trellis diagram of (2,1)

encoder of R=1/2,K=3.


9/27

9

It is a maximum-likelihood decoding algorithm Fixed decoding time

Highly parallelizable

Disadvantage:

Decoding complexity grows exponentially as afunction of constraint length


10/27

10

Received

00 0

2

11 2

0

3

3

01 3

4


11/27

11Fig: Viterbi decoding

For Binary Symmetric Channel it searches the path inthe trellis which has minimum HD with the receivedbit sequences.


12/27

12

PMM

BMU SMUACS

input

BM

Previous PM Updated PM

BD

output


13/27

BMU and ACS unitmerged into a singleunit.

Four identical unitsfor each state

13


14/27

14

Simulation result for ACS unit for state a


15/27

Metric Normalization Variable Shift Method

15


16/27

16

Survivor Path

Competing Path

Decodedbit output

Copy

Shifted in 0

Survivor Memory Management Register Exchange


17/27


18/27

18

Channel BER = 0.1

System BER = 0


19/27

19Fig: Effect of the channel coding.


20/27

20

Avoid catastrophic encoders

Fig: Effect of the Catastrophic Encoder.


21/27

21

Fig: Effect of increasing constraint.


22/27

22Fig: Effect of increasing free distance.


23/27

S.N. Components Nos. Cost per unit (RS) Cost (RS)1. Microcontroller

(AT89s52)1 175 175

2. Crystal 1 30 30

3. D Flip-flop 2 30 60

4. XOR gate 2 25 50

5. Buffer (74LS244) 1 60 60

6. MAX 232 1 120 120

7. FPGA (Spartan 3E) 1 12,500 12,500

8. Serial Connector 1 50 50

9. Serial Cable 1 500 500

10. Resistors 20

11. Capacitors 20

12. Connecting Wires 50

13. Miscellaneous 1000

Total 14,63523


24/27

Performance of the convolution code is not comparedwith performance of other channel coding techniques.

System is implemented for randomly generated digitaldata

Convolutional code of rate and constraint length 3 isused

Wired channel is used for hardware implementation

Trace back method could be used for survivor memorymanagement

Mechanism for introducing error is not provided inhardware

24


25/27

System is simulated in MATLAB

Viterbi Decoder is implemented in FPGA.

Register exchange is used for survivor memory

management For same SNR BER of the system decreased for using

channel coding.

25


26/27

1. S. Haykin, "Digital Communication", Wiley, 1988.

2. B. P. Lathi, "Modern Digital and Analog Communication Systems", third edition, Oxforduniversity press, 1998

3. Fu-hau Huang, "Evaluation of Soft Output Decoding for Turbo Codes, Chapter-2(Convolutional Codes),Master's Thesis, 29 May, 1997.

4. MATLAB documentation.

5. Ranjan Bose, "An efficient method to calculate the free distance of convolutional codes",Paper, Department of Electrical Engineering, Indian Institute of Technology, Hauz Khas, NewDelhi.

6. J. Das, S. K. Mullick and P. K. Chatterjee, "Principles of Digital Communication", Willey, 1986.

7. Feng Lo, "FPGA Realization of the Viterbi Decoder for HDSL2 Systems", Paper, Department ofElectrical Engineering, National Central University, Taiwan.

8. D. K. Sharma, "Communication Systems-II", Course Manual, Institute of Engineering,Tribhuvan University, 1999.

9. R. Shakya, S. Maharjan, S. Tuladhar, S.R. Shrestha, CDMA Based Personal CommunicationSystem, Department of Electronics and Computer Engineering, Pulchowk Campus, IOE, March2009.

26


27/27

1. Charles H. Roth, Jr, Digital Systems Design Using VHDL, PWS Publishing Company,1998.

2. C. Maxfield, The Design Warriors Guide to FPGAs, Newnes Publication, 2004.

3. FPGA-Based Control: Millions of Transistors at Your Command, National InstrumentsDeveloper zone.

4. XILINX, Spartan-3E Starter Kit Board User Guide, UG230 (v1.0), March 2006

5. Wikipedia, Linear Feedback Shift Register, http://en.wikipedia.org/wiki/linearfeedbackshift register.

6. L. Van de Meeberg, "A Viterbi Decoder", Report, Eindhoven University of Technology TheNederlands, Department of Electrical Engineering, October 1974.

7.

8. Hema S., Suresh Babu V., Ramesh P.,FPGA Implementation of Viterbi Decoder, Paper,Kerala University, College of Engineering Trivandrum, Dept of ECE, India, February 2007.

9. Chaiwat Keawsai, Keattisak Sripimanwat , and Attasit Lasaku, Modified Register ExchangeMethod of Viterbi Decoder for 3GPP Mobile System, Paper, King Mongkut's Institute ofTechnology, Department of Information Engineering, Thiland.

27
http://en.wikipedia.org/wiki/linearhttp://en.wikipedia.org/wiki/linear

Implementation of Viterbi Decoder

Documents

Transcript of Implementation of Viterbi Decoder