VHDL

ELCTRONICS AND COMMUNICATION ENGINEERING

ECADLAB(VHDL) 1

INTRODUCTION TO VHDL

What is VHDL?

VHDL is the VHSIC Hardware Description Language. VHSIC is an abbreviation for Very

High Speed Integrated Circuit. It can describe the behavior and structure of electronic

systems, but is particularly suited as a language to describe the structure and behavior

of digital electronic hardware designs, such as ASICs and FPGAs as well as

conventional digital circuits.

VHDL is a notation, and is precisely and completely defined by the Language Reference

Manual (LRM). This sets VHDL apart from other hardware description languages, which

are to some extent defined in an ad hoc way by the behavior of tools that use them.

VHDL is an international standard, regulated by the IEEE. The definition of the language

is non-proprietary.

VHDL is not an information model, a database schema, a simulator, a toolset or a

methodology! However, a methodology and a toolset are essential for the effective use

of VHDL.

Simulation and synthesis are the two main kinds of tools which operate on the VHDL

language. The Language Reference Manual does not define a simulator, but

unambiguously defines what each simulator must do with each part of the language.

VHDL does not constrain the user to one style of description. VHDL allows designs to be

described using any methodology - top down, bottom up or middle out! VHDL can be

used to describe hardware at the gate level or in a more abstract way. Successful high

level design requires a language, a tool set and a suitable methodology. VHDL is the

language, you choose the tools, and the methodology... well, I guess that's where

Doulos come in to the equation!


ECADLAB(VHDL) 2

A Brief History of VHDL

The development of VHDL was initiated in 1981 by the United States Department of

Defense to address the hardware life cycle crisis. The cost of reprocuring electronic

hardware as technologies became obsolete was reaching crisis point, because the

function of the parts was not adequately documented, and the various components

making up a system were individually verified using a wide range of different and

incompatible simulation languages and tools. The requirement was for a language with a

wide range of descriptive capability that would work the same on any simulator and was

independent of technology or design methodology.

Standardization

The standardization process for VHDL was unique in that the participation and feedback

from industry was sought at an early stage. A baseline language (version 7.2) was

published 2 years before the standard so that tool development could begin in earnest in

advance of the standard. All rights to the language definition were given away by the

DoD to the IEEE in order to encourage industry acceptance and investment.

ASIC Mandate

DoD Mil Std 454 mandates the supply of a comprehensive VHDL description with every

ASIC delivered to the DoD. The best way to provide the required level of description is to

use VHDL throughout the design process.


ECADLAB(VHDL) 3

VHDL '93

As an IEEE standard, VHDL must undergo a review process every 5 years (or sooner) to

ensure its ongoing relevance to the industry. The first such revision was completed in

September 1993, and tools conforming to VHDL '93 are now available.

Summary: History of VHDL

1981 - Initiated by US DoD to address hardware life-cycle crisis

1983-85 - Development of baseline language by Intermetrics, IBM and TI

1986 - All rights transferred to IEEE

1987 - Publication of IEEE Standard

1987 - Mil Std 454 requires comprehensive VHDL descriptions to be delivered with

ASICs

1994 - Revised standard (named VHDL 1076-1993)


ECADLAB(VHDL) 4

Levels of Abstraction

VHDL can be used to describe electronic hardware at many different levels of

abstraction. When considering the application of VHDL to FPGA/ASIC design, it is

helpful to identify and understand the three levels of abstraction shown opposite -

algorithm, register transfer level (RTL), and gate level. Algorithms are unsynthesizable,

RTL is the input to synthesis, gate level is the output from synthesis. The difference

between these levels of abstraction can be understood in terms of timing.

Levels of abstraction in the context of their time domain

Algorithm

A pure algorithm consists of a set of instructions that are executed in sequence to

perform some task. A pure algorithm has neither a clock nor detailed delays. Some

aspects of timing can be inferred from the partial ordering of operations within the

algorithm. Some synthesis tools (behavioral synthesis) are available that can take

algorithmic VHDL code as input. However, even in the case of such tools, the VHDL

input may have to be constrained in some artificial way, perhaps through the presence of

an ‘algorithm' clock - operations in the VHDL code can then be synchronized to this

clock.


ECADLAB(VHDL) 5

RTL

An RTL description has an explicit clock. All operations are scheduled to occur in

specific clock cycles, but there are no detailed delays below the cycle level.

Commercially available synthesis tools do allow some freedom in this respect. A single

global clock is not required but may be preferred. In addition, retiming is a feature that

allows operations to be re-scheduled across clock cycles, though not to the degree

permitted in behavioral synthesis tools.

Gates

A gate level description consists of a network of gates and registers instanced from a

technology library, which contains technology-specific delay information for each gate.

Writing VHDL for Synthesis

In the diagram above, the RTL level of abstraction is highlighted. This is the ideal level of

abstraction at which to design hardware given the state of the art of today's synthesis

tools. The gate level is too low a level for describing hardware - remember we're trying to

move away from the implementation concerns of hardware design, we want to abstract

to the specification level - what the hardware does, not how it does it. Conversely, the

algorithmic level is too high a level, most commercially available synthesis tools cannot

produce hardware from a description at this level.

In the future, as synthesis technology progresses, we will one day view the RTL level of

abstraction as the “dirty” way of writing VHDL for hardware and writing algorithmic (often

called behavioral) VHDL will be the norm.


ECADLAB(VHDL) 6

Scope of VHDL

VHDL is suited to the specification, design and description of digital electronic hardware.

System level

VHDL is not ideally suited for abstract system-level simulation, prior to the hardware-

software split. Simulation at this level is usually stochastic, and is concerned with

modeling performance, throughput, queuing and statistical distributions. VHDL has been

used in this area with some success, but is best suited to functional and not stochastic

simulation.

Digital

VHDL is suitable for use today in the digital hardware design process, from specification

through high-level functional simulation, manual design and logic synthesis down to

gate-level simulation. VHDL tools usually provide an integrated design environment in

this area.

VHDL is not suited for specialized implementation-level design verification tools such as

analog simulation, switch level simulation and worst case timing simulation. VHDL can

be used to simulate gate level fan-out loading effects providing coding styles are

adhered to and delay calculation tools are available. The standardization effort named

VITAL (VHDL Initiative toward ASIC Libraries) is active in this area, and is now bearing

fruit in that simulation vendors have built-in VITAL support. More importantly, many ASIC

vendors have VITAL-compliant libraries, though not all are allowing VITAL-based sign-

off - not yet anyway.

Analogue

In 1999, the IEEE approved Standard 1076.1, which is informally known as VHDL-AMS.

It is a true super-set of VHDL, and includes analog and mixed-signal extensions.


ECADLAB(VHDL) 7

Design process

The diagram below shows a very simplified view of the electronic system design process

incorporating VHDL. The central portion of the diagram shows the parts of the design

process which are most impacted by VHDL.

Design Flow using VHDL

The diagram below summarizes the high level design flow for an ASIC (ie. gate array,

standard cell) or FPGA. In a practical design situation, each step described in the

following sections may be split into several smaller steps, and parts of the design flow

will be iterated as errors are uncovered.

System-level Verification

As a first step, VHDL may be used to model and simulate aspects of the complete

system containing one or more devices. This may be a fully functional description of the

system allowing the FPGA/ASIC specification to be validated prior to commencing

detailed design. Alternatively, this may be a partial description that abstracts certain

properties of the system, such as a performance model to detect system performance

bottle-necks.


ECADLAB(VHDL) 8

RTL design and test bench creation

Once the overall system architecture and partitioning is stable, the detailed design of

each FPGA/ASIC can commence. This starts by capturing the design in VHDL at the

register transfer level, and capturing a set of test cases in VHDL. These two tasks are

complementary, and are sometimes performed by different design teams in isolation to

ensure that the specification is correctly interpreted. The RTL VHDL should be

synthesizable if automatic logic synthesis is to be used. Test case generation is a major

task that requires a disciplined approach and much engineering ingenuity: the quality of

the final FPGA/ASIC depends on the coverage of these test cases.

RTL verification

The RTL VHDL is then simulated to validate the functionality against the specification.

RTL simulation is usually one or two orders of magnitude faster than gate level

simulation, and experience has shown that this speed-up is best exploited by doing more

simulation, not spending less time on simulation. In practice it is common to spend 70-

80% of the design cycle writing and simulating VHDL at and above the register transfer

level, and 20-30% of the time synthesizing and verifying the gates.

Look-ahead Synthesis

Although some exploratory synthesis will be done early on in the design process, to

provide accurate speed and area data to aid in the evaluation of architectural decisions

and to check the engineer's understanding of how the VHDL will be synthesized, the

main synthesis production run is deferred until functional simulation is complete. It is

pointless to invest a lot of time and effort in synthesis until the functionality of the design

is validated.


ECADLAB(VHDL) 9

Benefits of using VHDL

Executable specification

It is often reported that a large number of ASIC designs meet their specifications first

time, but fail to work when plugged into a system. VHDL allows this issue to be

addressed in two ways: A VHDL specification can be executed in order to achieve a high

level of confidence in its correctness before commencing design, and may simulate one

to two orders of magnitude faster than a gate level description. A VHDL specification for

a part can form the basis for a simulation model to verify the operation of the part in the

wider system context (eg. printed circuit board simulation). This depends on how

accurately the specification handles aspects such as timing and initialization. Behavioral

simulation can reduce design time by allowing design problems to be detected early on,

avoiding the need to rework designs at gate level. Behavioral simulation also permits

design optimization by exploring alternative architectures, resulting in better designs.


ECADLAB(VHDL) 10

Getting Started With Active-HDL


ECADLAB(VHDL) 11

Click Active-HDL 6.3 icon on desktop then above window will be appeared on the

screen Select create new work space and press ok


ECADLAB(VHDL) 12

Type the name in the box under Type the workspace name: and press ok


ECADLAB(VHDL) 13

Select create an empty design and press next


ECADLAB(VHDL) 14

Click on the button indicated by an arrow located under Synthesis tool: and select

Xilinx XST Vhdl .


ECADLAB(VHDL) 15

The above window will be appeared and then press Next .


ECADLAB(VHDL) 16

Type a name for the design in the box which is under Type the design name and press

Next.


ECADLAB(VHDL) 17

Click on Finish button.


ECADLAB(VHDL) 18

Right click on Add New File then select New and left click on VHDL Source


ECADLAB(VHDL) 19

The above window will be appeared and press Next


ECADLAB(VHDL) 20

Type a name in the box under Type the name of the source file to create:

Type a name in the box under Type the name of the entity(optional):

Type a name in the box under Type the name of the architecture body(optional): and

press Next


ECADLAB(VHDL) 21

The above window will be appeared and press Finish button


ECADLAB(VHDL) 22

The above window will be appeared. Then enter the code for your design


ECADLAB(VHDL) 23

Then press Compile button shown on the top and in the console box #compile

success 0 errors 0 warnings analysis time : 0.2 [s] will be appeared if the code is

correct


ECADLAB(VHDL) 24

Left click on the waveform button


ECADLAB(VHDL) 25

Click on waveform and select Add signals


ECADLAB(VHDL) 26

The above windows will be appeared right click on the input, output signals and click

on select all and press Add button


ECADLAB(VHDL) 27

The above window will be appeared


ECADLAB(VHDL) 28

Right click on the input signal a and click on Simulators and proceed the same process

for other input signals also


ECADLAB(VHDL) 29

The above windows will be appeared select Clock in the box under Type: give some

clock shown below and we can select 1 or 0 and then press Apply button and then press

close button


ECADLAB(VHDL) 30

The above window will be appeared.


ECADLAB(VHDL) 31

Select Simulation and left click on Initialize Simulation


ECADLAB(VHDL) 32

The above window will be appeared as #Simulation has been initialized


ECADLAB(VHDL) 33

After simulation has been finished select run time and press (Alt+F5) or

run button as shown on the top


ECADLAB(VHDL) 34

The Simulation results will be appeared as depicted in the above window


ECADLAB(VHDL) 35

EXPERIMENT NO.1: GATES

AIM: To simulate internal structure of all gates using VHDL and verify their operation.

APPARATUS:

S.NO COMPONENT QUANTITY

1. IC 7400 1

2. IC 7402 1

3. IC 7404 1

4. IC 7408 1

5. IC 7436 1

6. IC 7486 1

7. IC CD74HC7266 1

8. Digital Trainer Board 1

SOFTWARE USED: Active-HDL

THEORY:

Logic gates: Digital systems are said to be constructed by using logic gates. These

gates are the AND, OR, NOT, NAND, NOR, EXOR and EXNOR gates. The basic

operations are described below with the aid of truth tables.

AND gate

The AND gate is an electronic circuit that gives a high output (1) only if all

its inputs are high. A dot (.) is used to show the AND operation i.e. A.B

for a two input (A & B) AND gate, Y = A.B. Bear in mind that this dot is

sometimes omitted i.e. written as AB


ECADLAB(VHDL) 36

OR gate

The OR gate is an electronic circuit that gives a high output (1) if one or

more of its inputs are high. A plus (+) is used to show the OR operation.

E.g. output of a 2-input OR gate is Y=A+B.

NOT gate

The NOT gate is an electronic circuit that produces an inverted version of the

input at its output. It is also known as an inverter. If the input variable is A, the

inverted output is known as NOT A. This is also shown as A', or A with a bar

over the top, as shown at the output, i.e., Y= A'

NAND gate

This is a NOT-AND gate which is equal to an AND gate followed by a

NOT gate. The output of a NAND gate is high if any of its inputs are low.

The symbol is an AND gate with a small circle on the output. The small

circle represents inversion.

For a two input(A & B) NAND gate, output Y = (A.B)′ .


ECADLAB(VHDL) 37

NOR gate

This is a NOT-OR gate which is equal to an OR gate followed by a NOT

gate. The output of a NOR gate is low if any of the inputs are high.

The symbol is an OR gate with a small circle on the output. The small

circle represents inversion. For a two input(A & B) NOR gate, output Y =

(A+B)′ .

EXOR gate

The 'Exclusive-OR' gate is a circuit which will give a high output if either,

but not both, of its two inputs are high. An encircled plus sign ( ) is used

to show the EOR operation.When inputs are A and B,output Y of EXOR

gate is Y=A B

EXNOR gate

The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It

will give a low output if either, but not both, of its two inputs are high.

The symbol is an EXOR gate with a small circle on the output. The small

circle represents inversion.The output Y of a EXNOR gate with inputs

A&B is given by Y=( A B)′ .


ECADLAB(VHDL) 38

The NAND and NOR gates are called universal gates since with either one the

AND and OR functions and NOT can be generated.

Table 1 is a summary truth table of the input/output combinations for the NOT gate

together with all possible input/output combinations for the other gate functions. Also

note that a truth tables with 'n' inputs has 2n rows. You can compare the outputs of

different gates.

Table 1: Logic gates representation using the Truth table


ECADLAB(VHDL) 39

INTERNAL DIAGRAM:

NOR GATE:

NAND GATE:


ECADLAB(VHDL) 40

AND GATE:

NOT GATE:


ECADLAB(VHDL) 41

OR GATE:

ALL GATES Output Equations:

Y = A AND B; Y = A OR B;

Y = A NAND B; Y = A NOR B;

Y = A EXOR B; Y = A EXNOR B;

ECADLAB(VHDL) 42

VHDL CODE:

library IEEE;

use IEEE.std_logic_1164.all;

entity gates is

port ( a: in STD_LOGIC;

b: in STD_LOGIC;

and1: out STD_LOGIC;

or1: out STD_LOGIC;

nor1: out STD_LOGIC;

nand1: out STD_LOGIC;

xor1: out STD_LOGIC;

xnor1: out STD_LOGIC);

end gates;

architecture gates of gates is

begin

and1 <= a and b;

or1 <= a or b;

nor1 <= a nor b;

nand1 <= a nand b;

xor1 <= a xor b;

xnor1 <= a xnor b;

end gates;


ECADLAB(VHDL) 43

EXPECTED RESULTS (HARDWARE):

AND GATE OR GATE

NAND GATE NOR GATE

EX-OR GATE EX-NOR GATE

INPUTS OUTPUT

A B Y

0V 0V 0V

0V 5V 0V

5V 0V 0V

5V 5V 5V

INPUTS OUTPUT

A B Y

0V 0V 0V

0V 5V 5V

5V 0V 5V

5V 5V 5V

INPUTS OUTPUT

A B Y

0V 0V 5V

0V 5V 0V

5V 0V 0V

5V 5V 0V

INPUTS OUTPUT

A B Y

0V 0V 5V

0V 5V 5V

5V 0V 5V

5V 5V 0V

INPUTS OUTPUT

A B Y

0V 0V 0V

0V 5V 5V

5V 0V 5V

5V 5V 0V

INPUTS OUTPUT

A B Y

0V 0V 5V

0V 5V 0V

5V 0V 0V

5V 5V 5V


ECADLAB(VHDL) 44

EXPECTED RESULTS (SOFTWARE):

AND GATE : when all inputs are high output should be high.

OR GATE : when any of input is high output should be high.

NAND GATE : when any of input is low output should be high.

NOR GATE : when any of input is high output should be low.

EX-OR GATE: when input combination contains odd number of

Ones then only output should be high.

EX-NOR GATE: when input combination contains even number of

ones then only output should be high.


ECADLAB(VHDL) 45

Fig: Compilation Report of ALL GATES


ECADLAB(VHDL) 46

RESULTS (HARDWARE):

AND GATE OR GATE

NAND GATE NOR GATE

EX-OR GATE EX-NOR GATE

INPUTS

A B

OUTPUT

LED

0 0 OFF

0 1 OFF

1 0 OFF

1 1 ON

INPUTS

A B

OUTPUT

LED

0 0 OFF

0 1 ON

1 0 ON

1 1 ON

INPUTS

A B

OUTPUT

LED

0 0 ON

0 1 OFF

1 0 OFF

1 1 OFF

INPUTS

A B

OUTPUT

LED

0 0 ON

0 1 ON

1 0 ON

1 1 OFF

INPUTS

A B

OUTPUT

LED

0 0 OFF

0 1 ON

1 0 ON

1 1 OFF

INPUTS

A B

OUTPUT

LED

0 0 ON

0 1 OFF

1 0 OFF

1 1 ON


ECADLAB(VHDL) 47

RESULTS (SOFTWARE):

Fig: Simulation Report of ALL GATES


ECADLAB(VHDL) 48

Fig: Simulation Results of ALL GATES


ECADLAB(VHDL) 49

RESULT:

ALL GATES Internal Structures are Simulated and Verified Using Active-HDL

Software and in Hardware Lab Respectively.

INFERENCE:

Theoretical and Practical Results are according to the expected results both for Software

and Hardware.

PRECAUTIONS (SOFTWARE):

1) Follow Getting Started Procedure for the Software you are using.

2) Don’t Forget to instantiate IEEE Libraries At the starting of

the code

3) Follow Syntax and Semantics of the VHDL code throughout

PRECAUTIONS (HARDWARE):

1) Apply the voltages to the IC as per the details given in the data

Sheets.

2) Apply the inputs to the respective pins.

3) First decide which one is MSB and LSB.

4) Take the outputs at appropriate pins.


ECADLAB(VHDL) 50

QUESTIONS & ANSWERS:

1) Draw internal diagram of nand gate using RTL logic.

Ans:

2) What are the universal gates ?

Ans: NAND and NOR gates are called as universal gates.

3) What is the main difference between Exor and Exnor gates ?

Ans: Whenever inputs are same output is low - Exor gate

Whenever inputs are same output is high- Exnor gate

4) What are the Minimum number of nand gates required to implement

Exor gate ?

Ans : FOUR nand gates are required to implement Exor gate


ECADLAB(VHDL) 51

5) Implement basic gates using DTL & TTL Logic ?

Ans:

Fig: DTL NAND GATE

Fig: DTL OR GATE


ECADLAB(VHDL) 52

+VCC = +5V

Q1

2N2222A

Q2

2N2222A

Q3

2N2222A

Q4

2N2222A

R1

0Ohm_1%R2

0Ohm_1%

R3

0Ohm_1%

R4

0Ohm_1%D1

1BH62

D2

1BH62

Fig: TTL INVERTER


ECADLAB(VHDL) 53

Fig: TTL NAND GATE


ECADLAB(VHDL) 54

Fig: TTL NOR GATE


ECADLAB(VHDL) 55

Fig: TTL OR GATE

PROCEDURE (SOFTWARE):

1) Follow Getting Started Procedure for the Software you are

using.

2) Don’t forget to instantiate IEEE Libraries at the starting of

the code.

PROCEDURE (HARDWARE):

1) Connect the circuit as per the pin diagram.

2) Give proper VCC voltage to the IC.

3) Supply the inputs according to truth table and verify outputs.


ECADLAB(VHDL) 56

EXPERIMENT NO.2: D FLIP-FLOP

AIM: To Simulate internal structure of D FLIP FLOP(IC 7474) using VHDL and verify

Its operation.

APPARATUS:


1. IC 7474 1



THEORY:

The IC7474 contains two independent positive-edge-triggered D-type flip-flops with

complementary outputs. The information on the D input is accepted by the flip-flops on

the positive going edge of the clock pulse. The triggering occurs at a voltage level and is

not directly related to the transition time of the rising edge of the clock. The data on the

D input may be changed while the clock is low or HIGH without affecting the outputs as

long as the data setup and hold times are not violated. A LOW logic level on the preset

or clear inputs will set or reset the outputs regardless of the logic levels of the other

inputs. 74LS74 is a dual positive edge triggered D-type FF. It’s features are individual

data Clock Set and reset inputs and Complementary Q and Q΄outputs .The clock input is

level-sensitive. The positive transition of clock pulse between 0.8V and 2.0V should be

equal.


ECADLAB(VHDL) 57

D-FLIP FLOP DETAILS:

PIN DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUTS

PR CLR CLK D Q Q*

L H X X H L

H L X X L H

L L X X H H

H H

H H L

H H

L L H

H H L X Q0 Q0*

H = HIGH Logic Level X = Either LOW or HIGH Logic Level Clear

L = LOW Logic Level ↑ = Positive-going transition of the clock.

Q0 = The output logic level of Q before the indicated input conditions were and

established.


ECADLAB(VHDL) 58

INTERNAL DIAGRAM:

D FLIP- FLOP Output Equations:

D = Qt+1

ECADLAB(VHDL) 59

VHDL CODE:

library IEEE;


entity dff is

port (

d: in STD_LOGIC;

clk: in STD_LOGIC;

clr: in STD_LOGIC;

pr: in STD_LOGIC;

q: out STD_LOGIC;

qbar: out STD_LOGIC);

end dff;

architecture dff of dff is

signal clr1,pr1:std_logic;

begin

clr1<=not clr;

pr1<=not pr;

process(clk,clr1,pr1)

begin

if(pr1='1'and clr1='1')then q<='0';qbar<='0';

elsif(pr1='1'and clr1='0')then q<='1';qbar<='0';

elsif(pr1='0'and clr1='1')then q<='0';qbar<='1';

elsif(clk'event and clr1='1')then q<=d;qbar<=not d;

end if;

end process;

end dff;


ECADLAB(VHDL) 60


INPUTS OUTPUTS

PR CLR CLK D Q Q*

0 1 X X 5V 0V

1 0 X X 0V 5V

0 0 X X 5V 5V

1 1

1 5V 0V

1 1

0 0V 5V

1 1 0 X Q0 Q0*


When pr = 0, clr = 1 irrespective of clock and D input Q = 1, Q* = 0.



When pr = 1, clr = 1, clock transition is positive and D = 1, Q = 1, Q* = 0.

When pr = 1, clr = 1, clock transition is positive and D = 0, Q = 0, Q* = 1.

When pr = 1, clr = 1, clock = 0, irrespective of D input Q = Q0, Q* = Q0*

Q0 = The output logic level of Q before the indicated input conditions were and

established.


ECADLAB(VHDL) 61

Fig: Compilation Report of D FLIP- FLOP


ECADLAB(VHDL) 62

RESULTS (HARDWARE):

INPUTS OUTPUTS

PR CLR CLK D Q LED Q* LED

0 1 X X ON OFF

1 0 X X OFF ON

0 0 X X ON ON

1 1

1 ON OFF

1 1

0 OFF ON

1 1 0 X Q0 Q0*


ECADLAB(VHDL) 63

RESULTS (SOFTWARE):

Fig: Simulation Report of D FLIP- FLOP


ECADLAB(VHDL) 64

Fig: Simulation Results of D FLIP- FLOP


ECADLAB(VHDL) 65

RESULT:

D FLIP-FLOP Internal Structure is Simulated and Verified Using Active HDL


INFERENCE:


and Hardware.



2) Don’t Forget to instantiate IEEE Libraries at the starting of

the code

3) Follow Syntax and Semantics of the VHDL code throughout



Sheets.



4)Take the outputs at appropriate pins.


ECADLAB(VHDL) 66


1. Why it is called D-FF?

Ans: Due to the reason of transmitting whatever is given as input.

2. Applications of D-FF.

Ans: we can design any circuit easily with D-FF because only one input is involved..

3. Difference between edge-triggered FF, level sensitive FF and master slave FF.

Ans: Edge Triggered FF responds for 1 to 0 (or) 0 to 1 transition whereas level sensitive

FF’s

respond to the level 1(or) 0.

In master-slave FF if the master respond for positive edge then slave responds for

negative

edge.

4. What is a Flip-Flop?

Ans: Flip-Flop is a one bit storage device. It is having two outputs one for normal value

and one for the complement value of the bit stored in it.

5. Explain the operation of D Flip-Flop?

Ans: The binary information present at the data input of the D Flip-Flop is transferred to

Q output when clock pulse input is enabled.

6. What is the advantage of D Flip-Flop when compared with RS Flip-Flop?

Ans: The undesirable condition of indeterminate state in RS Flip-Flop is eliminated in

D Flip-Flop

7. Why D Flip-Flop sometimes called as gated D latch?

Ans: The D Flip-Flop receives the designation from its ability to hold data into its internal

storage such a type of Flip-Flop sometimes called as gated D latch.


ECADLAB(VHDL) 67


1)Follow Getting Started Procedure for the Software you are

using.


the code.






ECADLAB(VHDL) 68

EXPERIMENT NO. 3: DECADE COUNTER

AIM: To Simulate internal structure of Decade Counter(IC 7490) using VHDL and verify

Its operation.

APPARATUS:

HARDWARE:


1. IC 7490 1


SOFTWARE: Active-HDL

THEORY:

7490 is a 4-bit ripple type decade counter.

Features are:

Output QA is connected to input B for BCD count. Output QD is connected

to input A for qi-binary count. This counter has a gated ‘O’ reset. This

counter contains 4 master-slave FF’s and additional gating to provide a

divide by two counter.


ECADLAB(VHDL) 69

TRUTH TABLE:

OUTPUT COUNT

QD QC QB QA

0 L L L L

1 L L L H

2 L L H L

3 L L H H

4 L H L L

5 L H L H

6 L H H L

7 L H H H

8 H L L L

9 H L L H

H = HIGH; L = LOW


ECADLAB(VHDL) 70

INTERNAL DIAGRAM:

Decade Counter Output Equations:

OUTPUT Q = 0000 when INPUTS ro(1)= 1, ro(2) = 1 and rg(1)= 0 ;

OUTPUT Q = 1001 when INPUTS rg(1)= 1 and rg(2) = 1;

OUTPUT Q = Q + 1 when clock is HIGH

ECADLAB(VHDL) 71

VHDL CODE:

library IEEE;


use IEEE.std_logic_arith.all;

entity dcounter is

port (

clk: in STD_LOGIC;

ro: in STD_LOGIC_VECTOR (2 downto 1):="00";

rg: in STD_LOGIC_VECTOR (2 downto 1):="00";

q:inout unsigned(3 downto 0):="0000"

);

end dcounter;

architecture dcounter of dcounter is

begin

process(clk)

begin

if(ro(1)='1'and ro(2)='1'and rg(1)='0')then q<="0000";

elsif(ro(1)='1'and ro(2)='1'and rg(2)='0')then q<="0000";

elsif(rg(1)='1'and rg(2)='1')then q<="1001";

elsif(clk'event and clk='1')then q<=q+1;

if(q="1001")then q<="0000";

end if;

end if;

end process;

end dcounter;


ECADLAB(VHDL) 72


OUTPUT COUNT

QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1


Reset inputs Output

RO(1) RO(2) RG(1) RG(2) QD QC QB QA

H H L X L L L L

H H X L L L L L

X X H H H L L H

X L

X

L

COUNT

L X L X COUNT

L

X

X

L

COUNT

X L L X COUNT


ECADLAB(VHDL) 73

Fig: Compilation Report of Decade Counter


ECADLAB(VHDL) 74

RESULTS (HARDWARE):

OUTPUT COUNT

QD LED QC LED QB LED QA LED

0 OFF OFF OFF OFF

1 OFF OFF OFF ON

2 OFF OFF ON OFF

3 OFF OFF ON ON

4 OFF ON OFF OFF

5 OFF ON OFF ON

6 OFF ON ON OFF

7 OFF ON ON ON

8 ON OFF OFF OFF

9 ON OFF OFF ON


ECADLAB(VHDL) 75

RESULTS (SOFTWARE):

Fig: Simulation Report of Decade Counter


ECADLAB(VHDL) 76

Fig: Simulation Results of Decade Counter


ECADLAB(VHDL) 77

RESULT:

Decade Counter internal structure is Simulated and verified using Active-HDL


INFERENCE:


and Hardware.




the code.

3) Follow Syntax and Semantics of the VHDL code throughout.


1) Apply the voltages to the IC as per the details given in the data sheets.





ECADLAB(VHDL) 78


1. Explain the operation binary counter.

Ans: A counter that follows the binary sequence is called binary counter. An n-bit

binary counter consists of n flip-flops and can count in binary from 0 to 2n-1.

2. What is difference between register and counter?

Ans: A Register is a group of binary cells where each cell stores one bit information.

A sequential circuit that goes through a prescribed sequence of states upon the

application of input pulses is called a counter.

3. What is a decade counter?

Ans: The BCD counter is a decade counter , since it counts from 0 to 9.

4. How many Decade counters are required to count from 0 to 999?

Ans: Three Decade counters are required to count from 0 to 999.

5. Applications of decade counter? Ans: A decade counter is also known as mod-10 counter or BCD counter. It is used In frequency counter, digital voltmeter, digital voltmeter, wrist watches etc. 6. Applications of counter? Ans: Digital system use counter in a variety of applications, such as digital clocks,

special sequence generators, time-delay circuits, pulse counters, control

state counters, program counters etc.


ECADLAB(VHDL) 79



2) Don’t forget to instantiate IEEE Libraries at the starting of the code.






ECADLAB(VHDL) 80

EXPERIMENT NO.4: 4 BIT COUNTER

AIM: To Simulate Internal structure of Four Bit Counter (IC 7493) using VHDL and

Verify its operation.

APPARATUS:


1. IC 7493 1



THEORY:

7493 is a 4- bit ripple type binary counter.

- The device consists of 4 master slaves Flip Flops internally connected to provide

Divide by two sections and a divide by eight sections.

- Independent use of first Flip Flop is available if reset function coincides with Reset

of 3-bit ripple through counter.


ECADLAB(VHDL) 81

4 BIT COUNTER DETAILS:

PIN DIAGRAM:

TRUTH TABLE:

OUTPUT COUNT

QO Q1 Q2 Q3

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 1 0 1

11 1 1 0 1

12 0 0 1 1

13 1 0 1 1

14 0 1 1 1

15 1 1 1 1

ECADLAB(VHDL) 82

INTERNAL DIAGRAM:

VHDL CODE:

library IEEE;


use IEEE.std_logic_arith.all;

entity counter4 is

port (

clk: in STD_LOGIC;

r: in STD_LOGIC_VECTOR (1 downto 0);

q: inout unsigned(3 downto 0):="0000" );

end counter4;

Architecture counter4 of counter4 is

begin

-- <<enter your statements here>>

process (clk)

begin

if(r(0)='1'and r(1)='1')then q<="0000";

elsif (clk'event and clk='1') then q<=q+1;

end if;

end process;

end counter4;


ECADLAB(VHDL) 83



If R0(1) ,R0(2) inputs are high then output will be low

else if any one of the input is high count will be increased by one.

OUTPUT COUNT

QO Q1 Q2 Q3

0 0V 0V 0V 0V

1 5V 0V 0V 0V

2 0V 5V 0V 0V

3 5V 5V 0V 0V

4 0V 0V 5V 0V

5 5V 0V 5V 0V

6 0V 5V 5V 0V

7 5V 5V 5V 0V

8 0V 0V 0V 5V

9 5V 0V 0V 5V

10 0V 5V 0V 5V

11 5V 5V 0V 5V

12 0V 0V 5V 5V

13 5V 0V 5V 5V

14 0V 5V 5V 5V

15 5V 5V 5V 5V


ECADLAB(VHDL) 84

Fig: Compilation Report of Four Bit Counter


ECADLAB(VHDL) 85

RESULTS (HARDWARE):

OUTPUT COUNT

QOLED Q1LED Q2LED Q3LED

0 OFF OFF OFF OFF

1 ON OFF OFF OFF

2 OFF ON OFF OFF

3 ON ON OFF OFF

4 OFF OFF ON OFF

5 ON OFF ON OFF

6 OFF ON ON OFF

7 ON ON ON OFF

8 OFF OFF OFF ON

9 ON OFF OFF ON

10 OFF ON OFF ON

11 ON ON OFF ON

12 OFF OFF ON ON

13 ON OFF ON ON

14 OFF ON ON ON

15 ON ON ON ON


ECADLAB(VHDL) 86

RESULTS (SOFTWARE):

Fig: Simulation Report of Four Bit Counter


ECADLAB(VHDL) 87

Fig: Simulation Results of Four Bit Counter


ECADLAB(VHDL) 88

RESULT:

Four Bit Counter internal structure is Simulated and verified using Active-HDL


INFERENCE:

Theoretical and Practical results are according to the expected results both for Software

and Hardware.



2) Don’t forget to instantiate IEEE Libraries At the starting of

the code.




Sheets.





ECADLAB(VHDL) 89


1. What is the difference between synchronous counter and asynchronous counter?

Ans: In asynchronous counter flip flops are connected in such a way that output of first

flip flop drives the clock for next flip flop.

In synchronous counter there is no connection between output of first flip flop and clock

input of next flip flop.

2. Which type of counter is preferred when there are more number of flip flops and why

such a type of counter is preferred?

Ans: synchronous counter is preferred because clock is simultaneously given to all flip

flops there is no problem of propagation delay

3. If a four-bit synchronous counter is designed with 4 flip flops and two AND gates then

determine f max if t pd (propagation delay time ) for each flip flop is 50ns and t pd for each

AND gate is 20ns?

Ans: For a synchronous counter total delay that must be allowed between input clock

pulses is equal to flip flop t pd + AND gate t pd .Thus Tclk 50 + 20 = 70ns and so counter

has f max = 1/ 70ns = 14.3Mhz.

4. A counter has 14 stable states 0000 through 1101 .If input frequency is 50khz what

will be its output frequency?

Ans: Input frequency /number of stable states = output frequency

50 kHz / 14 = 3.57 kHz.


ECADLAB(VHDL) 90


1)Follow Getting Started Procedure for the Software you are

using.

2)Don’t Forget to instantiate IEEE Libraries at the starting of

the code.






ECADLAB(VHDL) 91

EXPERIMENT NO.5: SHIFT REGISTER

AIM: To Simulate Internal structure of Shift Register(IC 7495) using VHDL and verify

Its operation.

APPARATUS:


1. IC 7495 1



THEORY:

- IC 7495 is a 4-bit shift register with serial and parallel synchronous operating modes.

- It has serial data (DS) and 4 parallel data (D0-D3) inputs and 4 parallel outputs (Q0-

Q3).


ECADLAB(VHDL) 92

TRUTH TABLE:


ECADLAB(VHDL) 93

INTERNAL DIAGRAM:

SHIFT REGISTER OUTPUT EQUATIONS:

QA = (A(MC) + (MC) (SI))`

QB = (B(MC) + (MC) (QA))`

QC = (C(MC) + (MC) (QB))`

QD = (D(MC) + (MC) (QC))`

MC = Mode Control

SI = Serial Input

ECADLAB(VHDL) 94

VHDL CODE:

library IEEE;


entity pshift is

port (

clr: in STD_LOGIC;

ro: in STD_LOGIC;

lo: in STD_LOGIC;

clk: in STD_LOGIC;

s: in STD_LOGIC_VECTOR (0 to 1);

ih: in STD_LOGIC_VECTOR (0 to 3);

q: inout STD_LOGIC_VECTOR (0 to 3)

);

end pshift;

architecture pshift of pshift is

signal qin:std_logic_vector(0 to 3);

begin

process(clk,clr,ih,ro,lo,q,s)

begin

qin<=q;

if(clr=’0’)then q<=”0000”;

elsif(clk’event and clk=’1’)then

if(s=”11”)then q<=ih;

elsif(s=”01”)then q<=ro&qin(0)&qin(1)&qin(2);

elsif(s=”10”)then q(0)<=qin(1);q(1)<=qin(2);q(2)<=qin(3);q(3)<=lo;

elsif(s=”00”)then q<=qin;

end if;

end if;

end process;

end pshift;


ECADLAB(VHDL) 95


DATAIN inputs are “011010000” in that order.


S = 00 then Parallel load

S = 01 then Serial out

S = 10 then Left Shift

S = 11 then Parallel Out

0 0 0 0

1 0 0 0

1 1 0 0

0 1 1 0

1 0 1 1

0 1 0 1

0 0 1 0

0 0 0 1

0 0 0 0


ECADLAB(VHDL) 96

Fig: Compilation Report of Shift Register


ECADLAB(VHDL) 97

RESULTS (HARDWARE):

DATAIN inputs are “011010000” in that order.

QALED QBLED QCLED QDLED

OFF OFF OFF OFF

ON OFF OFF OFF

ON ON OFF OFF

OFF ON ON OFF

ON OFF ON ON

OFF ON OFF ON

OFF OFF ON OFF

OFF OFF OFF ON

OFF OFF OFF OFF


ECADLAB(VHDL) 98

RESULTS (SOFTWARE):

Fig: Simulation Report of Shift Register


ECADLAB(VHDL) 99

Fig: Simulation Results of Shift Register


ECADLAB(VHDL) 100

RESULT:

Shift Register internal structure is simulated and verified using Active-HDL Software

and in Hardware Lab Respectively.

INFERENCE:


and Hardware.



2) Don’t forget to instantiate IEEE Libraries At the starting of the code.



1) Apply the voltages to the IC as per the details given in the data Sheets.





ECADLAB(VHDL) 101


1) Explain the operation of shift register.

Ans: The binary information shifted from stage to stage within register upon application

of clock pulses. This type of shifting is essential for certain Arithmetic and logical

operations used in microprocessors. This gives rise to a group of registers called shift

registers.

2) What are the different types of shift registers?

Ans: Serial-in serial-out, Serial-in parallel-out, parallel-in serial-out, parallel-in parallel-

out, Bi-Directional shift register.

3) How shifting of data will occur in bidirectional shift register?

Ans: This type of register allows shifting of data either to the left or right side.

4) Draw the diagram for basic data movement in Pseudo-random binary sequence

generator.

Ans:

5. What are the different levels that are present in tristate buffer register?


ECADLAB(VHDL) 102

Ans: There are three levels in tristate buffer register they are high, low and high impedance levels. 6. Applications of shift register? Ans: Time delay: SISO can be used to introduce time delay from input to output. Ring counter: If output shift register is fed back to serial input then this can be used as a ring counter. Serial to parallel data conversion, parallel to serial data conversion.



using.

2) Don’t Forget to instantiate IEEE Libraries at the starting of

the code.






ECADLAB(VHDL) 103

EXPERIMENT NO.6: UNIVERSAL SHIFT REGISTER

AIM: To Simulate Internal structure of Universal Shift Register (IC 74194/195) using

VHDL and Verify its operation.

APPARATUS:


1. IC 74194/195 1



THEORY (HARDWARE):

The 74194 is a bidirectional shift register designed to incorporate virtually all of the

features a system designer want in a shift register. The circuit contains 46 equivalent

gates and features parallel inputs, parallel outputs, right-shift and left-shift serial inputs,

operating mode control inputs and a direct overriding clear line. The register has four

distinct modes of operation namely;

Parallel (Broadside) Load

Shift Right (In the direction of QA toward QD)

Shift Left (In the direction of QD toward QA)

Inhibit Clock (Do nothing)

Synchronous parallel loading is accomplished by applying the four bits of data and

taking both mode control inputs, S0 and S1, high. The data is loaded into the associated

flip flop and appears at the outputs after the positive transition of the clock input. During

loading, serial data flow is inhibited.

Shift right is accomplished synchronously with the rising edge of the clock pulse when S0

is high and S1 is low. Serial data for this mode is entered at the shift-left serial input.


ECADLAB(VHDL) 104

Clocking of the flip flop is inhibited when both mode control inputs are low. The mode

controls should be changed only while the clock input is high.

SHIFT REGISTER DETAILS:

PIN DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUTS

MODE SERIAL PARALLEL CLEAR

S1 S0

CLOCK

LEFT RIGHT A B C D

QA QB QC QD

L X X X X X X X X X L L L L

H X X L X X X X X X QA0 QB0 QC0 QD0

H H H X X a b c d a b c d

H L H X H X X X X H QAN QBN QCN

H L H X L X X X X L QAN QBN QCN

H H L H X X X X X QBN QCN QDN H

H H L L X X X X X QBN QCN QDN L

H L L X X X X X X X QA0 QB0 QC0 QD0


ECADLAB(VHDL) 105

INTERNAL DIAGRAM:

ECADLAB(VHDL) 106

UNIVERSAL SHIFT REGISTER OUTPUT EQUATIONS:

QA = (QB S0`+ A(S0)`+(S1)`)` + (S1)`(SRSI))`

QB = (QA S0`+ B(S0)`+(S1)`)` + (S1)`(QA))`

QC = (QB S0`+ C(S0)`+(S1)`)` + (S1)`(QB))`

QD = (QC S0`+ D(S0)`+(S1)`)` + (S1)`(QC))`

SRSI = Shift Right Serial Input

VHDL CODE:

library IEEE;


entity shift is

generic (n:integer:=4);

port (

r: in STD_LOGIC_VECTOR (n-1 down to 0);

e: in STD_LOGIC;

l: in STD_LOGIC;

w: in STD_LOGIC;

clk: in STD_LOGIC;

q: buffer STD_LOGIC_VECTOR (n-1 downto 0));

end shift;

architecture shift of shift is

begin

process

begin

wait until clk’event and clk=’1’;

if e=’1’ then

if l=’1’ then

q<=r;

ECADLAB(VHDL) 107

else contd…

gcnbits:for I in 0 to n-2 loop

q(i)<= q(i+1);

end loop;

q(n-1)<=w;

end if;

end if;

end process;

end shift;


INPUTS OUTPUTS


S1 S0

CLOCK

LEFT RIGHT A B C D

QA QB QC QD

0 X X X X X X X X X 0 0 0 0

1 X X 0 X X X X X X QA0 QB0 QC0 QD0

1 1 1 X X a b c d a b c d

1 0 1 X 1 X X X X 1 QAN QBN QCN


1 1 0 1 X X X X X QBN QCN QDN 1


1 0 0 X X X X X X X QA0 QB0 QC0 QD0


clock= 1 ; input e= 1; input l= 1 output q = r ; output q(0) = q(1); q(1) = q(2); and so

on up to q(n-2) = q(n-1). q(n-1) = input w;


ECADLAB(VHDL) 108

Fig: Compilation Report of Universal Shift Register


ECADLAB(VHDL) 109

RESULTS (HARDWARE):

INPUTS OUTPUTS


S1 S0

CLOCK

LEFT RIGHT A B C D

QA QB QC QD

0 X X X X X X X X X 0 0 0 0

1 X X 0 X X X X X X QA0 QB0 QC0 QD0

1 1 1 X X a b c d a b c d





1 0 0 X X X X X X X QA0 QB0 QC0 QD0


ECADLAB(VHDL) 110

RESULTS (SOFTWARE):

Fig: Simulation Report of Universal Shift Register


ECADLAB(VHDL) 111

Fig: Simulation Results of Universal Shift Register


ECADLAB(VHDL) 112

RESULT:

Universal Shift Register internal structure is simulated and verified using Active HDL


INFERENCE:


and Hardware.











ECADLAB(VHDL) 113


1) What are the features of universal shift register

Ans: This register has both left and right shifts and parallel load capabilities.

2) Mention any two applications of shift register.

Ans: i) Delay line:

A Serial- in serial-out shift register used to introduce time delay in

digital signals. The time delay can be given as = N X 1/fc. (N = No. of stages, fc is

clock frequency).

ii) Pseudo random binary sequence (PRBS) generator:

A suitable feed back is used to generate PRBS.

3) What do you mean by parallel load in universal shift register?

Ans: The binary information on parallel input lines is transferred into the universal

shift register simultaneously.

4) Differentiate between bidirectional and universal shift registers.

Ans: Bidirectional shift register capable of shifting in both left and right directions.

Universal shift register has both left and right shifts and parallel load capabilities.


ECADLAB(VHDL) 114



using.


the code.






ECADLAB(VHDL) 115

EXPERIMENT NO.7: 3-to-8 DECODER

AIM: To Simulate the internal structure of a 3- to-8 decoder (IC 74138) using VHDL

and verify its operation.

APPARATUS:


1. IC 74LS138 1



THEORY:

These Schottky-clamped circuits are designed to be used in high-performance memory-

decoding or data-routing applications, requiring very short propagation delay times. In

high-performance memory systems these decoders can be used to minimize the effects

of system decoding. When used with high-speed memories, the delay times of these

decoders are usually less than the typical access time of the memory. This means that

the effective system delay introduced by the decoder is negligible. The DM74LS138

decodes one-of-eight lines; based upon the conditions at the three binary select inputs

and the three enable inputs. Two active-low and one active-high enable inputs reduce

the need for external gates or inverters when expanding. A 24-line decoder can be

implemented with no external inverters, and a 32-line decoder requires only one inverter.

An enable input can be used as a data input for demultiplexing applications. The

DM74LS139 comprises two separate two-line-to-four line decoders in a single package.

The active-low enable input can be used as a data line in demultiplexing applications. All

of these decoders/demultiplexers feature fully buffered inputs, presenting only one

normalized load to its driving circuit. All inputs are clamped with high-performance

Schottky diodes to suppress line-ringing and simplify system design.


ECADLAB(VHDL) 116

Absolute Maximum Ratings:

The “Absolute Maximum Ratings” are those values beyond which the safety of the

device cannot be guaranteed. The device should not be operated at these limits. The

parametric values defined in the Electrical Characteristics tables are not guaranteed at

the absolute maximum ratings. The “Recommended Operating Conditions” table will

define the conditions for actual device operation. An N-bit decoder has 2N outputs, only

one of which may be activated at a given time. If the device is active-HIGH, then only

one output may be HIGH at any time. If the device is active-LOW, then only one output

may be LOW at any time.

DECODER DETAILS:

TRUTH TABLE:

INPUTS OUTPUTS

G1 G2* C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

X L X X X H H H H H H H H

H X X X X H H H H H H H H

L H L L L H L L L L L L L

L H L L H L H L L L L L L

L H L H L L L H L L L L L

L H L H H L L L H L L L L

L H H L L L L L L H L L L

L H H L H L L L L L H L L

L H H H L L L L L L L H L

L H H H H L L L L L L L H

H = high level , L = low level, X = Don’t Care

G2* = G2*A + G2*B


ECADLAB(VHDL) 117

INTERNAL DIAGRAM:

3- 8 Decoder Output Equations:

Y0 = X2` X1` X0` Y4 = X2 X1` X0`

Y1 = X2 ` X1 `X0 Y5 = X2 X1 `X0

Y2 = X2 ` X1 X0` Y6 = X2 X1X0`

Y3 = X2 ` X1X0 Y7 = X2 X1X0

ECADLAB(VHDL) 118

VHDL CODE:

--This entity is a 3-to-8 decoder with a delay

-- (behavioral description)

ENTITY decoder IS

GENERIC (delay: TIME: = 5 NS);

PORT (sel: IN BIT_VECTOR (2 down to 0) ;

outZ: OUT BIT_VECTOR (7 down to 0)

);

END decoder;

ARCHITECTURE single delay OF decoder IS

BEGIN

WITH sel SELECT outZ <=

"00000001" AFTER delay WHEN "000",







"10000000" AFTER delay WHEN "111";

END single delay;


ECADLAB(VHDL) 119


INPUTS OUTPUTS

C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

0 0 0 5V 0V 0V 0V 0V 0V 0V 0V

0 0 1 0V 5V 0V 0V 0V 0V 0V 0V

0 1 0 0V 0V 5V 0V 0V 0V 0V 0V

0 1 1 0V 0V 0V 5V 0V 0V 0V 0V

1 0 0 0V 0V 0V 0V 5V 0V 0V 0V

1 0 1 0V 0V 0V 0V 0V 5V 0V 0V

1 1 0 0V 0V 0V 0V 0V 0V 5V 0V

1 1 1 0V 0V 0V 0V 0V 0V 0V 5V


Z7 Should be 1 when Sel = 000









ECADLAB(VHDL) 120

Fig: Compilation Report of 3-to-8 DECODER


ECADLAB(VHDL) 121

RESULTS (HARDWARE):

INPUTS OUTPUTS

G1 G2* C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

LED LED LED LED LED LED LED LED

X L X X X ON ON ON ON ON ON ON ON

H X X X X ON ON ON ON ON ON ON ON

L H L L L ON OFF OFF OFF OFF OFF OFF OFF

L H L L H OFF ON OFF OFF OFF OFF OFF OFF

L H L H L OFF OFF ON OFF OFF OFF OFF OFF

L H L H H OFF OFF OFF ON OFF OFF OFF OFF

L H H L L OFF OFF OFF OFF ON OFF OFF OFF

L H H L H OFF OFF OFF OFF OFF ON OFF OFF

L H H H L OFF OFF OFF OFF OFF OFF ON OFF

L H H H H OFF OFF OFF OFF OFF OFF OFF ON

H = high level , L = low level, X = Don’t Care

G2* = G2*A + G2*B


ECADLAB(VHDL) 122

RESULTS (SOFTWARE):

Fig: Simulation Report of 3-to-8 DECODER


ECADLAB(VHDL) 123

Fig: Simulation Results of 3-to-8 DECODER


ECADLAB(VHDL) 124

RESULT:

3-to-8 DECODER internal structure is Simulated and verified using Active-HDL


INFERENCE:


and Hardware.




the code.

3) Follow Syntax and Symantics of the VHDL code throughout.







ECADLAB(VHDL) 125


1) Explain about decoder.

Ans: A decoder is a multiple input, multiple output logic circuit which converts coded

inputs into coded outputs, where input and output codes are different. The input code

generally has fewer bits than output code.

2) Explain about binary decoder.

Ans: A decoder which has n-bit binary input code and one activated output out-of-2n

output code is called Binary decoder.

3) Explain basic concept of 3-to-8 line decoder.

Ans: Three inputs are decoded into eight outputs, each output represent one

of minterms of the three input variables.

4) Implement 3-to-8 line decoder using 2-to-4 line decoder ?

Ans:

Fig: 3 to 8 line decoder using 2 to 4 line decoder


ECADLAB(VHDL) 126








ECADLAB(VHDL) 127

EXPERIMENT NO.8: 4 BIT COMPARATOR

AIM: To Simulate internal structure of 4 Bit Comparator(IC 7485) using VHDL and


APPARATUS:


THEORY:

This four-bit magnitude comparator performs comparison of straight binary or BCD

codes. Three fully-decoded decisions about two, 4-bit words {A, B} are made and are

externally available at three outputs. This device is fully expandable to any number of

bits without external gates. Words of greater length may be compared by connecting

comparators in cascade. The A>B, A<B, and A=B outputs of a stage handling less

significant bits are connected to the corresponding inputs of the next stage handling

more-significant bits. The stage handling the least-significant bits must

have a high level voltage applied to the A=B input.


1. IC 7485 1

ECADLAB(VHDL) 128

FOUR BIT COMPARATOR DETAILS:

TRUTH TABLE:

COMPARING INPUTS CASCADING

INPUTS

OUTPUTS

A3>B3 A2>B2 A1>B1 AO>BO A>B AB AB3 X X X X X X X X X H L L

A3<B3 X X X X

X X X X X L H L

A3=B3 A2>B2 X X X X X X X H L L

A3=B3 A2<B2 X X X X X X X L H L

A3=B3 A2=B2 A1>B1 X X X X X H L L

A3=B3 A2=B2 A1<B1 X X X X X L H L

A3=B3 A2=B2 A1=B1 AO>BO X

X

X H L L

A3=B3

A2=B2

A1=B1

AO<BO X

X

X L H L

A3=B3

A2=B2 A1=B1 AO=BO H L L H L L

A3=B3 A2=B2 A1=B1 AO=BO L H L L H L

A3=B3 A2=B2

A1=B1

AO=BO L L H L L H

A3=B3

A2=B2

A1=B1

AO=BO

H H L L

L

L

A3=B3 A2=B2 A1=B1 AO=BO L L L H H L


ECADLAB(VHDL) 129

INTERNAL DIAGRAM:

ECADLAB(VHDL) 130

FOUR BIT COMPARATOR OUTPUT EQUATIONS:

A<B = (A3(A3B3)`)` ((A0B0)À0 + (A0B0)`B0)` (CIAGB) ((A1B1)À1 + (A1B1)`B1)` (A2B2)À2 +

(A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)` ((A0B0)À0 + (A0B0)`B0)` (CIAEQB) ((A1B1)À1

+(A1B1)`B1)` (A2B2)À2 + (A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)` ((A0) (A0B0)`

((A1B1)À1 +(A1B1)`B1)` (A2B2)À2 + (A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)`

((A1B1)À1(A2B2)À2 + (A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)` )( (A3B3)À3 +

(A3B3)`B3)`(A2B2)À2)`.

A>B = (B3(A3B3)`)` ((A0B0)À0 + (A0B0)`B0)` (CIALB) ((A1B1)À1 + (A1B1)`B1)` (A2B2)À2 +

(A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)` ((A0B0)À0 + (A0B0)`B0)` (CIAEQB) ((A1B1)À1

+(A1B1)`B1)` (A2B2)À2 + (A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)` ((B0) (A0B0)`

((A1B1)À1 +(A1B1)`B1)` (A2B2)À2 + (A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)`

((A1B1)`B1(A2B2)À2 + (A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)`) ((A3B3)À3 + (A3B3)`B3)`

(A2B2)`B2)`.

(A=B) = (A3B3)À3 + (A3B3)`B3)` (A2B2)À2 + (A2B2)`B2)` ((A1B1)À1 +(A1B1)`B1)`

((A0B0)À0 + (A0B0)`B0)` (CIAEQB).

CIAGB = Cascading Input A Greater than B

CIAEQB = Cascading Input A Equal to B

CIALB = Cascading Input A Less than B

VHDL CODE:

library IEEE;


entity bit4 is

port (

a0: in STD_LOGIC;

a1: in STD_LOGIC;

a2: in STD_LOGIC;

a3: in STD_LOGIC;

cg: in STD_LOGIC; contd…

b0: in STD_LOGIC;

b1: in STD_LOGIC;

ECADLAB(VHDL) 131

b2: in STD_LOGIC;

b3: in STD_LOGIC;

ce: in STD_LOGIC;

cl: in STD_LOGIC;

agb: out STD_LOGIC;

aeb: out STD_LOGIC;

alb: out STD_LOGIC);

end bit4;

architecture bit4 of bit4 is

begin

process(a0,a1,a2,a3,b0,b1,b2,b3,cg,ce,cl)

begin if a3>b3 then agb<='1'; alb<='0';aeb<='0';

elsif a3<b3 then agb<='0'; alb<='1';aeb<='0';

else if a2>b2 then agb<='1'; alb<='0';aeb<='0';

elsif a2<b2 then agb<='0'; alb<='1';aeb<='0';

elsif a1>b1 then agb<='1';alb<='0';aeb<='0';

elsif a1<b1 then agb<='0';alb<='1';aeb<='0';

else if a0>b0 then agb<='1';alb<='0';aeb<='0';

elsif a0<b0 then agb<='0';alb<='1';aeb<='0';

else if(cg='1' and ce='0' and cl='0')then agb<='1';alb<='0';aeb<='0';

elsif(cg='0' and ce='1' and cl='0')then agb<='0';alb<='0';aeb<='1';


elsif(ce='1')then agb<='0';alb<='0';aeb<='1';



end if;

end if;

end if;

end if;

end if;

end process;

end bit4;

ECADLAB(VHDL) 132



INPUTS

OUTPUTS

A3>B3 A2>B2 A1>B1 AO>BO A>B AB AB3 X X X X X X X X X 5V 0V 0V

A3<B3 X X X X

X X X X X 0V 5V 0V

A3=B3 A2>B2 X X X X X X X 5V 0V 0V

A3=B3 A2<B2 X X X X X X X 0V 5V 0V

A3=B3 A2=B2 A1>B1 X X X X X 5V 0V 0V

A3=B3 A2=B2 A1<B1 X X X X X 0V 5V 0V


X

X 5V 0V 0V

A3=B3

A2=B2

A1=B1

AO<BO X

X

X 0V 5V 0V

A3=B3

A2=B2 A1=B1 AO=BO 1 0 0 5V 0V 0V

A3=B3 A2=B2 A1=B1 AO=BO 0 1 0 0V 5V 0V

A3=B3 A2=B2

A1=B1

AO=BO 0 0 1 0V 0V 5V

A3=B3

A2=B2

A1=B1

AO=BO

1 1 0 0V

0V

0V

A3=B3 A2=B2 A1=B1 AO=BO 0 0 0 5V 5V 0V


Agb should be HIGH when data A is Greater than data B

Alb should be HIGH when data A is less than data B

Aeb should be HIGH when data A is Equal data B


ECADLAB(VHDL) 133

Fig: Compilation Report of 4 bit Comparator

ECADLAB(VHDL) 134

RESULTS (HARDWARE):


INPUTS

OUTPUTS

A3>B3 A2>B2 A1>B1 AO>BO A>B AB

LED

AB3 X X X X X X X X X ON OFF OFF

A3<B3 X X X X

X X X X X OFF ON OFF

A3=B3 A2>B2 X X X X X X X ON OFF OFF

A3=B3 A2<B2 X X X X X X X OFF ON OFF

A3=B3 A2=B2 A1>B1 X X X X X ON OFF OFF

A3=B3 A2=B2 A1<B1 X X X X X OFF ON OFF


X

X ON OFF OFF

A3=B3

A2=B2

A1=B1

AO<BO X

X

X OFF ON OFF

A3=B3

A2=B2 A1=B1 AO=BO 1 0 0 ON OFF OFF

A3=B3 A2=B2 A1=B1 AO=BO 0 1 0 OFF ON OFF

A3=B3 A2=B2

A1=B1

AO=BO 0 0 1 OFF OFF ON

A3=B3

A2=B2

A1=B1

AO=BO

1 1 0 OFF

OFF

OFF

A3=B3 A2=B2 A1=B1 AO=BO 0 0 0 ON ON OFF


ECADLAB(VHDL) 135

RESULTS (SOFTWARE):

Fig: Simulation Report of 4 bit Comparator


ECADLAB(VHDL) 136

Fig: Simulation Results of 4 bit Comparator


ECADLAB(VHDL) 137

RESULT:

Four bit Comparator internal structure is Simulated and verified using Active-HDL


INFERENCE:


and Hardware.




the code.




Sheets.





1) Explain concept of magnitude comparator.

Ans: It is a special type of combinational circuit designed primarily to compare the

relative magnitude of two binary numbers.

2) What is the main feature of IC 7485?

Ans: IC 7485 is a four- bit comparator used to compare two four-bit binary inputs.


ECADLAB(VHDL) 138

3) Draw the block diagram for magnitude comparator.

Ans:



using.


the code.






ECADLAB(VHDL) 139

EXPERIMENT NO.9: 8X1 MULTIPLEXER

AIM: To Simulate internal structure of 8X1 MULTIPLEXER (IC 74151) using VHDL and

verify its operation.

APPARATUS:


1. IC 74151 1



THEORY:

74LS51 is a logical implementation of a single-pole, 8-position switch with Switch

position controlled by the state of three select inputs S0,S1,S2.

- Multi function capability.

- Complementary outputs.


ECADLAB(VHDL) 140

DETAILS:

TRUTH TABLE:

INPUT OUTPUT

SELECT STROBE

C B A S

W Y

X X X H H L

L L L L DO’ DO

L L H L D1΄ D1

L H L L D2΄ D2

L H H L D3΄ D3

H L L L D4΄ D4

H L H L D5΄ D5

H H L L D6΄ D6

H H H L D7΄ D7

INTERNAL DIAGRAM:

ECADLAB(VHDL) 141

OUTPUT EQUATIONS:

D0 = A`B`C` D1 = AB`C` D2 = A`BC` D3 = ABC` D4 = A`B`C

D5 = AB`C D6 = A`BC D7 = ABC

VHDL CODE:

File: mux8by1

library IEEE;


entity mux is

port ( a: in STD_LOGIC; b: in STD_LOGIC;

c: in STD_LOGIC;

d: in STD_LOGIC_VECTOR(7 down to 0); en: in STD_LOGIC;

y: out STD_LOGIC );

end mux;

Architecture mux of mux is

begin

process (a, b,c,d)

begin

if(en='0')then

if(a='0' and b='0' and c='0')then y<=d(0);

elsif(a='0' and b='0' and c='0')then y<=d(0);








end if;

else y<='X';

end if;

end process;

end mux;


ECADLAB(VHDL) 142



a='0' and b='0' and c='0' y=d(0);

a='0' and b='0' and c='1' y=d(1);

a='0' and b='1' and c='0' y=d(2);

a='0' and b='1' and c='1' y=d(3);

a='1' and b='0' and c='0' y=d(4);

a='1' and b='0' and c='1' y=d(5);

a='1' and b='1' and c='0' y=d(6);

a='1' and b='1' and c='1' y=d(7);

INPUT OUTPUT

SELECT STROBE

C B A S

W Y

X X X 1 1 0

0 0 0 0 A+B+C A`B`C`

0 0 1 0 A`+B+C AB`C`

0 1 0 0 A+B`+C A`BC`

0 1 1 0 A`+B`+C ABC`

1 0 0 0 A+B+C` A`B`C

1 0 1 0 A`+B+C` AB`C

1 1 0 0 A+B`+C` A`BC

1 1 1 0 A`+B`+C` ABC


ECADLAB(VHDL) 143

Fig: Compilation Report of 8X1 MULTIPLEXER


ECADLAB(VHDL) 144

RESULTS (HARDWARE):

INPUT OUTPUT

SELECT STROBE

C B A S

W Y

X X X 1 1 0

0 0 0 0 A+B+C A`B`C`

0 0 1 0 A`+B+C AB`C`

0 1 0 0 A+B`+C A`BC`

0 1 1 0 A`+B`+C ABC`

1 0 0 0 A+B+C` A`B`C

1 0 1 0 A`+B+C` AB`C

1 1 0 0 A+B`+C` A`BC

1 1 1 0 A`+B`+C` ABC


ECADLAB(VHDL) 145

RESULTS (SOFTWARE):

Fig: Simulation Report of 8X1 MULTIPLEXER


ECADLAB(VHDL) 146

Fig: Simulation Results of 8X1 MULTIPLEXER


ECADLAB(VHDL) 147

RESULT:

8X1 MULTIPLEXER internal structure is simulated and verified using Active-HDL


INFERENCE:


and Hardware.


1)Follow Getting Started Procedure for the Software you are using.

2)Don’t forget to instantiate IEEE Libraries at the starting of

the code.

3)Follow Syntax and Semantics of the VHDL code throughout.







1) What is the main feature of IC 74LS151?

Ans: It is an 8x1 Multiplexer having eight inputs and provides two outputs, one is

active high and other one is active low.


ECADLAB(VHDL) 148

2) Give the functional table for Quadruple 2-to-1 line multiplexer.

Ans:

ENABLE SELECT OUTPUT

1 X 0

0 0 Select input A

0 1 Select input B

3) What is principle of operation of a multiplexer?

Ans: Multiplexer is a digital switch which allows digital information from several

sources to be routed onto a single output line.

4) Differentiate between decoder and multiplexer.

Ans: Decoder: n inputs produce 2n possible outputs, 2n output values are from 0

through 2n-1.

Multiplexer: There are 2n input lines and n select lines whose bit combinations

determine which input is selected.

5. Applications of multiplexers? Ans: The multiplexer include data selection and routing, operation sequencing, parallel to serial conversion, wave form generation and logic function generation. 6. Applications of demultiplexers? Ans: The demultiplexer include serial to parallel conversion, logic function generation, operation sequencing.



using.


the code.






ECADLAB(VHDL) 149

EXPERIMENT NO.10: 2X4 DEMULTIPLEXER

AIM: To Simulate internal structure of 2X4 DEMULTIPLEXER (IC 74155) using VHDL

and Verify its operation.

APPARATUS:


1. IC 74155 1



THEORY:

The LS155 and LS156 are Dual 1-of-4 Decoder/Demultiplexers with common Address

inputs and separate gated Enable inputs. When enabled, each decoder section accepts

the binary weighted Address inputs (A0, A1) and provides four mutually exclusive active

LOW outputs (O0–O3). If the Enable requirements of each decoder are not met, all

outputs of that decoder are HIGH.

Each decoder section has a 2-input enable gate. The enable gate for Decoder “a”

requires one active HIGH input and one active LOW input (Ea•Ea). In demultiplexing

applications, Decoder “a” can accept either true or complemented data by using the Ea

or Ea inputs respectively. The enable gate for Decoder “b” requires two active LOW

inputs (Eb•Eb). The LS155 or LS156 can be used as a 1-of-8 Decoder/Demultiplexer by

tying Ea to Eb and relabeling the common connection

as (A2). The other Eb and Ea are connected together to form the common enable.The

LS155 and LS156 can be used to generate all four minterms of two variables. These

four minterms are useful in some applications replacing multiple gate functions.


ECADLAB(VHDL) 150

2X4 DEMULTIPLEXER DETAILS:

TRUTH TABLE:

ADDRESS ENABLE a OUTPUT a ENABLE b OUTPUT b

A0 A1 Ea Ea` O0` O1` O2` O3` Eb` Eb` O0` O1` O2` O3`

X X L X H H H H H X H H H H

X X X H H H H H X H H H H H

L L H L L H H H L L L H H H

H L H L H L H H L L H L H H

L H H L H H L H L L H H L H

H H H L H H H L L L H H H L

INTERNAL DIAGRAM:

OUTPUT EQUATIONS:

ECADLAB(VHDL) 151

VHDL CODE:

library ieee;

use ieee.std_logic_1164.all;

entity TryDeMUX is

port( X: in std_logic;

sel: in std_logic_vector (1 downto 0);

A: out std_logic;

B: out std_logic;

C: out std_logic;

D: out std_logic);

end TryDeMUX;

architecture behaviour of TryDeMUX is

begin

process(sel,X)

begin

case sel is

when "00"=>

A <=X; B <= '0'; C <= '0'; D <= '0';

when "01" =>

B <=X; A <='0'; C <='0'; D <='0';

when "10" =>

C <=X; A <='0'; B <='0'; D <='0';

when others =>

D <=X; A <='0'; B <= '0'; C <='0';

end case;

end process;

end behaviour;

ECADLAB(VHDL) 152


ADDRESS ENABLE a OUTPUT a ENABLE b OUTPUT b


X X 0 X 5V 5V 5V 5V 1 X 5V 5V 5V 5V

X X X 1 5V 5V 5V 5V X 1 5V 5V 5V 5V

0 0 1 0 0V 5V 5V 5V 0 0 0V 5V 5V 5V

1 0 1 0 5V 0V 5V 5V 0 0 5V 0V 5V 5V

0 1 1 0 5V 5V 0V 5V 0 0 5V 5V 0V 5V

1 1 1 0 5V 5V 5V 0V 0 0 5V 5V 5V 0V


When SELECT = 00

A =1; B = '0'; C = '0'; D = '0';

When SELECT = 01

B =1; A ='0'; C ='0'; D ='0';

when SELECT =10

C <=1; A = 0; B = 0; D = 0;

When SELECT = 11

D =1; A = 0; B = 0; C = 0;


ECADLAB(VHDL) 153

Fig: Compilation Report of 2X4 DEMULTIPLEXER


ECADLAB(VHDL) 154

RESULTS (HARDWARE):

ADDRESS ENABLE

a

OUTPUT a ENABLE

b

OUTPUT b


X X 0 X ON ON ON ON 1 X ON ON ON ON

X X X 1 ON ON ON ON X 1 ON ON ON ON

0 0 1 0 OFF ON ON ON 0 0 OFF ON ON ON

1 0 1 0 ON OFF ON ON 0 0 ON OFF ON ON

0 1 1 0 ON ON OFF ON 0 0 ON ON OFF ON

1 1 1 0 ON ON ON OFF 0 0 ON ON ON OFF


ECADLAB(VHDL) 155

RESULTS (SOFTWARE):

Fig: Simulation Report of 2X4 DEMULTIPLEXER


ECADLAB(VHDL) 156

Fig: Simulation Results of 2X4 DEMULTIPLEXER


ECADLAB(VHDL) 157

RESULT:

2X4 DEMULTIPLEXER internal structure is simulated and verified using Active-HDL


INFERENCE:


and Hardware.



2) Don’t forget to instantiate IEEE Libraries At the starting of

the code.




Sheets.





1) Explain the concept of Demultiplexer.

Ans: A Demultiplexer is a circuit that receives information on a single line and transmits

this information on one of 2n possible output lines. The selection of specific output line is

controlled by values of n selection lines.


ECADLAB(VHDL) 158

2. Differentiate Decoder and Demultiplexer.

Ans: Decoder: n inputs produce 2n possible outputs, 2n output values are from 0

through 2n-1.

Demultiplexer: A Demultiplexer is a circuit that receives information on a single line and

transmits this information on one of 2n possible output lines.

3. Draw the block diagram for full subtractor using 1:8 Demultiplexer

Ans:


1. Follow Getting Started Procedure for the Software you are

using.


the code.




3) Supply the inputs according to truth table and verify outputs


ECADLAB(VHDL) 159

EXPERIMENT NO.11: 16X1 MULTIPLEXER

AIM: To Simulate Internal structure of 16X1 MULTIPLEXER (IC 74150) using VHDL


APPARATUS:


1. IC 74150 1



THEORY:

These data selectors/multiplexers contain full on-chip decoding to select the desired

data source. The 74150 selects one-of-sixteen data sources; the 74151A selects one-of-

eight data sources. The 74150 and 74151A have a strobe input which must be at a low

logic level to enable these devices. A high level at the strobe forces the W output high

and the Y output (as applicable) low. The 74151A features complementary W and Y

outputs, whereas the 74150 has an inverted (W) output only. The 74151A incorporates

address buffers which have symmetrical propagation delay times through the

complementary paths. This reduces the possibility of transients occurring at the output(s)

due to changes made at the select inputs, even when the 74151A outputs are enabled

(i.e., strobe low). 74LS150 selects one-of-sixteen data lines. Performs parallel-to-serial

conversion. Permits multiplexing from N lines to one line. Also for use as Boolean

function generator.


ECADLAB(VHDL) 160

DETAILS:

TRUTH TABLE:

INPUTS

SELECT STROBE

OUTPUT

D C B A S W

X X X X H H

L L L L L Eo`

L L L H L E1`

L L H L L E2`

L L H H L E3`

L H L L L E4`

L H L H L E5`

L H H L L E6`

L H H H L E7`

H L L L L E8`

H L L H L E9`

H L H L L E10`

H L H H L E11`

H H L L L E12`

H H L H L E13`

H H H L L E14`

H H H H L E15`

H = High Level; L = low Level; X = Don’t Care; E 0’ , E1’ , … E15’ = The Complement of

the level of the respective E input.


ECADLAB(VHDL) 161

INTERNAL DIAGRAM:

ECADLAB(VHDL) 162

16X1 MULTIPLEXER OUTPUT EQUATIONS:

Eo`= ABCD E1`= A`BCD E2`= AB`CD E3`= A`B`CD E4`= ABC`D

E5`= A`BC`D E6`= AB`C`D E7`= A`B`C`D E8`= ABCD` E9`=A`BCD`

E10`= AB`CD` E11`=A`B`CD` E12`= ABC`D` E13`= A`BC`D`E14`= AB`C`D`

E15`= A`B`C`D`

VHDL CODE:

library IEEE;


entity mux16 is

port (

l: in STD_LOGIC_VECTOR (0 to 15);

a: in STD_LOGIC;

b: in STD_LOGIC;

d: in STD_LOGIC;

s: in STD_LOGIC;

c: in STD_LOGIC;

wl: out STD_LOGIC);

end mux16;

architecture mux16 of mux16 is

signal p:std_logic_vector(3 downto 0):="0000";

begin

p(0)<=a;

p(1)<=b;

p(2)<=c;

p(3)<=d;

process (p, s)

begin

if s='1' then wl<='1';

else

case p is contd…

ECADLAB(VHDL) 163

when "0000"=>wl<=not l(0); when "0001"=>wl<=not l(1);



when "0110"=>wl<=not l(6);

when "0111"=>wl<=not l(7);

when "1000"=>wl<=not l(8);

when "1001"=>wl<=not l(9);

when "1010"=>wl<=not l(10);

when "1011"=>wl<=not l(11);

when "1100"=>wl<=not l(12);

when "1101"=>wl<=not l(13);

when "1110"=>wl<=not l(14);

when "1111"=>wl<=not l(15);

when others=>wl<='1';

end case;

end if;

end process;

end mux16;

ECADLAB(VHDL) 164


INPUTS

SELECT STROBE

OUTPUT

D C B A S W

X X X X 5V 5V

0 0 0 0 0V ABCD

0 0 0 1 0V A`BCD

0 0 1 0 0V AB`CD

0 0 1 1 0V A`B`CD

0 1 0 0 0V ABC`D

0 1 0 1 0V A`BC`D

0 1 1 0 0V AB`C`D

0 1 1 1 0V A`B`C`D

1 0 0 0 0V ABCD`

1 0 0 1 0V A`BCD`

1 0 1 0 0V AB`CD`

1 0 1 1 0V A`B`CD`

1 1 0 0 0V ABC`D`

1 1 0 1 0V A`BC`D`

1 1 1 0 0V AB`C`D`

1 1 1 1 0V A`B`C`D`


if s='1' then wl<='1';

if s=0 the output wl should be the complement of the corresponding input logic

vector l(n) where n = 0123456789… when ABCD = “0000", “0001”, “0010”, and so on till

“1111”. when others wl ='1';


ECADLAB(VHDL) 165

Fig: Compilation Report of 16X1 MULTIPLEXER


ECADLAB(VHDL) 166

RESULTS (HARDWARE):

INPUTS

SELECT STROBE

OUTPUT

D C B A S W LED

X X X X 1 ON

0 0 0 0 0 ON when ABCD=1

0 0 0 1 0 ON when A`BCD=1

0 0 1 0 0 ON when AB`CD=1

0 0 1 1 0 ON when A`B`CD=1

0 1 0 0 0 ON when ABC`D=1

0 1 0 1 0 ON when A`BC`D=1

0 1 1 0 0 ON when AB`C`D=1

0 1 1 1 0 ONwhen A`B`C`D=1

1 0 0 0 0 ON when ABCD`=1

1 0 0 1 0 ON when A`BCD`=1

1 0 1 0 0 ON when AB`CD`=1

1 0 1 1 0 ONwhen A`B`CD`=1

1 1 0 0 0 ON when ABC`D`=1

1 1 0 1 0 ONwhen A`BC`D`=1

1 1 1 0 0 ONwhen AB`C`D`=1

1 1 1 1 0 ONwhenA`B`C`D`=1


ECADLAB(VHDL) 167

RESULTS (SOFTWARE):

Fig: Simulation Report of 16X1 MULTIPLEXER


ECADLAB(VHDL) 168

Fig: Simulation Results of 16X1 MULTIPLEXER


ECADLAB(VHDL) 169

RESULT:

16X1 MULTIPLEXER internal structure is simulated and verified using Active-HDL


INFERENCE:


and Hardware.




the code.



1) Apply the voltages to the IC as per the details given in the data sheets.

2. Apply the inputs to the respective pins.




ECADLAB(VHDL) 170


1. Implement 16-to-1 line Multiplexer using 4-to-1 line multiplexers?

Ans:

Fig: 16-to-1 MUX using 4-to-1 mux


ECADLAB(VHDL) 171

2.) Implement 16-to-1 line Multiplexer using 8-to-1 line multiplexers?

Ans:

Fig: 16-to-1 MUX using 8-to-1 mux



using.


the code.






ECADLAB(VHDL) 172

EXPERIMENT NO.12: 4X16 DEMULTIPLEXER

AIM: To Simulate Internal structure of 4X16 DEMULTIPLEXER (IC 74154) using VHDL


APPARATUS:


1. IC 74154 1



THEORY:

The 74154 is a TTL monolithic, 4- line-to-16-line decoder which allows decoding of a 4

bit binary coded input into one of 16 mutually exclusive outputs. The devices provided

with two strobe lines, both of which have to be in the low state in order to perform the

decoding function ;if either of the strobes is high ,all 16 outputs will remain high. The

device can be used as a demultiplexer by passing information from one of the strobes

(the other being low ) to an output selected by the 4 line input address. These

demultiplexers are ideally suited for implementing high performance memory decoders.


ECADLAB(VHDL) 173

TRUTH TABLE:

INPUTS OUTPUTS

G1 G2 D C B A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

L L L L L L H L L L L L L L L L L L L L L L

L L L L L H L H L L L L L L L L L L L L L L

L L L L H L L L H L L L L L L L L L L L L L

L L L L H H L L L H L L L L L L L L L L L L

L L L H L L L L L L H L L L L L L L L L L L

L L L H L H L L L L L H L L L L L L L L L L

L L L H H L L L L L L L H L L L L L L L L L

L L L H H H L L L L L L L H L L L L L L L L

L L H L L L L L L L L L L L H L L L L L L L

L L H L L H L L L L L L L L L H L L L L L L

L L H L H L L L L L L L L L L L H L L L L L

L L H L H H L L L L L L L L L L L H L L L L

L L H H L L L L L L L L L L L L L L H L L L

L L H H L H L L L L L L L L L L L L L H L L

L L H H H L L L L L L L L L L L L L L L H L

L L H H H H L L L L L L L L L L L L L L L H

L H X X X X L L L L L L L L L L L L L L L L

H L X X X X L L L L L L L L L L L L L L L L

H H X X X X L L L L L L L L L L L L L L L L


ECADLAB(VHDL) 174

INTERNAL DIAGRAM:

4x16 DEMULTIPLEXER OUTPUT EQUATIONS:

O0 = A` B`C`D` ; O1 = AB`C`D`; O2 = A`BC`D`; O3 = ABC`D`; O4 = A`B`CD`

O5 = AB`CD`; O6 = A`BCD`; O7 = ABCD`; O8 = A`B`C`D; O9 = AB`C`D

O10 = A`BC`D; O11 = ABC`D; O12 = A`B`CD; O13 = AB`CD; O14 = A`BCD

O15 = ABCD;

ECADLAB(VHDL) 175

VHDL CODE:

library ieee;


entity TryDeMUX is

port( X: in std_logic;

sel: in std_logic_vector (3 downto 0);

A: out std_logic; B: out std_logic; C: out std_logic; D: out std_logic;

E: out std_logic; F: out std_logic; G: out std_logic; H: out std_logic;

I: out std_logic; J: out std_logic; K: out std_logic; L: out std_logic;

M: out std_logic; N: out std_logic; O: out std_logic; P: out std_logic);

end TryDeMUX;

architecture behaviour of TryDeMUX is

begin

process(sel,X)

begin

case sel is

when "0000"=>

A <=X; B <='0'; C <= '0'; D <= '0'; E <= '0'; F <= '0'; G <= '0';H <= '0'; I <= '0'; J <= '0'; K

<= '0';L <= '0'; M <= '0'; N <= '0';O <= '0';P <= '0';

when "0001"=>

A <='0'; B <=X;C <= '0'; D <= '0'; E <= '0'; F <= '0'; G <= '0';H <= '0'; I <= '0'; J <= '0';K <=

'0'; L <= '0'; M <= '0';N <= '0'; O <= '0'; P <= '0';

when "0010"=>

A <='0'; B <='0'; C <= X; D <= '0'; E <= '0'; F <= '0'; G <= '0';H <= '0'; I <= '0'; J <= '0'; K

<= '0'; L <= '0'; M <= '0';N <= '0'; O <= '0'; P <= '0';

when "0011" =>

A <='0'; B <='0'; C <= '0'; D <= X; E <= '0'; F <= '0'; G <= '0';H <= '0'; I <= '0'; J <= '0'; K

<= '0'; L <= '0'; M <= '0';N <= '0'; O <= '0'; P <= '0';

when "0100" =>

A <='0'; B <='0'; C <= '0'; D <= '0'; E <= X; F <= '0'; G <= '0';H <= '0'; I <= '0'; J <= '0'; K

<= '0'; L <= '0'; M <= '0';N <= '0'; O <= '0'; P <= '0';

when "0101" =>

A <='0'; B <='0'; C <= '0'; D <= '0'; E <= '0'; F <= X; G <= '0';H <= '0'; I <= '0'; J <= '0'; K

<= '0'; L <= '0'; M <= '0';N <= '0'; O <= '0'; P <= '0'; contd…

ECADLAB(VHDL) 176

when "0110" =>

A <='0'; B <='0'; C <= '0'; D <= '0'; E <= '0'; F <= '0'; G <= X;H <= '0'; I <= '0'; J <= '0'; K

<= '0'; L <= '0'; M <= '0';N <= '0'; O <= '0'; P <= '0';

when "0111" =>

A <='0'; B <='0'; C <= '0'; D <= '0'; E <= '0'; F <= '0'; G <= '0';H <= X; I <= '0'; J <= '0'; K

<= '0'; L <= '0'; M <= '0';N <= '0'; O <= '0'; P <= '0';

when "1000" =>

A <='0'; B <='0'; C <= '0'; D <= '0'; E <= '0'; F <= '0'; G <= '0';H <= '0'; I <= X; J <= '0'; K

<= '0'; L <= '0'; M <= '0';N <= '0'; O <= '0'; P <= '0';

when "1001" =>

A <='0'; B <='0'; C <= '0'; D <= '0'; E <= '0'; F <= '0'; G <= '0';H <= '0'; I <= '0'; J <= X; K

<= '0'; L <= '0'; M <= '0';N <= '0'; O <= '0'; P <= '0';

when "1010" =>

A <='0'; B <='0'; C <= '0'; D <= '0'; E <= '0'; F <= '0'; G <= '0';H <= '0'; I <= '0'; J <= '0'; K

<= X; L <= '0'; M <= '0';N <= '0'; O <= '0'; P <= '0';

when "1011" =>

A <='0'; B <='0'; C <= '0'; D <= '0'; E <= '0'; F <= '0'; G <= '0';H <= '0'; I <= '0'; J <= '0'; K

<= '0'; L <= X; M <= '0';N <= '0'; O <= '0'; P <= '0';

when "1100" =>

A <='0'; B <='0'; C <= '0'; D <= '0'; E <= '0'; F <= '0'; G <= '0';H <= '0'; I <= '0'; J <= '0';K

<= '0'; L <= '0'; M <= X;N <= '0'; O <= '0'; P <= '0';

when "1101" =>

A <='0'; B <='0'; C <= '0'; D <= '0'; E <= '0'; F <= '0'; G <= '0';H <= '0'; I <= '0'; J <= '0'; K

<= '0'; L <= '0'; M <= '0';N <= X; O <= '0'; P <= '0';

when "1110" =>

A <='0'; B <='0'; C <= '0'; D <= '0'; E <= '0'; F <= '0'; G <= '0';H <= '0'; I <= '0'; J <= '0'; K

<= '0'; L <= '0'; M <= '0';N <= '0'; O <= X; P <= '0';

when others =>

A <='0'; B <='0'; C <= '0'; D <= '0'; E <= '0'; F <= '0'; G <= '0';H <= '0'; I <= '0'; J <= '0'; K

<= '0';L <= '0'; M <= '0';N <= '0'; O <= '0'; P <= X;

end case;

end process;

end behaviour;


ECADLAB(VHDL) 177

EXPECTED RESULTS(HARDWARE):

INPUTS OUTPUTS

G1 G2 D C B A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

0 1 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 0 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


when sel = “1111” then all outputs will be low otherwise respective outputs will be high

depending on the address given on input lines.


ECADLAB(VHDL) 178

Fig: Compilation Report of 4X16 DEMULTIPLEXER


ECADLAB(VHDL) 179

RESULTS (HARDWARE):

INPUTS OUTPUTS

G1 G2 D C B A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

0 1 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 0 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


ECADLAB(VHDL) 180

RESULTS (SOFTWARE):

Fig: Simulation Report of 4X16 DEMULTIPLEXER


ECADLAB(VHDL) 181

Fig: Simulation Results of 4X16 DEMULTIPLEXER


ECADLAB(VHDL) 182

RESULT:

4X16 DEMULTIPLEXER internal structure is simulated and verified using Active

HDL Software and in Hardware Lab Respectively.

INFERENCE:


and Hardware.











1) How many 2X4 Demultiplexers are needed to implement 4X16 Demultiplexer?

Ans: Four 2X4 Demultiplexers are needed to implement 4X16 Demultiplexer.

2) Mention one important application of Demultiplexer.

Ans: These demultiplexers are ideally suited for implementing high performance memory

decoders.

3) How do you get the decoding function from a Demultiplexer?

Ans: The devices provided with two strobe lines, both of which have to be in the low

state in order to perform the decoding function


ECADLAB(VHDL) 183

4) Implement 1x16 demultiplexer using 1x4 demultiplexer ?

Ans:


ECADLAB(VHDL) 184



2) Don’t forget to instantiate IEEE Libraries at the starting of sthe code.






ECADLAB(VHDL) 185

EXPERIMENT NO.13: RAM (16x4)

AIM: To Simulate Internal structure of 16X4 RAM(IC 74189) using VHDL and


APPARATUS:


1. IC 74189 1



THEORY:

The CY7C189 and CY7C190 are extremely high performance 64-bit static RAM’s

organized as 16 words by 4 bits. Easy memory expansion n is provided by an active low

chip select (CS) input and three- state outputs. The devices are provided with inverting

(CY7C189) and non inverting (CY7C190) outputs. Writing to the device is accomplished

when the chip select (CS) and write enable (WE) inputs are both low. Data on the four

data inputs (D0 through D3) is written into the memory location specified on the address

pins(A0 through A3). The outputs are preconditioned such that the correct data is present

at the data outputs (O0 through O3) when the write cycle is complete. This precondition

operation insures minimum write recovery times by eliminating the “write recovery

glitch.” Reading the device is accomplished by taking chip select (CS) LOW, while write

enable(WE) remains HIGH. Under these conditions, the contents of the memory location

specified on the address pins will appear on the four output pins (O0 through O3) in

inverted (CY7C189) or non-inverted (CY7C190) format. The four output pins remain in

high-impedance state when chip select (CS) is HIGH or write enable (WE) is LOW.


ECADLAB(VHDL) 186

16x4 RAM DETAILS:

TRUTH TABLE:

INPUT

CS΄

WE΄

OPERATION CONDITION

OF OUTPUT

L L WRITE HIGH

IMPEDENCE

L H READ COMPLEMENT

OF STORED

DATA

H X INHIBIT HIGH

IMPENDENCE


ECADLAB(VHDL) 187

INTERNAL DIAGRAM:

RAM OUTPUT EQUATIONS:

Write = CS`WE`

READ = CS`WE

INHIBIT = CS WE

ECADLAB(VHDL) 188

VHDL CODE:

library IEEE;


entity ram is

port (

cs: in STD_LOGIC;

we: in STD_LOGIC;

re: in STD_LOGIC;

mr: out STD_LOGIC;

mw: out STD_LOGIC

);

end ram;

architecture ram of ram is

begin

process (cs,we,re)

begin

if (cs='0'and we='1'and re='0')then

mr<='0';

mw<='1';

elsif (cs='0'and we='0'and re='1')then

mr<='1';

mw<='0';

end if;

end process;

end ram;


ECADLAB(VHDL) 189


INPUT

CS΄

WE΄

OPERATION CONDITION OF

OUTPUT

0v

0v

Data is written

Into specified

location

Tristate

0v +5v Data is read

from specified

location

COMPLEMENT OF

STORED DATA

+5v X No write or read Tristate

X = don’t care


cs ='0'and we ='1'and re ='0'

memory read ='0'

memory write = '1'

cs ='0'and we='0'and re='1'

memory read ='1'

memory write = '0'


ECADLAB(VHDL) 190

Fig: Compilation Report of RAM (16x4)


ECADLAB(VHDL) 191

RESULTS (HARDWARE):

X = don’t care

INPUT

CS΄

WE΄

OPERATION CONDITION

OF OUTPUT

0v 0v Data is available

In specified

location

Tristate

0v +5v Data is retrieved

from specified

location

Complement Of

stored data is

available

+5v X INHIBIT Tristate


ECADLAB(VHDL) 192

RESULTS (SOFTWARE):

Fig: Simulation Report of RAM (16x4)


ECADLAB(VHDL) 193

Fig: Simulation Results of RAM (16x4)


ECADLAB(VHDL) 194

RESULT:

16X4 RAM internal structure is simulated and verified using Active-HDL Software

and in Hardware Lab Respectively.

INFERENCE:


and Hardware.






1)Apply the voltages to the IC as per the details given in the data sheets.

2)Apply the inputs to the respective pins.

3)First decide which one is MSB and LSB.

4)Take the outputs at appropriate pins.


1) Differentiate between combinational circuit and sequential circuit

Ans: Combinational circuit: In this memory unit is not required. Parallel adder is one

example of combinational circuit.

Sequential circuit: Memory unit is required to store the past history of input variables.

Serial adder is one the example for sequential circuit.

2) Differentiate between Moore and Mealy Machines.

Ans: Moore Machine: its output is a function of present state only Input changes does

not affect the output.

Mealy Machine: its output is a function of present state as well as present output.

Input changes may affect the output.


ECADLAB(VHDL) 195

3) How memory cells are organized in a RAM?

Ans: Memory cell organized in the form of array, in which each cell is capable of

storing one bit information

4) Differentiate between Static and Dynamic RAM.

Ans: Static RAM: Memories that consists of circuits capable of retaining their

state as long as power is applied are known as static memories. These are Random

Access Memories, hence combinely called Static RAM.

Dynamic RAM: Memories that store data as a charge on the capacitor are

called as Dynamic RAM’s.

5) Implement 256x2 Ram using 256x1 RAM?

Ans:


ECADLAB(VHDL) 196

6) Implement 32x4 RAM using 16x4 RAM?

Ans:


ECADLAB(VHDL) 197

7) Implement 256x2 Ram using 256x1 RAM?

Ans:









ECADLAB(VHDL) 198

APPENDIX-A


ECADLAB(VHDL) 199


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ECADLAB(VHDL) 262

APPENDIX-B

VHDL PROGRAMMING CONCEPTS

Tools

VHDL descriptions of hardware design and test benches are portable between design tools, and portable between design centres and project partners. You can safely invest in VHDL modelling effort and training, knowing that you will not be tied in to a single tool vendor, but will be free to preserve your investment across tools and platforms. Also, the design automation tool vendors are themselves making a large investment in VHDL, ensuring a continuing supply of state-of-the-art VHDL tools.

Technology

VHDL permits technology independent design through support for top down design and logic synthesis. To move a design to a new technology you need not start from scratch or reverse-engineer a specification - instead you go back up the design tree to a behavioural VHDL description, then implement that in the new technology knowing that the correct functionality will be preserved.

Benefits Executable specification Validate spec in system context (Subcontract) Functionality separated from implementation Simulate early and fast (Manage complexity) Explore design alternatives Get feedback (Produce better designs) Automatic synthesis and test generation (ATPG for ASICs) Increase productivity (Shorten time-to-market) Technology and tool independence (though FPGA features may be unexploited) Portable design data (Protect investment)

An Example Design Entity

A design is described in VHDL using the concept of a design entity. A design entity is split into two parts, each of which is called a design unit in VHDL jargon. The entity declaration represents the external interface to the design entity. The architecture body represents the internal description of the design entity - its behaviour, its structure, or a mixture of both. Let's imagine we want to describe an and-or-invert (AOI) gate in VHDL. If we consider the AOI gate as a single chip package, it will have four input pins and one output pin; we need not concern ourselves with power and ground pins in modelling our AOI design.

ECADLAB(VHDL) 263

VHDL: an AOI gate design entity

VHDL code for AND-OR-INVERT gate

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity AOI is

port (

A, B, C, D: in STD_LOGIC;

F : out STD_LOGIC

);

end AOI;

architecture V1 of AOI is

begin

F <= not ((A and B) or (C and D));

end V1;

OK, that's the code. Let's dissect it line by line...

-- VHDL code for AND-OR-INVERT gate.

Similar to many programming languages, VHDL supports comments. Comments are not part of the VHDL design, but allow the user to make notes referring to the VHDL code, usually as an aid to understanding it. Here the comment is a “header” that tells us that the VHDL describes an AOI gate. It is no more than an aide de memoire in this case. A VHDL compiler will ignore this line of VHDL. Two hyphens mark the start of a comment, which is ignored by the VHDL compiler. A comment can be on a separate line or at the end of a line of VHDL code, but in any case stops at the end of the line.

library IEEE;


Above the entity declaration is a library clause (library IEEE;) and a use clause (use IEEE.STD_LOGIC_1164.all;). This gives the entity AOI access to all the names declared within package STD_LOGIC_1164 in the library IEEE, and to data type STD_LOGIC in particular. More on data types, later.


ECADLAB(VHDL) 264

Entity AOI is

The name of the design entity is just an arbitrary label invented by the user. It does not correspond to a name pre-defined in a VHDL component library. entity and is are VHDL keywords. This line defines the start of a new VHDL design unit definition. The library and use clauses, although written before the entity declaration do not define the start the VHDL description of a design unit, they are context clauses. We can think of an entity declaration as corresponding to a chip package.

port (


F : out STD_LOGIC );

The entity declaration includes the name of the entity (AOI in this example), and a set of port declarations. A port may correspond to a pin on an IC, an edge connector on a board, or any logical channel of communication with a block of hardware. Each port declaration includes the name of one or more ports ( e.g., A, B), the direction that information is allowed to flow through the ports (in, out or inout), and the data type of the ports (i.e., STD_LOGIC). In our example the port declarations correspond to the pins of our AOI chip.

The data type of a port defines the set of values that may flow through the port. The ports are of type STD_LOGIC, which is found in package STD_LOGIC_1164 in library IEEE. A package is a VHDL language construct where new data types may be defined, and the particular package STD_LOGIC_1164 is an IEEE standard for representing digital signals in VHDL. The concept of data type is borrowed by VHDL from the world of software. It allows the VHDL compiler to ensure that the design is at least reasonably robust before beginning simulation.

end AOI;

The entity declaration is terminated by the VHDL keyword end. Here we indulge in a little programming robustness by adding the name of the design entity after the end keyword. Including the name of the design entity is particularly relevant in large descriptions where the port list may extend over many screens (or pages); it is good to be reminded of the name of the design entity whose end we are looking at, lest we forget.


The name of the architecture body (V1) is just an arbitrary label invented by the user. It is possible to define several alternative architecture bodies for a single design entity, and the only purpose of the architecture name is to distinguish between these alternatives. architecture, of and portis are VHDL keywords. Note that when we define an architecture, we have to tell the VHDL analyzer that the architecture V1 corresponds to the AOI design entity. You might think that it would be enough to specify the name of the architecture and that the architecture automatically corresponded to the previously


ECADLAB(VHDL) 265

declared entity, but I'm afraid VHDL doesn't work this way! In essence, we can think of the architecture as the die inside the chip package.

begin

The VHDL keyword begin denotes the end of the architecture declarative region and the start of the architecture statement part. In this architecture, there is but one statement, and all the names referenced in this statement are in fact the ports of the design. Because all of the names used in the architecture statement part are declared in the entity declaration, the architecture declarative part is empty.


The architecture contains a concurrent signal assignment, which describes the function of the design entity. The concurrent assignment executes whenever one of the four ports A, B, C or port D change value. That's it! That's all there is to describing the functionality of an AOI gate in VHDL. Some might regard the rest of the VHDL code as superfluous and level a charge of verbosity against VHDL. Of course, the remainder of the VHDL code is setting the context in which this functionality is defined.

end V1;

The architecture is terminated by the VHDL keyword end. Once again, we reference the architecture name at the end of the architecture body for the same reason as we did with the entity. Usually, architecture bodies require sigificantly more code than entity declarations, hence repeating the name of the architecture is even more relevant.

-- end of VHDL code

Another VHDL comment, and that's the end of a VHDL description of an AOI gate.

Internal signals

Shown below is a second architecture V2 of AOI (remember that the architecture name V2 is completely arbitrary - this architecture is called V2 to distinguish it from the earlier architecture V1). Architecture V2 describes the AOI function by breaking it down into the constituent boolean operations. Each operation is described within a separate concurrent signal assignment. In hardware terms we can think of each assignment as a die in a hybrid package or a multi-chip module. The signals are the bonding wires or substrate traces between each die.

Signals

The architecture contains three signals AB, CD and O, used internally within the architecture. A signal is declared before the begin, of an architecture, and has its own data type (eg. STD_LOGIC). Technically, ports are signals, so signals and ports are read and assigned in the same way.


ECADLAB(VHDL) 266

Assignments

The assignments within the architecture are concurrent signal assignments. Such assignments execute whenever a signal on the right hand side of the assignment changes value. Because of this, the order in which concurrent assignments are written has no effect on their execution. The assignments are concurrent because potentially two assignments could execute at the same time (if two inputs changed simultaneously). The style of description that uses only concurrent assignments is sometimes termed dataflow.

Delays

Each of the concurrent signal assignments has a delay. The expression on the right hand side is evaluated whenever a signal on the right hand side changes value, and the signal on the left hand side of the assignment is updated with the new value after the given delay. In this case, a change on the port A would propagate through the AOI entity to the port F, with a total delay of 5 ns.

VHDL: Internal signals of an AOI gate

library IEEE;


entity AOI is

port (A, B, C, D: in STD_LOGIC;

F : out STD_LOGIC);

end AOI;


signal AB, CD, O: STD_LOGIC;

begin

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AB <= A and B after 2 NS;

CD <= C and D after 2 NS;

O <= AB or CD after 2 NS;

F <= not O after 1 NS;

end V2;

Components and Port Maps

The example above shows the previously defined design entity AOI being used as a component within another, higher level design entity MUX2, to create a design hierarchy with two levels. The design entity MUX2 also contains a second component, named INV. In order to write the VHDL for this circuit, we need to cover two new concepts: component instantiation (placing the INV and AOI inside another higher-level design, MUX2) and port mapping (connecting up the two components to each other and to the primary ports of MUX2). In VHDL, this is how we can model PCBs assembled from individual chips, for example.

Components

The two component declarations (for INV and AOI) must match the corresponding entity declarations exactly with respect to the names, order and types of the ports. We've already seen enough of the AOI gate, let's see how closely the component and entity declarations match for the INV design entity.


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Entity Component

entity INV is

port (A: in STD_LOGIC;

F: out STD_LOGIC);

end INV;

component INV


F: out STD_LOGIC);

end component;

The two component declarations (for INV and AOI) appear in the architecture declarative part (that's a VHDL technical

term that means that the component declarations are coded before the begin).

library IEEE;


entity MUX2 is

port (SEL, A, B: in STD_LOGIC;

F : out STD_LOGIC);

end;

architecture STRUCTURE of MUX2 is

component INV


F: out STD_LOGIC);

end component;

component AOI

port (A, B, C, D: in STD_LOGIC;

F : out STD_LOGIC);

end component;

signal SELB: STD_LOGIC;

begin

G1: INV port map (SEL, SELB);

G2: AOI port map (SEL, A, SELB, B, F);

end;


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Instantiation

The architecture STRUCTURE of MUX2 makes instances of INV and AOI through the component instantiations at the bottom of the architecture (labelled G1 and G2). The component names (INV and AOI) are references to design entities defined elsewhere. The instance labels (G1 and G2) identify two specific instances of the components, and are mandatory.

Port Maps

The ports in a component declaration must usually match the ports in the entity declaration one-for-one. The component declaration defines the names, order, mode and types of the ports to be used when the component is instanced in the architecture body. Instancing a component implies making a local copy of the corresponding design entity - a component is declared once within any architecture, but may be instanced any number of times. In this example, there is just one instance of the components AOI and INV.

Association

Signals in an architecture are associated with ports on a component using a port map. In effect, a port map makes an electrical connection between “pieces of wire” in an architecture (signals) and pins on a component (ports). The same signal may be associated with several ports - this is the way to define interconnections between components. In our MUX2 example, the signal SELB is associated with the F port of the INV instance and the C port of the AOI instance.

Plugging Chips into Sockets

On the page “Components and Port Maps”, we looked at the VHDL used to describe the instantiation of components in an architecture. Instantiating components in VHDL


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enables us to create a design hierarchy, it's just like plugging chips into a PCB. In our case, the MUX2 is the PCB, the AOI gate andthe inverter (INV) are two chips. But what about the sockets? Let's look into instantiating components in a little more detail.

Component Declarations

Remember that the two component declarations (for INV and AOI) must match the corresponding entity declarations exactly with respect to the names, order and types of the ports. This is important because, as a hardware analogy, the component declaration is essentially a chip socket for the chip represented by the design entity - the entity declaration defines the pins of the chip.

Component Instantiation

So, instantiation is essentially a VHDL term for soldering a chip socket into a PCB. Instantiation also assumes that the socket contains the chip referenced by the same name as it is plugged into the PCB. However, for our purposes, we can think of component instantiation as plugging a chip into a PCB, ignoring whether it's socketed or not.

Component Declaration Component Instantiation

component INV


F: out STD_LOGIC);

end component;

G1: INV

port map (SEL,

SELB

);

Port Mapping

The concept of port mapping is little more than soldering the chip socket pins into the holes of the PCB. Thus in the case of our inverter, the F output pin of the INV chip is plugged into the F pin of the INV socket. The F pin of the INV socket is soldered to a PCB trace called SELB.

Similarly, instantiation of the AOI gate can be thought of as soldering the AOI socket into the MUX2 PCB. In this case, as an example, the SELB trace is soldered to the C pin of the AOI socket. By default, the AOI socket is assumed to be carrying an AOI chip.


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component AOI

port (A, B, C, D: in STD_LOGIC; -- 3rd item in list is C

F : out STD_LOGIC);

end component;

signal SELB: STD_LOGIC;

begin

G2: AOI port map (SEL, A, SELB, B, F); -- 3rd item in list is SELB

end;

Default binding

Our current view of component instantiation assumes default binding. In default binding, the chip socket (component declaration) carries a chip (design entity) of the same name (say, AOI) as we've already seen. Now in the hardware world, there's no such limitation, sockets aren't chip specific. VHDL allows the designer the same freedom. The chip socket and the chip do not have to have the same name, but to implement this facility requires a configuration to bind the appropriate design entity to the component instantiation.

Configurations: Part 1

On the page “Plugging Chips into Sockets” it was suggested (in the default binding section) that an instantiation of a design entity need not have a component declaration of the same name to be legal VHDL, providing we use a configuration to change the default binding. In the case of Plugging Chips into Sockets, the emphasis was on establishing the relationships between component declaration, design entity (particularly its entity declaration) and component instantiation.

Remember that the design entity (chip package) consists of both an entity declaration (chip pins) and architecture body (chip die). In Part 1 of Configurations, we will look at


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selecting one architecture from many architectures of one design entity for instantiation (essentially specifying which die goes in the package of the chip that will be plugged into the PCB to maintain our analogy) and in Part 2, we will look at choosing from amongst different design entities for instantiation (essentially specifying which chip to plug into the socket).

Configuration

A VHDL description may consist of many design entites, each with several architectures, and organized into a design hierarchy. The configuration does the job of specifying the exact set of entities and architectures used in a particular simulation or synthesis run.

A configuration does two things. Firstly, a configuration specifies the design entity used in place of each component instance (i.e., it plugs the chip into the chip socket and then the socket-chip assembly into the PCB). Secondly, a configuration specifies the architecture to be used for each design entity (i.e., which die).

Default configuration5

Shown below is a minimal configuration for the top level entity MUX2. This configuration selects the architecture to be used (there is only one, STRUCTURE). By default, all components inside the architecture will be configured to use a design entity of the same name as the component (i.e., AOI), and the most recently analyzed architecture of each design entity. We'll tackle the concept of the most recently analyzed architecture in the next but one article in this series. Suffice to say that in this example we will take v2 to be the most recently analyzed, by virtue of the fact that we compiled the v1 version of AOI first and then compiled the v2 version of our AOI design entity a few minutes later (let's say).

Configuration declaration

The configuration declaration is yet another one of those VHDL design units. Remember the entity declaration is a design unit as is the architecture body. In the configuration declaration, for the architecture that we want to configure, we can specify exactly which components make up the final design entity. In the example below, for the G2 instance inside our STRUCTURE architecture, we use the V1 architecture of the AOI gate. There will be absolutely no doubt as to which architecture has been chosen for simulation because we have specified v1 in the configuration. In the MUX2_default_CFG configuration, we could change the AOI architecture for simulation by simply re-compiling v1 after v2 - hardly a robust mechanism for design description! Note, that you only need to be concerned with configurations of multiple architectures when you have more than one architecture per design entity in the first place.


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Default configuration of MUX2

use WORK.all;

configuration MUX2_default_CFG of MUX2 is

for STRUCTURE

-- Components inside STRUCTURE configured by default

-- let's say v2 architecture for AOI

end for;

end MUX2_default_CFG;

Specified configuration of MUX2

use WORK.all;

configuration MUX2_specified_CFG of MUX2 is

for STRUCTURE

for G2 : AOI

use entity work.AOI(v1);

-- architecture v1 specified for AOI design entity

end for;

end for;

end MUX2_specified_CFG;

Once again, let's break the VHDL code down fragment by fragment, using the specified configuration. Leaving aside the use clause for now, the first line specifies what we are configuring, configuration is a VHDL keyword and is followed by the name we wish to give the configuration. After the of keyword we specify the design entity we are configuring; is is also a keyword. Bracketed with this first line is the last end configuration_name line. Hence, Configurations usually consist of nested configuration items, bracketed with end for; statements. The first item is the architecture specification, the second is the instance specification, and finally the binding indication,

configuration MUX2_specified_CFG of MUX2 is

-- block configuration


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end MUX2_specified_CFG;

for architecture_name

-- thus, for STRUCTURE

for instance_label : component_name

-- thus, for G2 : AOI

use entity library_name.entity_name(architecture_name)

-- thus, use entity work.AOI(v1); use WORK. all;

Now, what about that use clause? Let's say the AOI design entity is compiled into the working library WORK by default. Thus in order for the component_name to be visible we need a use clause, hence is required.

Configurations: Part 2

Let's review default binding before we go any further. In default binding, the chip socket (component declaration) carries a chip (design entity) of the same name (say, AOI) as we've already seen. The chip is inserted into the socket courtesy of a component instantiation and a configuration declaration. If we omit the configuration or if we use a default configuration, the socket and chip must have the same name. If we want to choose a particular die (architecture) for our chip, we must specify the architecture in the configuration. Now. Suppose we want to create a general-purpose socket and at some later time, we want to specify which chip will be plugged into the socket. To do this requires a late-binding configuration declaration.

Order of Analysis

This is one of those topics that doesn't really relate to hardware design. However, you can't ignore this topic as it is so fundamental to simulating (and to a lesser extent, synthesizing) your VHDL designs. Anyhow, let's see how hardware-y we can make it!

Remember design units? So far we have used three of the five VHDL design units. An entity declaration is a primary design unit, as is a configuration declaration. An architecture body is a secondary design unit. An architecture is a secondary design unit of the corresponding entity declaration primary design unit. Hence, To simulate a piece of VHDL code, you need a design environment consisting of an entity declaration and an architecture body and you also need a testbench. The testbench contains an instance of the design plus some VHDL code to apply stimuli to the design that is being simulated. In VHDL terms, the testbench is just another design entity.


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architecture architecture_name of entity_name is --secondary primary.

On to order of analysis, following on from the hardware analogy we used in the Configuration pages. In the VHDL design world, you have to create the chip package first before you can glue in the die. So, create the chip package (and put it into stores), then create the chip die (and put that in to stores, too). Someone in stores will check to see that a package for the die exists, if not they'll give it back. Once you have done that, you can check the assembled chip out of stores any time you like. We'll look at checking items out of stores later on. In VHDL, checking items into stores is called analysis. In VHDL, stores is called a library (yes, in VHDL you can have lots of storerooms, hence a library not the library). So, this requires that before you analyze any architecture into a library, you must first analyze the corresponding entity declaration into the same library.

In the real world, you can goof up and put an empty chip package in to stores. You can do the same in VHDL, too. Analyzing an entity declaration into a library is OK. Conversely, a VHDL architecture body must not exist alone (the VHDL storeman will lose that tiny die!); an architecture won't be put into a library unless there's already an entity declaration in the library.

To summarise, VHDL design units are analyzed into VHDL libraries. One default library is provided for you, it is called WORK. Once you have have analyzed all of the design units you need for a simulation run into a VHDL library, you can run the simulation...

Simulating the MUX2

Let's suppose we have a rudimentary Unix or Windows'95 DOS Box command line interface for our VHDL simulator. The analyze comand allows you to specify a VHDL library name and a filename in order to analyze the VHDL source code. We'll assume that each VHDL design unit has it's own file. To analyze the VHDL in the correct order for simulation, we would enter the following commands, one after the other,

analyze -library WORK -file aoi.entity

analyze -library WORK -file aoi.v1.architecture

analyze -library WORK -file mux2.entity

analyze -library WORK -file mux2.v1.architecture

analyze -library WORK -file mux2test.entity

analyze -library WORK -file mux2test.v1.architecture

analyze -library WORK -file mux2test.v1.configuration on the command line.

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Vectored Ports and Signals

Ports can represent busses or vectors as well as single bits. In the example above, the port SEL is a 2-bit bus, with msb numbered 1 and lsb numbered 0. The type of the port is STD_LOGIC_VECTOR, which is also defined in package STD_LOGIC_1164 on library IEEE. Objects of type STD_LOGIC_VECTOR are simply an array of STD_LOGIC objects.

Vectors used in a MUX4 design

library IEEE;


entity MUX4 is

port (SEL : in STD_LOGIC_VECTOR(1 downto 0);


F : out STD_LOGIC); end MUX4;

In the previous example, an array type was used to allow the description in VHDL of a vectored port. Array types can be used for internal signals as well as ports. This can be seen in the MUX4 testbench code below:

entity TEST_MUX4 is

architecture BENCH of TEST_MUX4 is

signal SEL: STD_LOGIC_VECTOR(1 downto 0);

begin

SEL <= "00",

"01" after 30 NS,


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"10" after 60 NS,

"11" after 90 NS,

"XX" after 120 NS,

"00" after 130 NS;

M: MUX4 port map (SEL, A, B, C, D, F);

end BENCH;

The stimulus for the SEL signal is shown as a waveform, made up of individual waveform elements. A waveform element consists of an expression followed by a time specification for when the signal is driven by the value of the expression. In this particular case, the expression is a STD_LOGIC_VECTOR literal. STD_LOGIC_VECTOR values can be written as bit string literals. For example both bits are set to '0 at time 0, while at time 30 ns, SEL(1) is set to '0' and SEL(0) is set to '1'.

Test Benches

So we have a design. But it's unproven. In this tutorial we look at designing a simple test bench in VHDL.

With VHDL, it is possible to model not only the hardware or system design, but also a test bench to apply stimulus to the design and to analyze the results, or compare the


ECADLAB(VHDL) 278

results of two simulations. In effect, VHDL can be used as a stimulus definition language as well as a hardware description language. One consequence of using VHDL to model a test bench is that the test bench is portable between VHDL tools from different vendors.

Test Bench for MUX4

The entity declaration for a test bench (entity TEST_MUX4 is ... end ;) is usually empty. This is because the test bench itself does not have any inputs or outputs. Test vectors are generated and applied to the unit under test within the test bench. Note that it is illegal to have an architecture body without an entity declaration.

Components

A component declaration is needed (component MUX4 ... end component;) in order to pull the MUX4 entity into the test bench. Think of a component declaration as a chip socket. It allows a VHDL structural description to be written in a top-down manner, because the VHDL compiler can check the consistency of the design unit that uses the component before the corresponding design entity has been written. In order that the VHDL simulator can bind (more VHDL jargon) the design entity MUX4 to the component MUX4, the names and types of the ports must match between the entity and the component.

Test Bench for MUX4

entity TEST_MUX4 is

end;

library IEEE;



component MUX4

end component;

-- signals

begin

-- signal assignments to create stimulus

M: MUX4 port map (...);

end BENCH;

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Concurrent Assignment

The 5 concurrent signal assignment statements within the test bench define the input test vectors (eg. A <= 'X', '0' after 10 NS, '1' after 20 NS;). The delays in these assignments are relative to the time when the assignments execute (ie. time 0), not to each other (eg. Signal A will change to '1' at 20 NS, not at 30 NS).

Test Bench for MUX4

entity TEST_MUX4 is

end;

library IEEE;



component MUX4

port (SEL :in STD_LOGIC_VECTOR(1 downto 0);

A, B, C, D:in STD_LOGIC;

F :out STD_LOGIC);

end component;

signal SEL: STD_LOGIC_VECTOR(1 downto 0);

signal A, B, C, D, F: STD_LOGIC;

begin

SEL <= "00", "01" after 30 NS, "10" after 60 NS,

"11" after 90 NS, "XX" after 120 NS,

"00" after 130 NS;

A <= 'X', '0' after 10 NS, '1' after 20 NS;

B <= 'X', '0' after 40 NS, '1' after 50 NS;

C <= 'X', '0' after 70 NS, '1' after 80 NS;

D <= 'X', '0' after 100 NS, '1' after 110 NS;


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M: MUX4 port map (SEL, A, B, C, D, F);

end BENCH;

The waveforms generated for the SEL, A, B and C signals are shown below.

Bottom-up design

Joining components together is one method of design using VHDL. It's the bottom-up approach. There's nothing wrong with joining components together to create a design hierarchy, but using it as your design approach exclusively can restrict your productivity even though it is possible to create any design you could wish for using VHDL in this manner. Let's step back a moment and consider how the design of something as simple as a MUX_2 is being implemented; not at a hardware level but at a conceptual level. We'll change the MUX_2 so that it has an inverting data path:

signal SELB, FB: STD_LOGIC;

begin


G2: AOI port map (SEL, A, SELB, B, FB);

G3: INV port map (FB, F);

Adopting a structural design approach, we first have to decide what we want to do (switch between two inputs) and secondly how to implement it (using components). So, while joining components together has its place, we really ought to move on to a better low-level design approach. Instead of determining the functionality and then implementing it, we're going to describe the functionality and leave it at that. We're not going to worry about implementation. Well, ultimately we will concern ourselves with implementation but from a coding point of view, let's get the functionality or behavior out of the way first.


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Coding behavior

At a conceptual level we can specify what we want the design to do using a behavioral coding style. Using the structural approach, we have to describe explicitly how the design is to be implemented. Thus a structural approach implies an extra step in the design process. So, how do we implement (smile) a behavioral coding style? Well, this can be achieved by writing VHDL code as though we were writing software rather than describing hardware. We can take our VHDL coding capabilities closer to VHDL programming, closer to writing software rather than describing hardware. By writing software rather than describing hardware, we can concentrate on what a design does rather than how it does it. We can concern ourselves with functionality rather than implementation. In the same way that mathematicians look to abstract a concept to make a problem easier to solve and provide more flexible solutions, we can abstract our designs from VHDL hardware descriptions to VHDL software functions. However, a software function will still at some point become a hardware description. We can bridge the gap from software function to hardware description using synthesis.

With the behavioural approach to design, we still have to decide what we want to do, but that's it. We can use synthesis tools to decide how to implement the functionality we have (behaviourally) specified. There are still two steps in creating a netlist that meets our design goals, it's just that with a behavioural approach we use design automation to complete the second (implementation) step. Hopefully, this can save us time because we as engineers only have to do one job instead of two. Using a software-oriented design approach we can reduce the number of design steps.

Components vs. Processes

Designs could be created using a more software-oriented behavioral style of VHDL coding rather than the explicit structural coding style used to create the MUX_2 design. Before we look at how to describe a MUX_2 using a behavioral coding approach, let's deal with how VHDL designs operate - the MUX_2 will serve as our example. signal SELB, FB: STD_LOGIC;


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Begin


G2: AOI port map (SEL, A, SELB, B, FB);


Sequential, parallel or concurrent?

Conceptually, the AOI and INV components operate concurrently. They do not operate in parallel. Sorry for being pedantic but this subtlety is important. Parallel means operate simultaneously, usually without communication between the parallel elements (“never touching” in my dictionary). Concurrency means cooperating, taking place at the same time or location, with the cooperation implied through communication.

In VHDL, we usually speak of elements executing rather than operating (or cooperating), so in VHDL elements can execute concurrently, in parallel or in sequence. We can see that the AOI and INV components execute concurrently - they communicate via the internal signals. You might think that they execute in sequence. (Almost!) If SEL changes and A, B have the same value then the G1 instance of INV executes in parallel with AOI. As FB does not change value the G3 instance of INV does not execute. This simple scenario shows the absence of parallel execution (G3 doesn't execute whilst G1 and G2 are executing) and sequential execution (G3 doesn't execute after G2); this leaves us with concurrency. We often say to ourselves that the AOI and INV are connected. We now know that being connected means concurrent execution. In our example, the functionality of the MUX_2 is implemented via components executing concurrently.

Processes

To create software-style VHDL, we first have to deal with processes. We can think of a VHDL process as a blob of hardware. Instead of instantiating a component in an architecture, we can instantiate a process. For our MUX_2 example, let's dispense with concurrency altogether. Let's use a single process. Processes enable you to code up a design by describing the design's functionality using statements executing in sequence. This is different from the way in which components create functionality. Components create functionality by executing concurrently with respect to each other.

A process can contain signal assignments to describe the functionality of a design. Thus, we can re-code our MUX_2 example using a single process rather than three component instantiations. Processes do not have to exist in isolation. A process is a concurrent statement inside an architecture body just like a component instantiation. We know that components can be connected together using signals and so too can processes. So processes execute with respect to each other concurrently, but internally


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they execute statements in sequence. You can describe functionality using sequential statements inside processes. And you can create multiple processes within architecture to create your design. But there are a couple of things you can't do - a component instance is not a sequential statement so you can't execute a component inside a process. And you can't embed one process inside another in the way that you can embed component instances within each other, so there's no way to build a process hierarchy. To build a design hierarchy, you have to use components.

An extension to the approach of behavioral coding is to describe the functionality of the design by using software-oriented methods exclusively that don't use components. In VHDL, this is accomplished using processes to replace component instances. Processes enable you to code up a design by describing the design's functionality using statements executing in sequence. Instead of writing:


-- signal and component declarations...

begin


G2: AOI port map (SEL, A, SELB, B, F);

end;

We can write:

architecture BEHAVIOUR of MUX2 is

-- signal declarations (no components!)...

begin

G1: process

-- software-style VHDL for the INV component

end process;

G2: process

-- software-style VHDL for the AOI component

end process; end;


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Processes

In VHDL, the process statement contains sequential statements.

Processes are only permitted inside an architecture. The statements within processes execute sequentially, not concurrently.

Processes can be written in a variety of ways. The most common approach when using processes to describe designs is to use the form that has a sensitivity list.

We shall use two processes in our MUX_2 design, one to replace the AOI gate, the other to replace the inverter. We will then merge the two processes to see how a single process can be used to describe the design.

First of all, let's tackle the AOI gate. All we do is extract the signal assignment from the v1 architecture and insert it into the process. At this point, the signal assignment is a sequential signal assignment rather than a concurrent signal assignment. At this stage all we have done is wrap a process around the signal assignment.

v1_arch: process -- incomplete at this stage

begin


end process;

To make this process complete, we have to remember that we are describing a piece of combinational logic. From a conceptual point of view, the outputs of a combinational circuit CAN change when ANY one of the inputs changes. This means that we need to cause the process to execute when any of the ‘inputs' to the process changes. The way to do this is to create a sensitivity list for the process from the signals A, B, C and D. The sensitivity list follows the process keyword as shown:

v1_arch: process (A, B, C, D)

begin


end process;

However, inside the MUX_2 design, we are using the the ports and signals of that design, so:

G2: process (SEL, A, SELB, B)

begin

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F <= not ((SEL and A) or (SELB and B));

end process;

Likewise for the inverter:

G1: process (A)

begin

SELB <= not SEL;

end process;

We can combine these two processes into one:

combined: process (SEL, A, B)

begin

F <= not ((SEL and A) or ((not SEL) and B));

end process;

Notice that not SEL from the G1 process was used to substitute the SELB in the G2 process. We now have a single process with a sensitivity list made up from only the MUX_2 ports - no internal signals.

RTL Coding

We saw how to use processes to describe a MUX_2 design. However, the coding approach used was somewhat low-level, in that the code consisted of binary operators.

In order to adopt high-level design principles, it is necessary to try and describe a design at a higher level of abstraction. This means thinking about the functionality of the design rather than its implementation. This allows the synthesis tool to optimize the functionality you have specified, leaving you to describe what the design does, whilst the synthesis


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tool's job is to implement the design how it sees fit in order to create the optimal implementation. The style of coding required for synthesis tools is known as RTL coding.

Most commercially available synthesis tools expect to be given a design description in RTL form. RTL is an acronym for register transfer level. This implies that your VHDL code describes how data is transformed as it is passed from register to register. The transforming of the data is performed by the combinational logic that exists between the registers. Don't worry! RTL code also applies to pure combinational logic - you don't have to use registers. Using processes in RTL descriptions is particularly appropriate for input to a synthesis tool. For example, using component instances implies a level of structure in the design. This can sometimes be advantageous particularly on a large design but for a 2-input multiplexer.

library IEEE;


entity MUX2 is

port (SEL, A, B: in STD_LOGIC;

F : out STD_LOGIC);

end;

architecture BEHAVIOUR of MUX2 is

begin

-- descibed using a single process

end;

For the functionality, let's get conceptual. If sel is a logic 1, a is routed through to the f output. On the other hand if sel is a logic 0, b is routed through to the f output. Rather than think about routing one of the inputs through to the output let's think about the output getting one of the inputs, and let's write the text on separate lines depending upon whether we are making a decision or performing an action (sometimes referred to as pseudo-code):

if sel is logic 1

f gets a

otherwise

f gets b

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This can be translated into VHDL code:

if sel = '1' then

f <= a;

else

f <= b;

end if;

Now before we go any further, we'll just take this code snippet a line at a time.

if sel = '1'

The VHDL language allows for many different kinds of sequential statement. The sequential signal assignment is a signal assignment that can appear inside a process. You have already come across this statement in the Processes page (assignment to F in the combined process, if you remember). Here's another: the if statement. Actually this line is part of the if-else statement that is the entire code snippet. if is a VHDL keyword. After the if keyword you have a conditional expression, in this case sel = '1' - does sel have the value logic 1? If so...

f <= a;

f gets the value on the a input. But what if sel is not logic 1?

else

Otherwise (assume sel is logic 0 - more on this assumption later)...

f <= b;

f gets the value on the b input.

end if;

simply denotes the end of the if-else statement.

So, as it turns out, we have described the functionality of the MUX_2 design using a single sequential statement, the if-else statement. In each branch of this if-else statement, there is an additional sequential statement, either assigning a to f, or b to f, depending upon the value of sel. But we have to remember that sequential statements always live inside a process, so

process (sel, a, b)

begin

ECADLAB(VHDL) 288

if sel = '1' then

f <= a;

else

f <= b;

end if;

end

This now enables us to describe a design using a list of concurrent signal assignments, a hierarchy of designs (using component instances) or a process. Compare the 3 approaches for yourself:

// concurrent signal assignments

selb <= not sel;

fb <= not((a and sel) or (b and selb));

f <= not fb;

// a hierarchy of designs


G2: AOI port map (SELB, A, SEL, B, FB);


// process

process (sel, a, b)

begin

if sel = '1' then

f <= a;

else

f <= b;

end if;


ECADLAB(VHDL) 289

end process;

And of course you can mix'n'match coding styles if you wish. On a simple design, such as a MUX_2 it is perhaps not apparent how succinct the use of processes is in general compared to component instances and concurrent signal assignments. But you can readily appreciate that the use of just one process in this design is enabling us to describe the design in terms of its functionality without regard to the implementation. You can describe what you want without having to worry about how you are going to implement the design (because you don't have to - that's the synthesis tool's job!).

If statement

In the last article, we looked at describing hardware conceptually using processes. What kind of hardware can we describe? What are the limitations? What kinds of VHDL statement can be used in always blocks to describe hardware? Well, we have already seen the use of an if statement to describe a multiplexer, so let's dwell on if statements for this month's tutorial.

process (sensitivity-list) -- invalid VHDL code!

-- process declarative region

begin

-- statements

end process;

The code snippet above outlines a way to describe combinational logic using processes. To model a multiplexer, an if statement was used to describe the functionality. In addition, all of the inputs to the multiplexer were specified in the sensitivity list.

ECADLAB(VHDL) 290

signal sel, a, b : std_logic;

process (sel, a, b)

begin

if sel = '1' then

f <= a;

else

f <= b;

end if;

end process;

Sensitivity list

It is a fundamental rule of VHDL that only signals (which includes input and buffer ports) must appear in the sensitivity list.

Combinational logic

It transpires that in order to create VHDL code that can be input to a synthesis tool for the synthesis of combinational logic, the requirement for all inputs to the hardware to appear in the sensitivity list is a golden rule.

Golden Rule 1:

To synthesize combinational logic using a process, all inputs to the design must appear in the sensitivity list.

Altogether there are 3 golden rules for synthesizing combinational logic, we will address each of these golden rules over the next couple of articles in this tutorial.

If

The if statement in VHDL is a sequential statement that conditionally executes other sequential statements, depending upon the value of some condition. An if statement may optionally contain an else part, executed if the condition is false. Although the else part is optional, for the time being, we will code up if statements with a corresponding else rather than simple if statements. To incorporate more than one sequential statement in an if statement, simply list the statements one after the other, there are no special bracketing rules in VHDL as there are in some programming languages,

ECADLAB(VHDL) 291

signal f, g : std_logic; -- a new signal, g

process (sel, a, b)

begin

if sel = '1' then

f <= a;

g <= not a;

else

f = b;

g = a and b;

end if;

end process;

If statements can be nested if you have more complex behaviour to describe:

signal f, g : std_logic;

process (sel, sel_2, a, b)

begin

if sel = '1' then

f <= a;

if sel_2 = '1' then

g <= not a;

else

g <= not b;

else

if sel_2 = '1' then

g <= a and b;

ECADLAB(VHDL) 292

else

g <= a or b;

end if;

f <= b;

end if;

end process;

Synthesis considerations

If statements are synthesized by generating a multiplexer for each register assigned within the if statement. The select input on each mux is driven by logic determined by the if condition, and the data inputs are determined by the expressions on the right hand sides of the assignments. During subsequent optimization by a synthesis tool, the multiplexer architecture may be changed to a structure using and-or-invert gates as surrounding functionality such as the and, or and not can be merged into complex and-or-invert gates to yield a more compact hardware implementation.

Synthesizing Latches

In the last article, if statements were used to describe simple combinational logic circuits. Synthesizing the VHDL code produced multiplexing circuits, although the exact implementation depends upon the synthesis tool used and the target architecture of the device. As well as enabling the creation of multiplexers, if statements can also be used to implement tristate buffers and transparent latches. In this article we will look at how transparent latches are synthesized from if statements and how to avoid the inadvertent creation of latches when you meant to create combinational logic circuits from VHDL code containing if statements.

If Statements

In the processes that have been coded up so far, if-else statements rather than simple if statements have been used. Let's use a simple if statement rather than an if-else statement in an example you have already seen:

signal sel, a, b: std_logic;

if_else: process (sel, a, b)

begin

if sel = '1' then

f <= a;

ECADLAB(VHDL) 293

else

f <= b;

end if;

end process;

becomes...

signal sel, a, b : std_logic;

pure_if: process (sel, a, b)

begin

f <= b;

if sel = '1' then

f <= a;

end if;

end process;

Note that the behaviour being described is the same. In the pure_if process, f initially gets b. Only if sel is active HIGH does f get a. This is perhaps a slightly odd way to describe a multiplexing circuit but it is accepted by all synthesis tools. Synthesis tools expect to create circuits responding to only binary ('0' and '1' in VHDL) values. As far as a synthesis tool is concerned if sel is '1' a is routed through to f. If sel is not '1' it must be '0' and thus sel being '0' leaves f being driven by the initial assignment from b.

ECADLAB(VHDL) 294

Let's lose the b input to the process so that we have:

signal sel, a : std_logic;

latching_if: process (sel, a)

begin

if sel = '1' then

f <= a;

end if;

end process;

Incomplete Assignment

Now analyze the behaviour of the code. If sel is '1', f gets a. But what happens when sel is '0'? Well, very simply, nothing! f does not and can not change. When sel is fixed at '0', we can change a as much as we like, f will not be assigned the value of a. If we suppose that an if statement synthesises to a multiplexer, then we must be able to configure the multiplexer such that f only gets the value of a when sel is '1'. This can be achieved by feeding back the multiplexer f output back to the '0' input. in hardware terms this is a transparent latch and this is exactly the hardware synthesized by a synthesis tool given this VHDL code.

If the target architecture does not contain transparent latches the synthesis tool will generate multiplexer circuits that employ combinational feedback in order to mimic the latching behavior required. Now, this is very well but what's really happening here? One minute if statements create multiplexers, the next they create latches. Well, it's not the if statements, but the process as a whole that counts. If it is possible to execute a process without assigning a value to a signal in that process, the signal will be implemented as a transparent latch. This is known as incomplete assignment.

Note that this golden rule states that all objects must be assigned under all conditions. This is because signals are not the only VHDL objects, there are also variables in VHDL. In a later tutorial, we will use variables inside a process to describe functionality.

ECADLAB(VHDL) 295

Golden Rule 2:

To synthesize combinational logic using a process, all objects must be assigned under all conditions.

Simplifying code analysis

Suppose you are creating a process to describe combinational logic. This process consists of nested if-else statements as follows:

signal f, g : std_logic;

process (sel, sel_2, sel_3, a, b)

begin

if sel = '1' then

f <= a;

if sel_2 = '1' then

g <= not a;

else

g <= not b;

if sel_3 = '1' then

g <= a xor b;

end if;

end if;

else

if sel_2 = '1' then

g <= a and b;

else

if sel_3 = '1' then

g <= a nand b;

ECADLAB(VHDL) 296

-- oops! no else

-- else

-- g <= ...

end if;

end if;

f <= b;

end if;

end process;

Will you get transparent latches on the f and g outputs? Not easy is it? If you look carefully you will see that in fact, g is latched when sel is '0', sel_2 is '0' and sel_3 is '0'. The ‘oops!' comment should help you to see where the complete assignment is NOT made.

Fortunately, it is possible to save yourself the bother of scouring through the process code to locate possible incomplete assignments by setting signals to default values at the start of the process. Using this approach you may get undesired functionality if you have missed out an assignment (which should be easy to fix) as opposed to unwanted transparent latches. For our current example,

ECADLAB(VHDL) 297

process (sel, sel_2, sel_3 a, b)

begin

-- default values assigned to f, g

f <= b;

g <= a and b;

if sel = '1' then

f <= a;

if sel_2 = '1' then

g <= not a;

else

g <= not b;

if sel_3 = '1' then

g <= a xor b;

end if;

end if;

else

if sel_2 = '1' then

g <= a and b;

else

if sel_3 = '1' then

g <= a nand b;

end if;

end if;

end if;

end process;


ECADLAB(VHDL) 298

VHDL Design Units and Subprograms

A design unit may be the entire file or there may be more than one design unit in a file. No less than a design unit may be in a file. Any design unit may contain a context clause as its initial part. The context clause of a primary unit applies to all of the primary units corresponding secondary units. Architectures and package bodies are the secondary units. Subprograms are not library units and must be inside entities, architectures or packages. The analysis, compilation, of a design unit results in a library unit is some design library. Predefined libraries typically include but are not limited to: STD, IEEE and WORK. WORK is the default user library.

Entity The top of every design hierarchy must be an entity. Entities may range from primitive circuits to complex assemblies. The entity code typically defines just the interface of the entity. entity identifier is generic ( generic_variable_declarations ) ; -- optional port ( input_and_output_variable_declarations ) ; [ declarations , see allowed list below ] -- optional begin \__ optional [ statements , see allowed list below ] / end entity identifier ; generic_variable_declarations are of the form: variable_name : variable_type := variable_value ; -- := variable_value optional input_and_output_variable_declaration are of the form: variable_name : port_mode variable_type ; port_mode may be in out inout buffer linkage entity adder is generic ( N : natural := 32 ) ; port ( A : in bit_vector(N-1 downto 0); B : in bit_vector(N-1 downto 0); cin : in bit; Sum : out bit_vector(N-1 downto 0); Cout : out bit ); end entity adder ; entity test_bench is -- typical top level, simulatable, entity end entity test_bench; entity Latch is port ( Din: in Word; Dout: out Word; Load: in Bit; Clk: in Bit); constant Setup: Time := 12 ns;

constant PulseWidth: Time := 50 ns;

use WORK.TimingMonitors.all

begin


ECADLAB(VHDL) 299

assert Clk='1' or Clk'Delayed'Stable(PulseWidth);

CheckTiming(Setup, Din, Load, Clk); -- passive concurrent procedure

end entity Latch;

The allowed declarations are:

subprogram declaration

subprogram body

type declaration

subtype declaration

constant, object declaration

signal, object declaration

variable, object declaration - shared

file, object declaration

alias declaration

attribute declaration

attribute specification

disconnection specification

use clause

group template declaration

group declaration

The allowed statements are:

concurrent assertion statements

passive concurrent procedure call

passive process statement

Architecture Used to implement a design entity. There may be more than one architecture for a design entity. Typical architectures fall into classes such as functional simulation or detailed logic implementation and may be structural, functional(dataflow) or behavioral.

ECADLAB(VHDL) 300

architecture identifier of entity_name is [ declarations , see allowed list below ] begin -- optional [ statements , see allowed list below ] end architecture identifier ; architecture circuits of add4c is signal c : std_logic_vector(3 downto 0); component fadd -- duplicates entity port port(a : in std_logic; b : in std_logic; cin : in std_logic; s : out std_logic; cout : out std_logic); end component fadd; begin -- circuits of add4c a0: fadd port map(a(0), b(0), cin , sum(0), c(0)); a1: fadd port map(a(1), b(1), c(0), sum(1), c(1)); a2: fadd port map(a(2), b(2), c(1), sum(2), c(2)); a3: fadd port map(a(3), b(3), c(2), sum(3), c(3)); cout <= (a(3) and b(3)) or ((a(3) or b(3)) and ((a(2) and b(2)) or ((a(2) or b(2)) and ((a(1) and b(1)) or ((a(1) or b(1)) and ((a(0) and b(0)) or ((a(0) or b(0)) and cin))))))) after 1 ns; end architecture circuits; -- of add4c The allowed declarations are: subprogram declaration subprogram body type declaration subtype declaration constant, object declaration signal, object declaration variable, object declaration – shared file, object declaration alias declaration component declaration attribute declaration attribute specification disconnection specification use clause group template declaration group declaration The allowed statements are: concurrent statements

Configuration Used to bind component instances to design entities and collect architectures to make, typically, a simulatable test bench. One configuration could create a functional simulation while another configuration could create the complete detailed logic design. With an appropriate test bench the results of the two configurations can be compared.Note that significant nesting depth can occur on hierarchal designs. There is a capability to bind


ECADLAB(VHDL) 301

various architectures with instances of components in the hierarchy. To avoid nesting depth use a configuration for each architecture level and a configuration of configurations. Most VHDL compilation/simulation systems allow the top level configuration name to be elaborated and simulated. configuration identifier of entity_name is [ declarations , see allowed list below ] [ block configuration , see allowed list below ] end architecture identifier ; -- entities and architecture circuits for fadd, add4c and add32 not shown entity add32_test is -- test bench end add32_test; architecture circuits of add32_test is -- details implementing test bench deleted end architecture circuits; -- of add32_test configuration add32_test_config of add32_test is for circuits -- of add32_test for all: add32 use entity WORK.add32(circuits); for circuits -- of add32 for all: add4c use entity WORK.add4c(circuits); for circuits -- of add4c for all: fadd use entity WORK.fadd(circuits); end for; end for; end for; end for; end for; end for; end configuration add32_test_config; Note the architecture name in parenthesis following the entity name. Or an equivalent configuration of configurations: configuration add32_test_config of add32_test is for circuits -- of add32_test for all: add32 use configuration WORK.add32_config; end for; end for; end configuration add32_test_config; The allowed declarations are: attribute specification use clause group declaration The allowed block configurations are: for component_instance_name : component_name -- use clause end for; for all : component_name -- use clause


ECADLAB(VHDL) 302

end for; use clauses are of the form: use entity library_name.entity_name .configuration_name

Package Declaration Used to declare types, shared variables, subprograms, etc. package identifier is [declarations, see allowed list below ] end package identifier ; The example is included in the next section, Package Body. The allowed declarations are: subprogram declaration type declaration subtype declaration constant, object declaration signal, object declaration variable, object declaration – shared file, object declaration alias declaration component declaration attribute declaration attribute specification use clause group template declaration group declaration Declarations not allowed include: subprogram body A package body is unnecessary if no subprograms or

deferred constants are declared in the package declaration.

Package Body Used to implement the subprograms declared in the package declaration.

package body identifier is

[ declarations, see allowed list below ]

end package body identifier ;

package my_pkg is -- sample package declaration

type small is range 0 to 4096;

procedure s_inc(A : inout small);

function s_dec(B : small) return small;

end package my_pkg;

package body my_pkg is -- corresponding package body

procedure s_inc(A : inout small) is

begin

A := A+1;

end procedure s_inc;

function s_dec(B : small) return small is

begin


ECADLAB(VHDL) 303

return B-1;

end function s_dec;

end package body my_pkg;

The allowed declarations are:


subprogram body

type declaration

subtype declaration


variable, object declaration – shared


alias declaration

use clause


group declaration

Declarations not allowed include:


Subprograms

There are two kinds of subprograms: procedures and functions.Both procedures and functions written in VHDL must havea body and may have declarations.Procedures perform sequential computations and return valuesin global objects or by storing values into formal parameters.Functions perform sequential computations and return a value as the value of the function. Functions do not change their formal parameters. Subprograms may exist as just a procedure body or a function body. Subprograms may also have a procedure declarations or a function declaration. When subprograms are provided in a package, the subprogram declaration is placed in the package declaration and the subprogram body is placed in the package body.

Procedure Declaration

Used to declare the calling interface to a procedure.

procedure identifier [ ( formal parameter list ) ] ;

procedure print_header;

procedure build (A : in constant integer;

B : inout signal bit vector;

C : out variable real;

D: file);

Formal parameters are separated by semicolons in the formal parameter list. Each normal parameter is essentially a declaration of an object that is local to the procedure. The type definitions used in formal parameters must be visible at the place where the procedure is being declared. No semicolon follows the last formal parameter inside the


ECADLAB(VHDL) 304

parenthesis. Formal parameters may be constants, variables, signals or files. The default is variable. Formal parameters may have modes in, inout and out Files do not have a mode. The default is in If no type is given and a mode of in is used, constant is the default. The equivalent default declaration of "build" is

procedure build ( A : in integer;

B : inout signal bit_vector;

C : out real;

D : file ) ;

Procedure Body

Used to define the implementation of the procedure.

procedure identifier [ ( formal parameter list ) ] is


begin

sequential statement(s)

end procedure identifier ;

procedure print_header is

use STD.textio.all;

variable my_line : line;

begin

write ( my_line, string'("A B C"));

writeline ( output, my_line );

end procedure print_header ;

The procedure body formal parameter list is defined above in Procedure Declaration. When a procedure declaration is used then the corresponding procedure body should have exactly the same formal parameter list. The allowed declarations are:


subprogram body

type declaration

subtype declaration


ECADLAB(VHDL) 305


variable, object declaration


alias declaration

use clause


group declaration



Function Declaration

Used to declare the calling and return interface to a function.

function identifier [ ( formal parameter list ) ] return a_type ;

function random return float ;

function is_even ( A : integer) return boolean ;

Formal parameters are separated by semicolons in the formal parameter list. Each normal parameter is essentially a declaration of an object that is local to the function. The type definitions used in formal parameters must be visible at the place where the function is being declared. No semicolon follows the last formal parameter inside the parenthesis. Formal parameters may be constants, signals or files. The default is constant. Formal parameters have the mode in. Files do not have a mode. Note that inout and out are not allowed for functions. The default is in. The reserved word function may be preceded by nothing, implying pure, pure or impure.A pure function must not contain a reference to a file object,slice, subelement, shared variable or signal with attributessuch as 'delayed, 'stable, 'quiet, 'transaction and must notbe a parent of an impure function.

Function Body

Used to define the implementation of the function.

function identifier [ ( formal parameter list ) ]

return a_type is


begin


ECADLAB(VHDL) 306

sequential statement(s)

return some_value; -- of type a_type

end function identifier ;

function random return float is

variable X : float;

begin

-- compute X

return X;

end function random ;

The function body formal parameter list is defined above in Function Declaration. When a function declaration is used then the corresponding function body should have exactly the same formal parameter list. The allowed declarations are:


subprogram body

type declaration

subtype declaration




alias declaration

use clause


group declaration




ECADLAB(VHDL) 307

Context Clause

Used to name a library and make library units visible to the design unit that immediately follows.

library library_name ;

use library_name.unit_name.all ;

library STD ;

use STD.textio.all;

library ieee ;


use ieee.std_logic_textio.all;

use ieee.std_logic_arith.all;

use ieee.numeric_std.all;

use ieee.numeric_bit.all;

use WORK.my_pkg.s_inc;

-- select one item from package Note that the .all makes everything visible. It is optional and when not used the prefix such as ieee.std_logic_1164. must be used on every reference to an item in the library unit. Specific items in the library unit may be listed in place of .all . The libraries STD and WORK do not need a library specification on most systems. library ieee or equivalent library IEEE is needed on most systems.

Order of Analysis, Compilation

Every design unit must be analyzed, compiled, before it can be used by another design

unit. The result of the analysis or compilation results in an analyzed design in a library.

The analyzed design goes into the default library WORK unless otherwise specified. An

entity must be analyzed, compiled, before its corresponding architectures or

configurations.

A package declaration must be analyzed, compiled, before its corresponding package

body. A package declaration must be analyzed, compiled, before it canbe referenced in a

context clause. For example: Analyze, compile

package my_package is -- declarations

end package my_package; then analyze, compile

ECADLAB(VHDL) 308

library WORK; -- this line usually not needed

use WORK.my_package.all

entity my_entity is

-- entity stuff

end entity my_entity;

These statements are for use in Processes, Procedures and Functions. The signal

assignment statement has unique properties when used sequentially.

wait statement

Cause execution of sequential statements to wait.

[ label: ] wait [ sensitivity clause ] [ condition clause ] ;

wait for 10 ns; -- timeout clause, specific time delay.

wait until clk='1'; -- condition clause, Boolean condition

wait until A>B and S1 or S2; -- condition clause, Boolean condition

wait on sig1, sig2; -- sensitivity clause, any event on any

� signal terminates wait

assertion statement

Used for internal consistency check or error message generation.

label: ] assert boolean_condition [ report string ] [ severity name ] ;

assert a=(b or c);

assert j<i report "internal error, tell someone";

assert clk='1' report "clock not up" severity WARNING;

predefined severity names are: NOTE, WARNING, ERROR, FAILURE

default severity for assert is ERROR

ECADLAB(VHDL) 309

report statement

Used to output messages.

[ label: ] report string [ severity name ] ;

report "finished pass1"; -- default severity name is NOTE

report "Inconsistent data." severity FAILURE;

signal assignment statement The signal assignment statement is typically considered a concurrent statement rather than a sequential statement. It can be used as a sequential statement but has the side effect of obeying the general rules for when the target actually gets updated. In particular, a signal can not be declared within a process or subprogram but must be declared is some other appropriate scope. Thus the target is updated in the scope where the target is declared when the sequential code reaches its end or encounters a 'wait' or other event that triggers the update. [ label: ] target <= [ delay_mechanism ] waveform ; delay_mechanism transport reject time_expression inertial waveform waveform_element [, waveform_element] unaffected waveform_element value_expression [ after time_expression ] null [ after time_expression ] sig1 <= sig2; Sig <= Sa and Sb or Sc nand Sd nor Se xor Sf xnor Sg; sig1 <= sig2 after 10 ns; clk <= '1' , '0' after TimePeriod/2 ; sig3 <= transport sig4 after 3 ns; sig4 <= reject 2 ns sig5 after 3 ns; -- increasing time order sig6 <= inertial '1' after 2 ns, '0' after 3 ns , '1' after 7 ns; Note: omitting [ after time_expression ] is equivalent

to after 0 fs;


ECADLAB(VHDL) 310

variable assignment statement

Assign the value of an expression to a target variable.

[ label: ] target := expression ;

A := -B + C * D / E mod F rem G abs H;

Sig := Sa and Sb or Sc nand Sd nor Se xor Sf xnor Sg;

procedure call statement

Call a procedure.

[ label: ] procedure-name [ ( actual parameters ) ] ;

do_it; -- no actual parameters

compute(stuff, A=>a, B=>c+d); -- positional association first,

-- then named association of

-- formal parameters to actual parameters

if statement

Conditional structure.

[ label: ] if condition1 then

sequence-of-statements

elsif condition2 then \_ optional

sequence-of-statements /

elsif condition3 then \_ optional


...

else \_ optional


end if [ label ] ;

if a=b then

c:=a;

ECADLAB(VHDL) 311

elsif b<c then

d:=b;

b:=c;

else

do_it;

end if;

case statement

Execute one specific case of an expression equal to a choice. The choices must be

constants of the same discrete type as the expression.

[ label: ] case expression is

when choice1 =>


when choice2 => \_ optional


when others => \_ optional if all choices covered


end case [ label ] ;

case my_val is

when 1 =>

a:=b;

when 3 =>

c:=d;

do_it;

when others =>

null;

end case;

loop statement

Three kinds of iteration statements.

[ label: ] loop

sequence-of-statements -- use exit statement to get out

end loop [ label ] ; [ label: ] for variable in range loop


end loop [ label ] ;

[ label: ] while condition loop


end loop [ label ] ;

loop

input_something;

exit when end_file;

end loop;

for I in 1 to 10 loop

ECADLAB(VHDL) 312

AA(I) := 0; end loop;

while not end_file loop

input_something;

end loop; all kinds of the loops may contain the 'next' and 'exit' statements.

next statement

A statement that may be used in a loop to cause the next iteration.

[ label: ] next [ label2 ] [ when condition ] ;

next;

next outer_loop;

next when A>B;

next this_loop when C=D or done; -- done is a Boolean variable

exit statement A statement that may be used in a loop to immediately exit the loop.

[ label: ] exit [ label2 ] [ when condition ] ;

exit;

exit outer_loop;

exit when A>B;

exit this_loop when C=D or done; -- done is a Boolean variable

return statement

Required statement in a function, optional in a procedure.

[ label: ] return [ expression ] ;

return; -- from somewhere in a procedure

return a+b; -- returned value in a function

null statement

Used when a statement is needed but there is nothing to do.

[ label: ] null ;

null;

VHDL Concurrent Statements

These statements are for use in Architectures.

signal temp: std_logic;

begin

temp <= A xor B after delay;

ECADLAB(VHDL) 313

C <= temp nor B;

end block maybe;

process statement

Used to do have sequential statements be a part of concurrent processing.

label : process [ ( sensitivity_list ) ] [ is ]

[ process_declarative_items ]

begin

sequential statements

end process [ label ] ;

input and output are defined a type 'word' signals

reg_32: process(clk, clear)

Begin

if clear='1' then

output <= (others=>'0');

elsif clk='1' then

output <= input after 250 ps;

end if;

end process reg_32;

-- assumes use IEEE.std_logic_textio.all

printout: process(clk) -- used to show state when clock raises

variable my_line : LINE; -- not part of working circuit

Begin

if clk='1' then

ECADLAB(VHDL) 314

write(my_line, string'("at clock "));

write(my_line, counter);

write(my_line, string'(" PC="));

write(my_line, IF_PC);

writeline(output, my_line);

counter <= counter+1;

end if;

end process printout;

process_declarative_items are any of:


subprogram body

type declaration

subtype declaration




alias declaration

attribute declaration

attribute specification

use clause


group declaration

BUT NOT signal_declaration, all signals must be declared outside the

ECADLAB(VHDL) 315

rocess.

sig1 <= sig2 and sig3; -- considered here as a sequential statement

-- sig1 is set outside the process upon exit or wait

A process may be designated as postponed in which case it starts in the

ame simulation cycle as an equivalent non postponed process, yet starts

fter all other non postponed processes have suspended in that simulation

ycle. concurrent procedure call statement A sequential procedure call

tatement may be used and its behavior is that of an equivalent process.

[ label : ] [ postponed ] procedure name [ ( actual_parameters ) ] ;

trigger_some_event ;

Check_Timing(min_time, max_time, clk, sig_to_test);

Note that a procedure can be defined in a library package and then used

any places. A process can not be similarly defined in a package and may

ave to be physically copied. A process has some additional capability not

vailable in a concurrent procedure.

concurrent assertion statement

A sequential assertion statement may be used and its behavior is that of

n equivalent process.

[ label : ] [ postponed ] assertion_statement ;

concurrent signal assignment statement

A sequential signal assignment statement is also a concurrent signal

ssignment statement. Additional control is provided by the use of

ostponed and guarded.

ECADLAB(VHDL) 316

[ label : ] sequential signal assignment statement

[ label : ] [ postponed ] conditional_signal_assignment_statement ;

[ label : ] [ postponed ] selected_signal_assignment_statement ;

The optional guarded causes the statement to be executed when the

uarded signal changes from False to True.

conditional signal assignment statement

A conditional assignment statement is also a concurrent signal

ssignment statement.

target <= waveform when choice; -- choice is a boolean expression

target <= waveform when choice else waveform;

sig <= a_sig when count>7;

sig2 <= not a_sig after 1 ns when ctl='1' else b_sig;

"waveform" for this statement seems to include [ delay_mechanism

selected signal assignment statement

A selected assignment statement is also a concurrent signalassignment statement. with expression select

target <= waveform when choice [, waveform when choice ] ;

with count/2 select my_ctrl <=

'1' when 1, -- count/2 = 1 for this choice

'0' when 2,

'X' when others;

component instantiation statement Get a specific architecture-entity instantiated component. part_name: entity library_name.entity_name(architecture_name)


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port map ( actual arguments ) ; optional (architecture_name) part_name: component_name port map ( actual arguments ) ; Given entity gate is port (in1 : in std_logic ; in2 : in std_logic ; out1 : out std_logic) ; end entity gate; architecture circuit of gate is ... architecture behavior of gate is ... A101: entity WORK.gate(circuit) port map ( in1 => a, in2 => b, out1 => c ); -- when gate has only one architecture A102: entity WORK.gate port map ( in1 => a, in2 => b, out1 => c ); -- when order of actual arguments is used A103: entity WORK.gate port map ( a, b, c ); Given an entity entity add_32 is -- could have several architectures port (a : in std_logic_vector (31 downto 0); b : in std_logic_vector (31 downto 0); cin : in std_logic; sum : out std_logic_vector (31 downto 0); cout : out std_logic); end entity add_32; Create a simple component interface component add_32 -- use same port as entity port (a : in std_logic_vector (31 downto 0); b : in std_logic_vector (31 downto 0); cin : in std_logic; sum : out std_logic_vector (31 downto 0); cout : out std_logic); end component add_32; Instantiate the component 'add_32' to part name 'PC_incr' PC_incr : add_32 port map (PC, four, zero, PC_next, nc1); Create a component interface, changing name and renaming arguments component adder -- can have any name but same types in port port (in1 : in std_logic_vector (31 downto 0); in2 : in std_logic_vector (31 downto 0); cin : in std_logic;

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sum : out std_logic_vector (31 downto 0);

cout : out std_logic);

end component adder;

Instantiate the component 'adder' to part name 'PC_incr'

PC_incr : adder -- configuration may associate a specific architecture

port map (in1 => PC,

in2 => four,

cin => zero,

sum => PC_next,

cout => nc1);

generate statement Make copies of concurrent statements label: for variable in range generate -- label required block declarative items \__ optional begin / concurrent statements -- using variable end generate label ; label: if condition generate -- label required block declarative items \__ optional begin / concurrent statements end generate label ; band : for I in 1 to 10 generate b2 : for J in 1 to 11 generate

block statement Used to group concurrent statements, possibly hierarchically. label : block [ ( guard expression ) ] [ is ] [ generic clause [ generic map aspect ; ] ] [ port clause [ port map aspect ; ] ] [ block declarative items ] begin concurrent statements end block [ label ] ; clump : block begin A <= B or C; D <= B and not C; end block clump ; maybe : block ( B'stable(5 ns) ) is

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port (A, B, C : inout std_logic ); port map ( A => S1, B => S2, C => outp ); constant delay: time := 2 ns;

VHDL Resolution and Signatures Resolution Functions A resolution function defines how values from multiple sources, multiple drivers, are resolved into a single value. A type may be defined to have a resolution function. Every signal object of this type uses the resolution function when there are multiple drivers. A signal may be defined to use a specific resolution function. This signal uses the resolution function when there are multiple drivers. A resolution function must be a pure function that has a single input parameter of class constant that is a one dimensional unconstrained array of the type of the resolved signal. An example is from the package std_logic_1164 : type std_ulogic is ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1

'-' -- Don't care); type std_ulogic_vector is array ( natural range <> ) of std_ulogic; resolution functionfunction resolved ( s : std_ulogic_vector ) return std_ulogic; variable result : std_ulogic := 'Z'; -- weakest state default Begin -- the test for a single driver is essential otherwise the -- loop would return 'X' for a single driver of '-' and that -- would conflict with the value of a single driver unresolved -- signal. if s'length = 1 then return s(s'low); else for i in s'range loop result := resolution_table(result, s(i)); end loop; end if; return result; end resolved; constant resolution_table : stdlogic_table := ( -- -------------------------------------------------------- -- | U X 0 1 Z W L H - | | - --------------------------------------------------------- ( 'U', 'U', 'U', 'U', U', 'U', 'U', 'U', 'U' ), -- | U | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 | ( 'U', 'X', 'X', '1', '1', '1', '1', '1', X' ), -- | 1 | ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z | ( 'U', 'X', 0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W | ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', X' ), -- | L | ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - | ); subtype std_logic is resolved std_ulogic;

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type std_logic_vector is array ( natural range <>) of std_logic; signal xyz : std_logic_vector(0 to 3); xyz <= -- some expression ; xyz <= -- some other expression ; -- a second driver -- each bit of xyz comes from function "resolved" Signatures A signature distinguishes between overloaded subprograms and enumeration literals based on their parameter and result type profiles. A signature may be used in an attribute name, entity designator, or alias declaration. The syntax of the signature is [ type_mark, type_mark, ... , type_mark return type_mark ] A signature used in an alias statement to give a shorthand to a textio procedure is: alias swrite is write [line, string, side, width] ; allowing swrite(output, "some text"); in place of write(output, string'("some text")); The "[line, string, side, width]" is the signature to choose which of the overloaded 'write' procedures to alias to 'swrite'. No return is used for procedures. The type marks are the parameter types in their defined order. The square brackets at beginning and end are part of the signature.The signature is used immediately after the subprogram or enumeration literal name.

VHDL Reserved Words abs operator, absolute value of right operand. No () needed. access used to define an access type, pointer after specifies a time after NOW alias create another name for an existing identifier all dereferences what precedes the .all and operator, logical "and" of left and right operands architecture a secondary design unit array used to define an array, vector or matrix assert used to have a program check on itself attribute used to declare attribute functions begin start of a begin end pair block start of a block structure body designates a procedure body rather than declaration buffer a mode of a signal, holds a value bus a mode of a signal, can have multiple drivers case part of a case statement component starts the definition of a component configuration a primary design unit constant declares an identifier to be read only disconnect signal driver condition downto middle of a range 31 downto 0 else part of "if" statement, if cond then ... else ... end if; elsif part of "if" statement, if cond then ... elsif cond ... end part of many statements, may be followed by word and id entity a primary design unit exit sequential statement, used in loops file used to declare a file type for start of a for type loop statement function starts declaration and body of a function


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generate make copies, possibly using a parameter generic introduces generic part of a declaration group collection of types that can get an attribute guarded causes a wait until a signal changes from False to True if used in "if" statements impure an impure function is assumed to have side effects in indicates a parameter in only input, not changed inertial signal characteristic, holds a value inout indicates a parameter is used and computed in and out is used as a connective in various statements label used in attribute statement as entity specification library context clause, designates a simple library name linkage a mode for a port, used like buffer and inout literal used in attribute statement as entity specification loop sequential statement, loop ... end loop; map used to map actual parameters, as in port map mod operator, left operand modulo right operand nand operator, "nand" of left and right operands new allocates memory and returns access pointer next sequential statement, used in loops nor operator, "nor" of left and right operands not operator, complement of right operand null sequential statement and a value of used in type declarations, of Real ; on used as a connective in various statements open initial file characteristic or operator, logical "or" of left and right operands others fill in missing, possibly all, data out indicates a parameter is computed and output package a design unit, also package body port interface definition, also port map postponed make process wait for all non postponed process to suspend procedure typical programming procedure process sequential or concurrent code to be executed pure a pure function may not have side effects range used in type definitions, range 1 to 10; record used to define a new record type register signal parameter modifier reject clause in delay mechanism, followed be a time rem operator, remainder of left operand divided by right op report statement and clause in assert statement, string output return statement in procedure or function rol operator, left operand rotated left by right operand ror operator, left operand rotated right by right operand select used in selected signal assignment statement severity used in assertion and reporting, followed by a severity signal declaration that an object is a signal shared used to declare shared objects sla operator, left operand shifted left arithmetic by right op sll operator, left operand shifted left logical by right op sra operator, left operand shifted right arithmetic by right


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srl operator, left operand shifted right logical by right op subtype declaration to restrict an existing type then part of if condition then ... to middle of a range 1 to 10 transport signal characteristic type declaration to create a new type unaffected used in signal waveform units used to define new types of units until used in wait statement use make a package available to this design unit variable declaration that an object is a variable wait sequential statement, also used in case statement when used for choices in case and other statements while kind of loop statement with used in selected signal assignment statement xnor operator, exclusive "nor" of left and right operands xor operator, exclusive "or" of left and right operands Standard VHDL Packages VHDL standard packages and types The following packages should be installed along with the VHDL compiler and simulator. The packages that you need, except for "standard", must be specifically accessed by each of your source files with statements such as: library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_textio.all; use IEEE.std_logic_arith.all; use IEEE.numeric_bit.all; use IEEE.numeric_std.all; use IEEE.std_logic_signed.all; use IEEE.std_logic_unsigned.all; use IEEE.math_real.all; use IEEE.math_complex.all; library STD; use STD.textio; A version of these packages, declaration and body, are in this directory The package standard is predefined in the compiler. Types defined include: bit bit_vector typical signals integer natural positive typical variables boolean string character typical variables real time delay_length typical variables Click on standard to see the functions defined Note: This package must be provided with compiler, do not use this one. The package textio provides user input/output Types defined include: line text side width Functions defined include: readline read writeline write endline Click on textio to see how to call the functions The package std_logic_1164 provides enhanced signal types Types defined include: std_ulogic std_ulogic_vector std_logic std_logic_vector Click on std_logic_1164 to see available functions


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The package std_logic_textio provides input/output for 1164 types Functions defined include: readline read writeline write endline Click on std_logic_textio to see how to call the functions sThe package std_logic_arith provides numerical computation This package name unfortunately seams to have several definitions: std_logic_arith_syn.vhd defines types signed and unsigned and has arithmetic functions that operate on signal types signed and unsigned and std_logic_vector and std_ulogic_vector, but adding A to B of std_logic_vector type, needs unsigned(A) + unsigned(B). Click on std_logic_arith_syn to see the functions defined std_logic_arith_ex.vhd has arithmetic functions that operate on signal types std_logic_vector and std_ulogic_vector Click on std_logic_arith_ex to see the functions defined The package numeric_bit provides numerical computation Types defined include: unsigned signed arrays of type bit for signals Click on numeric_bit to see the functions defined The package numeric_std provides numerical computation Types defined include: unsigned signed arrays of type std_logic for signals Click on numeric_std to see the functions defined The package std_logic_signed provides signed numerical computation on type std_logic_vector Click on std_logic_signed to see the functions defined The package std_logic_unsigned provides unsigned numerical computation on type std_logic_vector Click on std_logic_unsigned to see the functions defined The package math_real provides numerical computation on type real Click on math_real to see the functions defined This declaration and body are in mathpack The package math_complex provides numerical computation Types defined include: complex, complex_vector, complex_polar Click on math_complex to see the functions defined This declaration and body are in mathpack


ECADLAB(VHDL) 324

REFERENCES: 1. VHDL Primer by J.Bhasker, Pearson Education 2. Digital Design by Mano, Eastern Economy Edition 3. Digital System Design Using VHDL by Charles Roth, Thomson Edition 4. VHDL by Douglas Perry, Tata Mc-Graw Hill Edition

Websites: www.datasheets4u.com www.alldatasheets.com www.xilinx.com www.altera.com www.mentorgraphics.com

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