VHDL for Designers

Stefan Sjoholm

ABB Industrial Systems, Sweden

and

Lennart Lindh Malardalens University, Sweden

PRENTICE HALL London New York Toronto Sydney Tokyo Singapore Madrid Mexico City Munich Paris

Contents

Preface xiii

1. Introduction and overview 1 1.1. Why use VHDL 3 1.2. Development flow 4 1.3. History 6 1.4. Synthesis , 11 1.5. Exercises 14

2. Introduction to VHDL 15 2.1. VHDL language abstractions 15

2.1.1. Simulation 19 2.1.2. Other languages for describing electronics 20

2.2. Design hierarchies - reducing complexity 21 2.3. VHDL component 22

2.3.1. Entity and architecture 23 2.4. Exercises 28 2.5. References 29

3. Concurrent VHDL 30 3.1. Signal assignment 30 3.2. Transport and inertial delay 32 3.3. Concurrency 33 3.4. Delta time 34 3.5. When Statement 36 3.6. With Statement 38 3.7. Example of a behavioural model of a multiplexor 39 3.8. Generics 39 3.9. The assert command - error management in VHDL 40 3.10. Behaviour and dataflow 43 3.11. Objects, class and type 43

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3.11.1. Datatypes 44 3.11.2. Synthesizable data types 51

3.12. Vector assignment 53 3.12.1. Bit string literals 53 3.12.2. Slice of array 56 3.12.3. Concatenation 58 3.12.4. Aggregate 59 3.12.5. Qualifier 60

3.13. Advanced data types 60 3.13.1. Subtypes 60 3.13.2. Multidimensional array 61 3.13.3. Records 63

3.14. Alias 64 3.15. Relational Operators 64 3.16. Arithmetic Operators 65 3.17. Initvalue 66 3.18. Exercises 68

4. Sequential VHDL 71 4.1. Concurrent and sequential data processing 71 4.2. Signal and variable assignment 72 4.3. Process statement 77

4.3.1. Combinational processes 79 4.3.2. Clocked processes 81

4.4. If statement 87 4.5. Case statement 89 4.6. Multiple assignment 94 4.7. Null statement 95 4.8. Wait statement 96 4.9. Loop statement 99

4.9.1. Forloop 100 4.9.2. Whileloop 101

4.10. Postponed process 102 4.11. Predefined signal attributes 103 4.12. Different clock descriptions in clocked processes 105 4.13. Asynchronous and synchronous reset 107

4.13.1. Asynchronous reset 107 4.13.2. Synchronous reset 109

4.14. Latches 110 4.15. Exercises 111

5. Library, package and subprograms 115 5.1. Libraries 115 5.2. Packages 116 5.3. Subprograms 119

Contents ix

5.3.1. Procedures 120 5.3.2. Functions 122 5.3.3. Resolution functions 126

5.4. Overloading 128 5.5. Type conversion 131 5.6. Shift Operators 134 5.7. Exercises 136

6. Structural VHDL 138 6.1. Component declaration 140 6.2. Component specification 142 6.3. Port map command 143

6.3.1. Unconnected Outputs 144 6.3.2. Unconnected inputs 145

6.4. Generic map command 147 6.5. Generate command 149 6.6. Configuration 150 6.7. Direct instantiation (VHDL-93) 154 6.8. Components in package 154 6.9. Exercises 156

7. RAM and ROM 158 7.1. ROM 158

7.1.1. Using an array constant 158 7.1.2. Instancing a technology-specific ROM 160 7.1.3. Summary 161

7.2. RAM 161 7.2.1. Using registers 161 7.2.2. Instancing RAM 162

7.3. Exercises 162

8. Testbench 163 8.1. Different levels of testbench 168 8.2. Pullup/down 178 8.3. Several components in the same testbench 180 8.4. Waveform generators 181 8.5. TextIO 188 8.6. Exercises 191

9. State machines 193 9.1. Moore machine 198 9.2. Mealy machine 204 9.3. Mealy and Moore variants 209 9.4. Output=state machine 209 9.5. Moore machine with clocked Outputs 211

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9.6. Mealy machine with clocked Outputs 213 9.7. State coding 215 9.8. Residual states 216 9.9. How to write an optimum State machine in VHDL 222 9.10. Asynchronous State machines 229 9.11. Exercises 232

10. RTL synthesis 237 10.1. Optimization and mapping 240 10.2. Constraints 244

10.2.1. Defining clock inputs 245 10.2.2. Defining input and Output delay 246 10.2.3. Falsepath 248 10.2.4. Area constraints 249 10.2.5. Design constraints 249

10.3. Best case optimization 250 10.4. What to do if the synthesis tool does not achieve the

optimization goals 252 10.5. Summary 258

11. Design methodology 260 11.1. Top-downflow 263 11.2. Verification 265

11.2.1. Summary of the different Simulation alternatives.... 269 11.2.2. Simulation speed 270 11.2.3. Formal verification 273 11.2.4. Recommendations for verification 274

11.3. How to write RTL VHDL code for synthesis 275 11.4. FPGA 284

12. Test methodology 287 12.1. Scan methodology 289 12.2. Füll scan and partial scan 295 12.3. ATPG design rules 296

12.3.1. How to write testable VHDL code 298 12.4. Boundary scan 305 12.5. Supplementary test vectors 308

13. Rapid prototyping 310 13.1. Introduction 310

13.1.1. Rapid prototyping 310 13.2. Real-time kernel - a brief description 311 13.3. The development system 312 13.4. Development phases 313 13.5. Further reading 317

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14. Common design errors in VHDL and how to avoid them 318 14.1. Signals and variables 318 14.2. Logic synthesis and sensitivity lists 320 14.3. Buffers and internal dummy signals 321 14.4. Declaring vectors with downto or to 325 14.5. Incompletely defined combinational processes 325

15. Design examples and design tips 327 15.1. Adders 328

15.1.1. One-bit adder with carry in 328 15.1.2. Eight-bit adder with carry in 329 15.1.3. Generic adder with carry in 329 15.1.4. Four-bit vector adder/subtractor 330

15.2. Vector multiplication 331 15.3. Resource sharing 332

15.3.1. Example when resource sharing of an adder is possible 332

15.3.2. Example when resource sharing of an adder is not possible 333

15.4. Comparators 335 15.5. Multiplexors and decoders 336

15.5.1. Two-to-one multiplexor 336 15.5.2. Eight-to-one multiplexor 337 15.5.3. Three-to-eight decoder 338

15.6. Register 339 15.6.1. Flip-flop with asynchronous reset 339 15.6.2. Flip-flop with synchronous reset 340 15.6.3. Flip-flop with asynchronous reset and set 341 15.6.4. Eight-bit register with enable and asynchronous

reset 342 15.7. Edge-controlled pulse generator 343 15.8. Counters 345

15.8.1. Three-bit counter with enable and carry out 345 15.8.2. Three-bit up/down counter 346 15.8.3. Parallel loadable generic up/down counter 348

15.9. Shift register 349 15.9.1. Four-bit shift register with serial input data and

parallel output data 349 15.9.2. Four-bit shift register with parallel load and serial

output 350 15.10. Filters 351

15.10.1. Four-input digital majority-voting filter 351 15.10.2. Four-input digital addition filter 353

15.11. Frequency dividers 355

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16. Development tools 357 16.1. Synopsys 357

16.1.1. VHDL Compiler and Design Analyzer 358 16.1.2. Design Ware 359 16.1.3. Design Compiler 362 16.1.4. ATPG tools 363 16.1.5. FPGA Compiler 363 16.1.6. VHDL Simulator 365

17. Behavioural synthesis 367 17.1. Introduction 367

17.1.1. Terminology 367 17.2. Handshaking 369

17.2.1. One-way handshake protocol 370 17.2.2. Two-way handshake protocol 371

17.3. Example of behavioural/RTL synthesis - FIR filter 372

18. Laboratories 388 18.1. "Hands on" for ViewLogic 388 18.2. "Hands on" for Synopsys synthesis tool and Mentor Graphics

VHDL Simulator 393 18.3. Script for Synopsys users 395 18.4. Laboratory assignments 395

19. Answers 411 19.1. Solutions to selected exercises 411 19.2. Solutions to the laboratory assignments - Synopsys and

Autologic2 422 19.3. Solutions to the laboratory assignments - ViewLogic 436

Appendix A. VHDL syntax 447 A.l. Library units 447 A.2. Declarations 449 A.3. Sequential Statements 451 A.4. Concurrent Statements 455

Appendix B. VHDL-package 458 B.l. Std-package 458 B.2. IEEE-package 459

B.2.1. Std_logic_1164 459 B.2.2. Std_logic_unsigned 463 B.2.3. Std_logic_signed 465

Appendix C. Keywords in VHDL-87 467 Appendix D. Additional keywords in VHDL-93 468

Index. 469