vhdl code for half adder
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Transcript of vhdl code for half adder
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7/23/2019 vhdl code for half adder
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Aim of The Experiment:
To design and implement half adder circuit using VHDL
Platform Required:
Windows 7 Operating System
Software Required:
Xilinx ISE Design Suite 14.7
Theory:
The half adder circuit is a digital circuit consisting of logic gates that adds two single bit
inputs and produces a single bit sum and carry. A half adder circuit having inputs A and B
produces a sum S and a carry C given by,
S = AB
C = A.B
Truth Table for Half Adder
Input Output
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity halfadder is
Port ( A,B : in STD_LOGIC;S,C : out STD_LOGIC);
end halfadder;
architecture Behavioral of halfadder is
begin
S
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Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY halfadder_tb ISEND halfadder_tb;
ARCHITECTURE behavior OF halfadder_tb IS
COMPONENT halfadder
PORT(
A : IN std_logic;
B : IN std_logic;
S : OUT std_logic;
C : OUT std_logic
);
END COMPONENT;
signal A : std_logic := '0';
signal B : std_logic := '0';
signal S : std_logic;
signal C : std_logic;
BEGIN
uut: halfadder PORT MAP (
A => A,
B => B,
S => S,
C => C
);
stim_proc: process
begin
a
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7/23/2019 vhdl code for half adder
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RTL Schematic Diagra
Test bench Waveform:
Conclusion:
Thus we have implemented
several inputs.
&
:
alf adder circuit in VHDL and studied its
peration by giving