System Design/DSD... · Web viewAssignment VHDL Index 4-bit Full Adder 4-bit Counter Decoder 2 to 4...

Assignment VHDL

Indexa. 4-bit Full Adderb. 4-bit Counterc. Decoder 2 to 4 Lined. Decoder 3 to 8 Linee. Half Adderf. Half Subtractorg. Encoderh. Flip-Flopi. Multiplexerj. DeMultiplexerk. Parity Checkerl. JK Flip-Flopm. BCD Countern. Any Sequenceo. Simulation:- Test bench waveform; test bench

1. 4-bit Full Adder

Library IEEE;

Use ieee.std_logic_1164.all;

Use ieee.std_logic_arith.all;

Use ieee.std_logic_unsigned.all;

Entity FA _4bit is

PORT (Signal a,b : in std_logic_vector(3 downto 0);

Signal cin : in std_logic;

Signal sum : out std_logic_vector(3 downto 0);

Signal cout : out std_logic

);

End FA_4bit;

Architecture behave of FA_4bit is

Signal c : std_logic_vector (4 downto 0);

Begin

Process (a,b,cin,c)

Begin

C(0) < cin;

for I in a’range loop

Sum(i) <= a(i) xor b(i) xor c(i);

C(i+1) <= (a(i) and b(i)) or (c(i) and (a(i) or b(i));

End loop;

Cout <= c(c’HIGH);

.UCF file for FPGA XC3S400

NET “a<0>” LOC = “p33”

NET “a<1>” LOC = “p26”;

NET “a<2>” LOC = “p24”;

NET “a<3>” LOC = “p22”;

NET “b<0>” LOC = “p37”;

NET “b<1>” LOC = “p36”;

NET “b<2>” LOC = “p35”;

NET “b<3>” LOC = “p34”;

NET “cin” LOC = “p42”;

NET “cout” LOC = “p133”;

NET “sum<0>” LOC = “p143”;

NET “sum<1>” LOC = “p140”;

NET “sum<2>” LOC = “p139”;

NET “sum<3>” LOC = “p138”;

Truth table for Full Adder

cin input output

Sw1 a3

Sw2 a2

Sw3 a1

Sw4 a0

Sw5 b3

Sw6 b2

Sw7 b1

Sw8 b0

LE5 Cout

LED4 Sum3

LED3 Sum3

LED2 Sum1

LED1 Sum0

0 1 1 1 1 1 1 1 1 1 1 1 1 00 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 1 0 0 1 0 0 0 0 1 10 1 0 0 0 1 0 0 0 1 0 0 0 00 1 1 1 0 1 0 1 1 1 1 0 0 10 1 1 0 1 1 0 0 1 1 0 1 1 0

;

2. 4-bit Counter

Library IEEE;




Entity Counter_4bit is

PORT ( clk, reset : in std_logic;

Cnt_en : in std_logic;

Dout : out std_logic_vector ( 3 downto 0)

);

End Counter_4bit;

Architecture behave of Counter_4bit is

Signal cnt_state : std_logic_vector (7 downto 0);

Begin

Process (clk, reset, cnt_en)

Begin

If(reset = ‘1’) then

--asynchronous reset

Cnt_state <= “00000000”;

Elsif (clk’event and clk=’1’ ) then

If (cnt_en = ‘1’) then

Cnt_state <= cnt_state+1;

End if;

End if;

End process;

Dout <= cnt_state (6 downto 3);

End behave;


NET “clk” LOC = “p180”;

NET “cnt_en” LOC = “p22”;

NET “dout<0>” LOC = “p143”;




NET “reset” LOC = “p204”;

3. Decoder 2 to 4 Line

Library IEEE;


Entity decode2to4 is

PORT ( a,b, enable : in std_logic;

z : out std_logic_vector ( 3 downto 0)

);

End decode2to4;

Architecture DECODE_Concurrent of decode2to4 is

Begin

Z(0) <= ‘1’ when ((enable =’1’) and (a=’0’) and (b=’0’)) else ‘0’;




End DECODE_Concurrent;


NET “a” LOC = “p22”;

NET “b” LOC = “p24”;

NET “a” LOC = “p22”;

NET “enable” LOC = “p26”;

NET “z<0>” LOC = “p143”;

NET “z<1>” LOC = “p140”;

NET “z<2>” LOC = “p139”;

NET “z<3>” LOC = “p138”;

Truth Table for 2 to 4 decoder

Sw S3 input En

Sw S2 input a

Sw S2 input a

LED4 o/p Y3

LED3 o/p Y2

LED2 o/p Y1

LED1 o/p Y0

1 0 0 0 0 0 11 0 1 0 0 1 01 1 0 0 1 0 01 1 1 1 0 0 0

4. Decoder 3 to 8 Line

Library IEEE;




Entity decoder3to8 is

PORT ( signal sel : in std_logic_vector( 2 downto 0);

Signal en : in std_logic;

Signal Y : out std_logic_vector( 7 downto 0)

);

End decoder3to8;

Architecture behave of decoder3to8 is

Begin

Process ( sel, en)

Begin

Y <= “11111111”;

If(en=’1’) then

Case sel is

When “000” => Y(0) <= ‘0’;

When “000” => Y(0) <= ‘0’;

When “001” => Y(1) <= ‘0’;

When “010” => Y(2) <= ‘0’;

When “011” => Y(3) <= ‘0’;

When “100” => Y(4) <= ‘0’;

When “101” => Y(5) <= ‘0’;

When “110” => Y(6) <= ‘0’;

When “111” => Y(7) <= ‘0’;

End case;

End if;

End process;

End behave;


NET “en” LOC = “p33”;

NET “sel<0>” LOC = “p26”;

NET “sel<1>” LOC = “p24”

NET “sel<2> LOC = “p22”;

NET “Y<0>” LOC = “p143”;

NET “Y<1>” LOC = “p140”;

NET “Y<2>” LOC = “p139”;

NET “Y<3>” LOC = “p138”;

NET “Y<4>” LOC = “p133”;

NET “Y<5>” LOC = “p132”;

NET “Y<6>” LOC = “p131”;

NET “Y<7>” LOC = “p130”;

5. Half Adder

Library IEEE;




Entity HA is

PORT (X, Y : in std_logic;

SUM, Carry : out std_logic

);

End HA;

Architecture behave of HA is

begin

Sum <= X xor Y;

Carry <= X and Y;

End behave;


NET “X” LOC = “p22”;

NET “Y” LOC = “p24”;

NET “SUM” LOC = “p140”;

NET “Carry” LOC = “p143”;

6. Half Subtractor

Library IEEE;




Entity HS is

PORT (X, Y : in std_logic;

Diff, Borrow : out std_logic

);

End HS;

Architecture behave of HS is

begin

Diff <= X xor Y;

Borrow <= NOT X and Y;

End behave;


NET “X” LOC = “p22”;

NET “Y” LOC = “p24”;

NET “Diff” LOC = “p140”;

NET “Borrow” LOC = “p143”;

7. Encoder

Library IEEE;




Entity encoder is

PORT (

Reset : in std_logic;

Clk : in std_logic;

D_in : in std_logic_vector (7 downto 0);

D_out : out std_logic_vector (2 downto 0)

);

End encoder

Architecture behave of encoder is

Begin

Process(reset, clk, D_in)

Begin

If (reset=’1’) then

D_out <= “000”;

Elsif (Clk’event and Clk = ‘1’) then

Case D_in is

When “00000001” => D_out <= “000”;

When “00000010” => D_out <= “001”;

When “00000100” => D_out <= “010”;

When “00001000” => D_out <= “011”;

When “00010000” => D_out <= “100”;

When “00100000” => D_out <= “101”;

When “01000000” => D_out <= “110”;

When “10000000” => D_out <= “111”;

End case;

End if;

End process;

End behave;



NET “D_in<0>” LOC = “p22”;

NET “D_in<1>” LOC = “p24”;

NET “D_in<2>” LOC = “p26”;

NET “D_in<3>” LOC = “p33”;

NET “D_in<4>” LOC = “p34”;

NET “D_in<5>” LOC = “p35”;

NET “D_in<6>” LOC = “p36”;

NET “D_in<7>” LOC = “p37”;

NET “D_out<0>” LOC = “p143”;

NET “D_out<1>” LOC = “p140”;

NET “D_out<2>” LOC = “p139”;

8. Flip-FlopLibrary IEEE;




Entity D_flipflop is

PORT (

Clk : in std_logic;

Din : in std_logic;

Dout : out std_logic

);

End D_flipflop;

Architecture behave of D_flipflop is

Begin

Process ( clk, Din)

Begin

If clk’event and clk=’1’ then -- using rising edge of the clock

Dout <= Din;

End if;

End process;

End behave;



NET “Din” LOC = “p22”;

NET “Dout” LOC = “p143”;

9. Multiplexer

Library IEEE;




Entity Mux is

PORT (

Sel : in std_logic_vector (1 downto 0);

A,B,C,D : in std_logic;

Y : out std_logic

);

End Mux;

Architecture behave of Mux is

Begin

Process ( A,B,C,D, Sel)

Begin

Case sel is

When “00” => Y <= A;

When “01” => Y <= B;

When “10” => Y <= C;

When “11” => Y <= D;

End case;

End process;

End behave;


NET “Sel<0>” LOC = “p34”;

NET “Sel<1>” LOC = “p35”;

NET “A” LOC = “p22”;

NET “B” LOC = “p24”;

NET “C” LOC = “p26”;

NET “D” LOC = “p33”;

NET “Dout” LOC = “p143”;

10. DeMultiplexure

Library IEEE;




Entity DeMux is

PORT (

A : in std_logic;

SEL : in std_logic_vector(1 downto 0);

Dout : out std_logic_vector(3 downto 0);

);

Architecture behave of DeMux is

Begin

Process(SEL,A)

Begin

Case SEL is

when “00” => Dout <= (0 => A, other <= ‘1’);

when “01” => Dout <= (1 => A, other <= ‘1’);

when “00” => Dout <= (2 => A, other <= ‘1’);

when “00” => Dout <= (3 => A, other <= ‘1’);

when others => Dout <= NULL;

end case;

end process;

end behave;

.UCF File

NET “A” LOC = “P22”;

NET “SEL<0>” LOC = “P24”;

NET “SEL<1>” LOC = “P26”;

NET”Dout<0>” LOC = “P143”;

NET “Dout<1>” LOC = “140”;

NET “Dout<2>” LOC = “P139”;

NET “Dout<3>” LOC = “P138”;

11. Parity Checker

Library IEEE;




Entity Parity_Checker is

PORT (

A,B,C : in std_logic;

Y : out std_logic

);

End Parity_Checker;

Architecture behave of Parity_Checker is

signal X : std_logic;

Begin

X <= A xor B;

Y <= X xor C;

End behave;


NET “A” LOC = “p22”;

NET “B” LOC = “p24”;

NET “C” LOC = “p26”;

NET “Y” LOC = “p143”;

12. JK Flip-Flop

Library IEEE;




Entity JKFF is

PORT (

J,K : in std_logic;

Q, QBar : out std_logic

);

End;

Architecture behave of JKFF is

Signal Qin : std_logic;

Begin

Q <= Qin;

QBar <= NOT Qin;

Process (clk)

Begin

If (clk’event and clk = ‘0’) then

If (J=’1’) then

Q < = ‘1’;

End if;

If (K=’1’) then

QBar <= ‘1’;

End if;

If (J=’1’ and K=’1’ ) then

Qin <= NOT Qin;

End if;

End if;

End process;

End;

.UCF File


NET “J” LOC = “p22”;

NET “K” LOC = “p24”;

NET “Q” LOC = “p143”;

NET “QBar” LOC = “p140”;

13 BCD Counter

Library IEEE;




Entity BCDCounter is

PORT (

Clk,reset, count, count_En : in std_logic;

Dout : out std_logic_Vector (3 downto 0);

Count_State : inout std_logic(7 downto 0);

);

Behaviour Simulation

There are two options to simulate the ISE design.

1. Specifying stimulus inputs graphically called test bench waveform (not available in version 10 and above)

2. Specifying input stimulus using VHDL test bench (Available in all higher versions)

This tutorial explains the behavior simulation using VHDL test bench techniques for the 4-bit counter created in assignment-2 above. The steps are:

1. Create a project (4-bit counter) and enter the code given at index (b).2. In the project menu, click new source.3. Create a pro

Procedure for Schematic Draw (Structureal Modeling using Schematc Drawing

ISE/WebPACK Simulation:

This section introduces the ISim simulator included with ISE. At this point you should have a project like that in section 5 which contains the description of a combinational logic circuit. Consideration is given later to state machines.

Simulation involves a special file called a test bench or test fixture. Following version 10.1 32-bit, ISE no longer includes a graphical tool to generate test benches. Rather, an ISE tool generates a skeleton of a test bench so that a minimum of typing is required.

Here we consider such a simple VHDL test bench. Xilinx provides application notes[?] that may be helpful.

Make a Testbench File After a skeleton testbench is created you will modify its contents. Be sure that all your work is saved or you may end up with a fairly empty skeleton testbench le. If you are making a testbench for a flip-flop, state machine, or other registered logic then make the skeleton testbench file using the following but making appropriate substitutions. The testbench file name will be different as will the entity name and the signals. At the point where you assign the stimulus input go to section 7

a. Open new sourceb. In the New Source Wizard pop-up window enter the following. The term Default refers to a

given value which should not be changed. Click Nextc. The next window asks you to select a source le. Click to select 'fadd' then click Nextd. The next window is a summary of your choices and values. Review the list then click 'Finish'.

e. If the test bench le doesn't automatically open then open the le. Under the Options pane or process pane look for and click on the Design tab. You might have to click the left arrow just to the right to bring the Design tab into view.

• Look in the Hierarchy pane, click to select the 'Simulation' button, check that the 'Behavioral' choice is made and double click on 'fadd_fadd_sch_tb' so the corresponding test bench le appears in the text editor window.A test bench is analogous to a laboratory test bench, which has signal generators, and test gear. We will use the test bench to describe the inputs and rather than using the test gear to verify the results, we will visually examine the simulator output waveform.• At the top of the test bench le look for the following generated text . The ellipsis refer to extra content not shown here. The double hyphens -- are used to start a comment that the simulator will ignore. Following the comment block are LIBRARY and USE clauses that we will take as given• Look for the keyword 'ENTITY' as in the text below. This is where the inputs and outputs are declared in the description of a circuit. Note that a testbench le is referred to as being enclosed as it has no overall inputs or outputs.

ENTITY fadd_fadd_sch_tb IS END fadd_fadd_sch_tb;

• Next, look for the keyword 'ARCHITECTURE' and following that the keyword 'COMPONENT' starts the description of what the circuit you made looks like from the outside, so to speak. Next, all the signals that connect to the inputs and outputs of your circuit are declared. To make the typing later easier we add a declaration for a signal x. This part of the testbench will look like the following:ARCHITECTURE behavioral OF fadd_fadd_sch_tb IS COMPONENT fadd

PORT( cout : OUT STD_LOGIC; bin : IN STD_LOGIC; ain : IN STD_LOGIC; cin : IN STD_LOGIC; sum : OUT STD_LOGIC);

END COMPONENT; SIGNAL cout : STD_LOGIC; SIGNAL bin : STD_LOGIC; SIGNAL ain : STD_LOGIC; SIGNAL cin : STD_LOGIC; SIGNAL sum : STD_LOGIC; SIGNAL x : STD_LOGIC_VECTOR(1 to 3); -- New line BEGIN

Figure: Declaration part of test bench• The next part assigns the simulation inputs. Look for the keyword 'PROCESS' and its following keyword 'BEGIN'. Each of the following lines after the keword 'BEGIN' in Figure 23 describes one step in the simulation. Each line assigns an input and the wait keyword causes the simulation to proceed for a given amount of simulated time. Insert code so the process looks like the following. Note that double quotes are used to express strings of bits but single quotes are used for individual bits, such as '0' or '1'.-- *** Test Bench - User Defined Section *** tb : PROCESS BEGIN x <= "000"; wait for 100 ns; -- The following x <= "001"; wait for 100 ns; -- are new text x <= "010"; wait for 100 ns; -- lines, insert x <= "011"; wait for 100 ns; -- and/or modify x <= "100"; wait for 100 ns; -- x <= "101"; wait for 100 ns; -- x <= "110"; wait for 100 ns; -- x <= "111"; wait; -- end of input END PROCESS; -- *** End Test Bench END;

Check the Testbench

With the testbench created the next step is to check the file

• Look in the Design Hierarchy pane, click to select the Simulation button, check that hte 'Behavioral' choice is made and double click on 'fadd_fadd_sch_tb' so the corresponding test bench le appears in the text editor window. The Design Hierarchy pane should look like that in Figure 17. ISE provides at least two opportunities to use simulation to check the correctness of a circuit.

Behavioral - A simulation performed using the VHDL code as-is. No device specific timing information is provided so the simulation looks ideal.

Post-Route - This is the whole enchilada. This type contains timing information from the implementation and will be the most realistic.

• In the Design Process pane click the '+' symbol to the left of 'ISim Simulator' to expand the category.

• Right click on 'Behavioral Check Syntax' and select 'Run' After a few moments a green check should appear in the pane, othwise scroll through the comments made in the console below to determine what happened during the check and then correct the testbench file.

Perform the Simulation (Full Adder)

ADVANCED Experimentsi. Multiplicationii. Divisioniii. Switch and LED interfaceiv. A switch Encoderv. Encodervi. Priority Encodervii. 4x4 KeyPad interfacing design viii. PS/2 KeyPad interfacing design

ix.

1. Multiplication

Library IEEE;




Entity Multiplication is

PORT (

A, b : in unsigned (1 downto 0);

Output : out unsigned (3 downto 0)

);

End;

Architecture behave of Multiplication is

Begin

Output <= a* b;

End;

.UCF file

NET “a<0>” LOC = “p22”; #s1

NET “a<1>” LOC = “p24”; #s2

NET “b<0>” LOC = “p26”; #s3

NET “b<1>” LOC = “p33”; #s4

NET “output<0>” LOC = “p143”;

NET “output <1>” LOC = “p140”;



2. DIVISION

It take two four bit inputs a (S5-S8) and b(S1-S4) and shows the result for the division a/b. The four bit quotient is shown on LEDs 1-4 and the remainder is shown on LED 5-8. When the divisor is 0, it gives error by turning the LEDs RED.

For eg.

No A B Y (Quotient) R (Remainder) Error (LED 5)

1 0011 0010 0001 0001 02 0111 0001 0111 0000 03 0010 0000 -- -- 14 0111 0100 0001 0011 05 0011 0101 0000 0011 06 1110 0100 0011 0010 07 1011 0111 0001 0100 08 1110 0010 0111 0000 09 1110 0111 0010 0000 0

Library IEEE;




Entity Div is

PORT (

A, b : in std_logic_vector (3 downto 0);

Y: out std_logic_vector (3 downto 0); -- output

R: out std_logic_vector (3 downto 0) – R is remainder

);

End;

Architecture behave of Div is

Begin

Process (a,b)

Variable temp1 : integer range 0 to 15;-- tem var to hold value of a

Variable temp2 : integer range 0 to 15; -- tem var to hold value of b

Begin

Temp1:= conv_integer(a); --convert a to integer

Temp2:= conv_integer(b); --convert b to integer

If(b=0) then

R <= “0001”;

Y<=”0000”;

Else

---------------to calculate y(3)--------------------

If (temp1>=temp2*8) then

Y(3) <= ‘1’;

Temp1 := temp1 - temp2*8;

Else

Y(3) <= ‘0’;

End if;

-------------------to calculate y(2)----------------

If(temp1 >= temp2 * 4) then

Y(2) <= ‘1’;

Temp1 := temp1 – temp2 * 4;

Else

Y(2) <= ‘0’;

End if;

-------------------to calculate y(2)----------------

If (temp1 >= temp2*2) then

Y(1) <= ‘1’;

Temp1 := temp1 – temp2 * 2;

Else

Y(1) <= ‘0’;

End if;

---------------to calculate y(0)--------------------------

If(temp1 >= temp2 ) then

Y(0) <= ‘1’;

Temp1 <= temp1 – temp2;

Else

Y(0) <= ‘0’;

End if;

------------Remainder-----------------------------

R <= conv_std_logic_vector (temp,4);

End if;

End process;

End behavioural;

.UCF File

NET “a<0> LOC = “p34”;

NET “a<1> LOC = “p35”;

NET “a<2> LOC = “p36”;

NET “a<3> LOC = “p37”;

NET “b<0> LOC = “p22”;

NET “b<1> LOC = “p24”;

NET “b<2> LOC = “p26”;

NET “b<3> LOC = “p33”;

NET “y<0> LOC = “p143”;

NET “y<1> LOC = “p140”;

NET “y<2> LOC = “p139”;

NET “y<3> LOC = “p138”;

NET “r<0> LOC = “p133”;

NET “r<1> LOC = “p132”;

NET “r<2> LOC = “p131”;

NET “r<3> LOC = “p130”;

3. Using On-Board switch Push-to-On switch and biclour LEDs

Program takes input from switches and connects it to LEDs. When a switch is pressed, Corresponding LED becomes green. LED will show RED when corresponding switch is not pressed.

Library IEEE;




Entity Switch LED is

PORT (

SW : in std_logic_vector (7 downto 0);

LED : out std_logic_vector (7 downto 0)

);

End;

Architecture behave of SwitchLED is

Begin

LED <= SW

End behavioural;

.UCF File

NET “SW<0> LOC = “p22”;

NET “SW<1> LOC = “p24”;

NET “SW<2> LOC = “p26”;

NET “SW<3> LOC = “p33”;

NET “SW<4> LOC = “p34”;

NET “SW<5> LOC = “p35”;

NET “SW<6> LOC = “p36”;

NET “Sw<7> LOC = “p37”;

NET “LED<0> LOC = “p143”;








ENCODER

An encoder has a number of input lines, only one of which is activated at a given time, and produces an N-bit output code, depending on which input is activated.An octal-to-binary encoder (8-line-to-3-line encoder) performs the opposite function: it accepts eight input lines and produces a three-bit output code corresponding to the activated input. Figure 9-13 shows the logic circuitand the truth table for an octal-to-binary encoder with active-LOW inputs.

Figure : An eight line-to-3 line Encoder

By following through the logic, you can verify that a LOW at any single input will produce the output binary code corresponding to that input. For instance, a LOW at A3 (while all other inputs are HIGH) will produce O2=0,O1=1 and O0=1, which is the binary code for 3. Notice that A0’ is not connected to the logic gates because the encoder outputs will normally be at 000 when none of the inputs A1’ to A9’ is LOW.74147 Priority EncodersPriority encoder, includes the necessary logic to ensure that when two or more inputs are activated, the output code will correspond to the highest-numbered input. 74147 which functions as a decimal-to-BCD priority encoder. It has nine active-LOW inputs representing the decimal digits 1 through 9, and it produces the inverted BCD code corresponding to the highest-numbered activated input.

Figure 74147 Decimal to-BCD Priority Encoder

The first line in the table shows all inputs in their inactive HIGH state. For this condition, the outputs are 1111, which is the inverse of 0000, the BCD code for 0. The second line in the table indicates that a LOW at regardless of the states of the other inputs, will produce an output code of 0110, which is the inverse of 1001, the BCD code for 9. The third line shows that a LOW at provided that is HIGH, will produce an output code of 0111, the inverse of 1000, the BCD code for 8. In a similar manner, the remaining lines in the table show that a LOW at any input, provided that all higher-numbered inputs are HIGH, will produce the inverse of the BCD code for that input.The 74147 outputs will normally be HIGH when none of the inputs are activated. This corresponds to the decimal 0 input condition. There is no input because the encoder assumes the decimal 0 input state when all otherinputs are HIGH. The 74147 inverted BCD outputs can be converted to normal BCD by putting each one through an INVERTER.

A Switch Encoder

Because the 74LS147 is a priority encoder, simultaneous key depressions will produce the BCD code for the higher-numbered key.Example usage is calculator where the BCD code for each decimal digit is entered into a four-bit storage register.When the first key is depressed, the BCD code for that digit is sent to a four-bit FF register; when the second switch is depressed, the BCD code for that digit is sent to another four-bit FF register, and so on. Thus, a calculator that can handle eight digits will have eight four-bit registers to store the BCD codes for these digits. Each four-bit register drives a decoder/driver and a numerical display so that the eight-digit number can be displayed.This circuit will take three decimal digits entered from the keyboard in sequence, encode them in BCD, and store the BCD in three FF output registers.

The circuit operation is described as follows for the case where the decimal number 309 is being entered:1. The CLEAR key is depressed. This clears all storage flip-flops Q0 to Q11 to 0. It also clears flip-flops X and Y and presets flip-flop Z to 1, so that the ring counter begins in the 001 state.2. The CLEAR key is released and the “3” key is depressed. The encoder outputs 1100 are inverted to produce 0011, the BCD code for 3.These binary values are sent to the D inputs of the three four-bit output registers.

3. The OR output goes HIGH (because two of its inputs are HIGH) and triggers the OS output Q = 1 for 20 ms.After 20 ms,Q returns LOW and clocks the ring counter to the 100 state (X goes HIGH). The positive transitionat X is fed to the CLK inputs of flip-flops to so that the encoder outputs are transferred to these FFs. That is,and . Note that flip-flops Q4 to Q11 are not affected because their CLK inputs have not received a positive transition.4. The “3” key is released and the OR gate output returns LOW.The “0” keyis then depressed. This produces the BCD code of 0000, which is fed tothe inputs of the three registers.5. The OR output goes HIGH in response to the “0” key (note the INVERTER) and triggers the OS for 20 ms. After 20 ms, the ring counter shifts to the 010 state (Y goes HIGH).The positive transition at Y is fed to the CLK inputs of Q4 toQ7 and transfers the 0000 to these FFs. Note that flip-flops Q0 to Q3 and Q8 to Q11 are not affected by the Y transition.6. The “0” key is released and the OR output returns LOW. The “9” key is depressed, producing BCD outputs 1001, which are fed to the storageregisters.7. The OR output goes HIGH again, triggering the OS, which in turn clocks the ring counter to the 001 state (Z goes HIGH). The positive transition at Z is fed to the CLK inputs of Q0 to Q3 and transfers the 1001 into theseFFs. The other storage FFs are unaffected.8. At this point, the storage register contains 001100001001, beginning with Q11 . This is the BCD code of 309. These register outputs feed decoder / drivers that drive appropriate displays for indicating the decimal digits 309.9. The storage FF outputs are also fed to other circuits in the system. In a calculator, for example, these outputs would be sent to the arithmetic section to be processed.

The 74ALS148 is slightly more sophisticated than the ’147. It has eight inputs that are encoded into a three-bit binary number.This IC also provides three control pins as indicated in Table 9-1.The Enable Input ( ) and EnableOutput (EO’ ) can be used to cascade two IC’s producing a hexadecimal-to binary encoder. The pin must be LOW in order for any output pin to go LOW, and the EO’ pin will only go LOW when none of the eight inputs is activeand the EI’ is active. The GS’ output is used to indicate when at least one of the eight inputs is activated. It should be noted that the outputs A2through A0 are inverted, just as in the 74147

1. 4x4 Keypad Module Design

Let us understand how such a digital system work. Then we will use this analysis to reinvent our own code.

In the following section we are going to analyse a very useful digital circuit that encodes a hexadecimal keypad into a four bit binary output. Encoder such as this generally have a strobe output that indicates WHEN SOMEONE PRESSES AND RELEASES A KEY. Because keypads are often interfaced to a microcomputer’s bus system, the encoded output should have tristate enables.Figure shows the block diagram of the keypad encoder.

The priority encoder method is effective for small keypad. However, large keypads such a sthose found on PCs must use a different technique. In these keyboards, each key is not an independent switch to Vcc or to Gnd. Instead, each key switch is used to connect a row to a column in a keyboard matrix. When keys are not pressed, there are no connections between the rows and columns. The trick of knowing which key is pressed is accomplished by activating (pulling low) one row at a time and then checking to see if any of the columns have gone low. If one of the column has a low on it, then the key being pressed is at the intersection of activated row and the column that is currently LOW. If no columns are low, we know that no key is in activated row are being pressed and we check the next row by pulling it low. Sequentially activating rows is called scanning the keyboard. The advantage of this method is the reduction in connections to the keypad. In this case 16 keys can be encoded using eight (8) inputs/outputs.

Each key represents a unique combination of a row number and a column number. By strategically numbering the rows and the columns, we can combine binary row and column numbers to create the binary values of the hexadecimal keys as shown in figure 2

In this figure row 1 (01) is pulled low and the data on the column encoder is 102 so the button at row 1, column 2 is evidently pressed. The NAND gae in figure 1 is used to determine if any column is LOW, indicating that a key is pressed in the currently active row. The output of this gate is named FREEZE because when a key is pressed, we want to FREEZE the ring counter and quit scanning until the key is released. As the encoder go through their propagation delay and the tristate buffer become enabled, the data outputs are in a transient state. On the next rising edge of the clock, the D FF will transfer a HIGH from FREEZE to the DAV output, indicating that a key is pressed and the valid data is available.

A shift register counter (ring counter), as we already have studied, is used to generate the sequential scan of the four rows. The count sequence uses four states, each state having different bit pulled LOW. When a key pressed is detected, the ring counter must hold in its current state (FREEZE) until the key is released. Figure-3 shows the state transition diagram. Each state of the counter must be encoded to generate a two-bit binary row number. Each column value must also be encoded to generate binary column number. The system will require the following input output ports.

Library ieee;


Entity Keypad_Encoder is

PORT (

CLK : in std_logic;

Col : IN std_logic_vector(3 downto 0);

Row : OUT std_logic_vector (3 downto 0);

D : out std_logic_vector(3 downto 0);

DAV : out std_logic

);

Architecture behave of Keypad_Encoder is

Signal FREEZE : std_logic;

Signal DATA : std_logic_vector (3 downto 0);

Begin

Process (clk)

Variable ring : std_logic_vector(3 downto 0);

Begin

If clk’event and clk=’1’ then

If FREEZE = ‘0’ then

Case ring is

When “1110” => ring := “1101”;

When “1101” => ring := “1011”;

When “1011” => ring := “0111”;

When “0111” => ring := “1110”;

When others => ring := “1110”;

End case;

End if;

DAV <= FREEZE;

End if;

Row <= ring;

CASE ring is

When “1110” => DATA(3 downt 2) <= “00”;

When “1101” => DATA(3 downt 2) <= “01”;

When “1011” => DATA(3 downt 2) <= “10”;

When “0111” => DATA(3 downt 2) <= “11”;

When others => DATA(3 downt 2) <= “00”;

End case;

CASE col is

When “1110” => DATA(1 downt 0) <= “00”; FREEZE <= ‘1’;




When others => DATA(1 downt 0) <= “00”; FREEZE <= ‘0’;

End case;

If FREEZE = ‘1’ then

D <= DATA;

Else

D <= “ZZZZ”;

End if;

End process;

End;

Priority Encoder

A very important concept is the method of describing precedence for the inputs. This code uses the conditional signal assignment statement. It assigns tha values listed on the right of <= to a signal on the left, assuming the condition following WHEN is true. If the clause is not TRUE, the clause fllowing ELSE are evaluated one ata atime until the one that is true is found. The value preceding WHEN is then assigned to a signal on the left side of <=.The precedence of the assignment is established by the order in which they are listed.

The first line of the statement, the first condition being tested is the enabling of the tristate outputs. It should be noted here that the three states of tristate outputs are HIGH, LOW and High Impedance which is referred as ‘Z’ or “ZZZZ”. If the outputs are to be disabled (High Z), then none of the other encoding matters.

In the following VHDL code the first line of code in architecture body is the condition for tristate output which is eithr OE line is LOW or when all the switches are HIGH. The second line tests for the highest priority , which is 9 of the switch and so on.

Library IEEE;

Use ieee.std_logic_1164.all

Entity Priority_Encod is

PORT (

Sw : in std_logic_vector(9 downto 0);

OE : in std_logic;

D : out std_logic_vector(3 downto 0)

);

End;

Architecture concur of Priority_Encod is

Begin

D <= “ZZZZ” when OE = ‘0’ or SW=”1111111111” else

“1001” when SW(9)=’0’ else

“1000” when SW(8)=’0’ else

“0111” when SW(7)=’0’ else

“0110” when SW(6)=’0’ else

“0101” when SW(5)=’0’ else

“0100” when SW(4)=’0’ else

“0011” when SW(3)=’0’ else

“0010” when SW(2)=’0’ else

“0001” when SW(1)=’0’ else

“0000” when SW(0)=’0’ ;

End;

Keyboard

This program is used to interface PS/2 keyboard with FPGA kit. The keyboard sends the data one byte a time in a frame consisting of 11 bits:

1 start bit

8 data bits

1 parity bit

1 stop bit

PS/2 keyboard generates the clock KBCLK. Since KBCLK is a TTL signal which is being transmitted over a distance of 1.5 meter and FPGA being high speed technology (> 100mHz), the clock will seem to have multiple edge during its rise times. The same have to be avoided using digital debounce circuit wherein a dead time of 4 usec is maintained on each rise and fall time.

Also when a key is pressed, the scan code in the for of serial data (KBDATA) from the keyboard is sampled at the middle of the negative clock cycle of KBCLK to overcome the transmission line delays. To do this, a counter is used to count delay using 16 MHz clock.

At the start of the negative half-cycle of KBCLK. The counter starts incrementing and after a certain number of increments(240) which delays 15 usec (period of 16 MHz clock is 62.5 ns. 62.5ns * 240=15us), KBDATA is sampled. When DIP switch SS3-1 is turned ON, the scan code is displayed on LEDs; when the switch is turned OFF, the corresponding ASCII code is displayed on LEDs(Display format: LED 5,6,7,8,1,2,3,4 on MB: MSB-LED). For keys having no valid ASCII code (e.g. ALT key), all LEDs turns green. A combinational logic is used to convert scancode to its ASCII equivalent.

VHDL code:

Library ieee;




Entity keyboard is

PORT(

Clk : in std_logic;

KBCLK : in std_logic;

KBDATA : in std_logic;

Switch :in std_logic;

LED : out std_logic_vector(7 downto 0):=(others => ‘0’)

);

End keyboard;

Architecture behave of keyboard is

Signal sampled_KBDATA : std_logic_vector(11 downto 0):=(others => ‘0’);

Signal ScanCode : std_logic_vector(7 downto 0):=(others => ‘0’);

Signal ASCII_equi : std_logic_vector(7 downto 0):=(others => ‘0’);

Signal counter: std_logic_vector(10 downto 0):=(others => ‘0’);

Signal BitCounter : std_logic_vector(3 downto 0):=(others => ‘0’);--to count the KBDATA bits

--debounce circuit---------------------------------used to get 250KHz clock for debounce circuit----

Signal clk_counter: std_logic_vector(5 downto 0):=(others => ‘0’);

Signal KHz250 “ std_logic; --------------------250 KHz clock

Signal KBCLK_debounce : std_logic;

Begin

KHz250 <= clk_counter (5);

ScanCode <= Sampled_KBDATA ( 8 downto 1);

--------------------Debounce Circuit--------------

Process (KHz250)

Begin

If (KHz250’event and KHz250=’1’) then

KBCLK_debounce <= KBCLK;

End if;

End process;

Process (CLK)

Begin

If(CLK’event and CLK = ‘1’) then

Clk_counter <=clk_counter +1;

If (switch = ‘1’) then

LED <= SanCode; --if SS4-1 is in OFF position, LED will show scancode------------------

Else

LED <= ASCII_equiv; --if SS4-1 I in ON position, LED will show ASCII Equiv------------

End if;

-----------to convert ScanCode into ASCII equivalent------------------------------------

Case (ScanCode) is

When X”1C” => ASCII_Equiv <= X”41”; -------------------A

When X”32” => ASCII_Equiv <= X”42”; -------------------B

When X”21” => ASCII_Equiv <= X”43”; -------------------C

When X”23” => ASCII_Equiv <= X”44”; -------------------D

When X”24” => ASCII_Equiv <= X”45”; -------------------E

When X”2B” => ASCII_Equiv <= X”46”; -------------------F

When X”34” => ASCII_Equiv <= X”47”; -------------------G

When X”33” => ASCII_Equiv <= X”48”; -------------------H

When X”43” => ASCII_Equiv <= X”49”; -------------------I

When X”3B” => ASCII_Equiv <= X”4A”; ------------------J

When X”42” => ASCII_Equiv <= X”4B”; ------------------K

When X”4B” => ASCII_Equiv <= X”4C”; ------------------L

When X”3A” => ASCII_Equiv <= X”4D”; -------------------M

When X”31” => ASCII_Equiv <= X”4E”; -------------------N

When X”44” => ASCII_Equiv <= X”4F”; -------------------O

When X”4D” => ASCII_Equiv <= X”50”; -------------------P

When X”15” => ASCII_Equiv <= X”51”; -------------------Q

When X”2D” => ASCII_Equiv <= X”52”; -------------------R

When X”1B” => ASCII_Equiv <= X”53”; -------------------S

When X”2C” => ASCII_Equiv <= X”54”; -------------------T

When X”3C” => ASCII_Equiv <= X”55”; -------------------U

When X”2A” => ASCII_Equiv <= X”56”; -------------------V

When X”1D” => ASCII_Equiv <= X”57”; -------------------W

When X”22” => ASCII_Equiv <= X”58”; -------------------X

When X”35” => ASCII_Equiv <= X”59”; -------------------Y

When X”1A” => ASCII_Equiv <= X”5A”; -------------------Z

When X”45” => ASCII_Equiv <= X”30”; -------------------0


When X”1E” => ASCII_Equiv <= X”32”; -------------------2





When X”3D” => ASCII_Equiv <= X”37”; -------------------7



When X”0E” => ASCII_Equiv <= X”60”; -------------------‘

When X”4E” => ASCII_Equiv <= X”2D”; ------------------- -

When X”55” => ASCII_Equiv <= X”3D”; ------------------- =

When X”5D” => ASCII_Equiv <= X”5C”; ------------------- \

When X”29” => ASCII_Equiv <= X”20”; ------------------- SPACE

When X”0D” => ASCII_Equiv <= X”09”; ------------------- TAB

When X”5A” => ASCII_Equiv <= X”0C”; ------------------- ENTER




When X”7A” => ASCII_Equiv <= X”33”; -------------------3

When X”6B” => ASCII_Equiv <= X”34”; -------------------4



When X”6C” => ASCII_Equiv <= X”37”; -------------------7


When X”7D” => ASCII_Equiv <= X”39”; -------------------9

When X”E0” => ASCII_Equiv <= X”2F”; ------------------- /

When X”7A” => ASCII_Equiv <= X”2A”; ------------------- *

When X”7A” => ASCII_Equiv <= X”2D”; ------------------- -

When X”7A” => ASCII_Equiv <= X”2B”; ------------------- +

When X”7A” => ASCII_Equiv <= X”5D”; ------------------- ]

When X”7A” => ASCII_Equiv <= X”3B”; ------------------- ;

When X”7A” => ASCII_Equiv <= X”27”; ------------------- ‘

When X”7A” => ASCII_Equiv <= X”2C”; ------------------- ,

When X”7A” => ASCII_Equiv <= X”2E”; ------------------- .

When X”7A” => ASCII_Equiv <= X”2F”; ------------------- /

WHEN OTHERS => ascii_Equiv <= X”00”;

--THE KEYS FOR WHICH THERE IS NO RELEVANT ascii CODE, WILL TURN on ALL GREEN ledS

If (KBCLK_debounce =’0’) then

Counter <= counter + 1; --counter is used to sample the KBDATA in the middle of the negative clock cycle when it is valid

If (counter = X”0F0”) then --if counter=240, sample KBDATA

Sampled_KBDATA (conv_integer (BitCunter)) <= KBDATA;

BitCounter <= BitCounter+1;

If(BitCounter = “1010”) then --when “11” bits of KBDATA are read, BitCounter is reset for next key press

BitCounter <= (others => ‘0’);

End if;

End if;

Elsif (KBCLK_debounce = ‘1’) then

Counter <= (others => ‘0’);

End if;

End if;

End process;

End;

.UCF File for Keyboard FPGA XCS400

NET “CLK” LOC = “P79”;

NET “KBDATA” LOC = “P144”;

NET “KBCLK” LOC = “P155”;

NET “Switch” LOC = “P22”;

NET “LED<0>” LOC = “P143”;

NET “LED<1>” LOC = “P140”;

NET “LED<2>” LOC = “P139”;

NET “LED<3>” LOC = “P138”;

NET “LED<4>” LOC = “P133”;

NET “LED<5>” LOC = “P132”;

NET “LED<6>” LOC = “P131”;

NET “LED<6>” LOC = “P130”;




















END CASE;

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