Verilog Tips & Rules

8/3/2019 Verilog Tips & Rules

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ntro uct on

Purpose of HDL:.

(like c) and in gate-level (e.g. And gate)

.

3. Synthesis

4. Words are better than pictures


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If both inputs are 1, change both outputs.

If one input is 1 change an output asfollows:

If the previous outputs are equalchange the output with input 0;

If the previous outputs are unequal

change the output with input 1.

If both inputs are 0, change nothing.


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ex cograp y

Comments:Two T es: // Comment

/* These comments extend

over multiple lines. Good

for commenting out code*/

Character Set:

0123456789ABCD..YZabcd...yz_$Cannot start with a number or $


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ata ypesmodule sample (a,b,c,d);

0,1,x,z

Wireinput a,b;

output c,d;- Synthesizes into wires

- Used in structural code

Rewire [7:0] b;

- May synthesize into latches, flip-flops or wires

- Used in procedural code

reg c,d;

integer k;

32-bit integer used as indexes

Input, Output, inoutDefines ports of a module (wire by default)


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ata a ues

Numbers:Numbers are defined by number

Parameters:

Value of 23:

5b10111

5d23

wire [n-1:0] t, d;

` = =5h17

Constants:

_ _Run_state =2, finish_state = 3;

if(state==`Run_state)

,

assign t = 23;

assign d= 4b0111;


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perators Arithmetic: reg [3:0] a, b, c, d;

*,+,-,/,%

Relational=,==, !=

w re : x,y,z;

parameter n =4;

c = a + b;

Bit-wise Operators Not: ~ XOR: ^

d = a *n;

If(x==y) d = 1; else d =0; n : 5b11001 & 5b01101 ==> 5b01001 OR: | XNOR: ~^ or ^~

d = a ~^ b;

if ((x>=y) && (z)) a=1;

Returns 1or 0, treats all nonzero as 1 ! : Not && : AND 27 && -3 ==> 1

else a = !x;

|| : OR


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perators Reduction Operators: module sample (a, b, c, d);

Unary operations returns single-bit values & : and | :or ~& : nand

,

output [2;0] c, d;wire z,y;

~| : nor ^ : xor

~^ :xnor Shift O erators

=c = a * b;If(a==b) d = 1; else d =0;

^Shift Left: >

Concatenation Operator

=

if ((a>=b) && (z)) y=1;else y = !x;

{ n{item} } (n fold replication of an item)

Conditional OperatorImplements if-then-else statement

assign d


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er og tructure

All code arecontained in modules

Can invoke other

modules Modules cannot be

contained in another

mo u e


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..

module gate(Z,A,B,C);input A,B,C;output Z;assign Z = A|(B&C);Endmodule

module two_gates(Z2,A2,B2,C2)input A2,B2,C2;output Z2;

ga e ga e_ , , , ;gate gate_2(Z2,G2,A2,B2);endmodule


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tructura s roce uraStructural Procedural

textua escr pt on o

circuit order does not matter

n e co e

Order of statements are

Starts with assignstatements

important Starts with initial or

always statement

Harder to code Easy to code, ,

wire c, d; reg c, d;alwa s a or b or c be in

assign d = c |b; assign c =a & b;assign d = c |b; end


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tructura s roce uraProcedural Structural

reg [3:0] Q;

wire [1:0] y;

always@(y)

wire [3:0]Q;

wire [1:0]y;

assign

begin

Q=4b0000;

case(y) begin

Q[0]=(~y[1])&(~y[0]),

Q[1]=(~y[1])&y[0],

Q[2]=y[1]&(~y[0]),=

2b01: Q[1]=1;

2b10: Q[2]=1;

2b11: Q 3 =1

=

Q[1]

endcase

end

0

Q[2]

y[1]Q[3]


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Blocking Non-blocking

=

Similar to C code

=

The inputs are stored once

The next assignmentwaits until the resent

e proce ure s r ggere

Statements are executed inone is finished para e

Used for fli -flo s, latches

logic and registers

one procedure


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oc ng s on- oc ng

Initialbe in

#1 e=2;

=

#1 b


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tatements

Syntax

if (expression)be in

...statements...end

else if (expression)begin

...statements...end

...more else if blocks

elsebegin

...statements...end


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ase tatements

Syntax

case (expression)case_choice1:

...statements...end

case_choice2:begin...statements...

end

... ...

default:begin...statements...

endendcase


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or oops

Syntax integer j;

for (count= value1;

count= value2;for(j=0;j


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ComponentInference


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p- ops

always@(posedge clk)begin

a


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-Reset

always@(posedge clk ornegedge rst)

eg n

if (!rst) a


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-and Enable

always@(posedge clk)begin

if (rst) a


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t eg sters

reg[3:0] Q;always@(posedge clk or

begin

if (rset) Q


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u t p exers

assign a = (select ? b : c);

Methodalways@(select or b or c) beginif(select) a=b;

else a=c;end

Method 2b

case se ec1b1: a=b;1b0: a=c;


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ounters

reg [7:0] count;wire enable;

a ways pose ge c ornegedge rst)

beginif (rst) count


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Avoiding UnwantedLatches

Latches are BAD


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u e

Method1:

,

every path must evaluate all outputs

.Later on different values can overwrite those values.always @(...

begin= = =

if (a) x=2; elseif (b) y=3; else z=4;End Method2:

always @(...begin

if (a) begin x=2; y=0; z=0; end= = =

else begin x=0; y=0; z=4; end

end


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u e

Right-hand side variables:

appear in the trigger list

Except variables both calculated and used in the procedure.always @(a or b or c or x or y)

begin

x=a; y=b; z=c;w=x+y;

end Branch controlling variables:Be sure every branch of every if and case generate every output

always @(a or b)beginif (a) begin x=2; y=0; z=0; endelseif (b) begin x=0; y=3; z=0; endelse begin x=0; y=0; z=4; end

end


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u e

End all case statements with the default case whetherstatements must be covered

you need it or not.case(state)...default: next_state = reset;

endcase

o no orge e se oops n your s a e grapif(a|b&c) next_state=S1;elseif(c&d) next_state=S2;else next_state=reset;


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Finite StateMachines


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tan ar orm or a er og

//state flip-flops

reg [2:0] state, nxt_st;//state definitions

//REGISTER DEFINITION

always@(posedge clk)

be inparameter

reset=0,S1=1,S2=2,S3=3,..state


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xamp emodule m FSM clk x zinput clk, x; output z;

// state flip-flopsre 2:0 state nxt st

always @(state or x)

begincase (state)

_// state definitionparameter S0=0,S1=1,S2=2,S3=3,S7=7

// REGISTER DEFINITION

_ =else nxt_st=S0;

S1: if(x) nxt_st=S3;

else nxt_st=S2;always @(posedge clk)begin

state


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ystem tas s

Used to generate input and output during simulation.Start with $ sign.

$display (format_string,par_1,par_2,...);

$monitor(format_string,par_1,par_2,...); ,

Writing to a File:

$fopen, $fdisplay, $fmonitor and $fwrite

Random number generator: $random (seed) Query current simulation time: $time


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est enc es

Overview Approach

.design

.

2. Set the clk signal.

3. Implement the system3. Send test vectors

4. Specify when to end thesimulation.


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xamp etimescale1 ns /100 ps

meun = ns; prec s on= ns;module my_fsm_tb;

reg clk, rst, x;wire z;

xInitial begin

#1 x=0;#400 x=1;$dis la Out ut z: %b, z ;

/**** DESIGN TO SIMULATE (my_fsm)INSTANTIATION ****/

myfsm dut1(clk, rst, x, z);

**** ****

#100 x=0;@(posedge clk) x=1;

#1000 $finish; //stop simulationInitialbegin

clk=0;rst=0;

,endendmodule

rst= ; e e ay g ves rst a pose ge or

sure.*/#200 rst=0;//Deactivate reset after two clock

cycles +1ns*/enda ways #50c =~c ; 10 z c oc 50 1ns 2

with 50% duty-cycle */


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equence etector

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