UNIT V.pdf

Analysis of Analog IC MOS amplifiers

Dr. D. Meganathan Department of Electronics Engineering, Madras Institute of Technology

Name the amplifier Mid Band Gain= ?

Positive Power Supply Rejection

Ratio ?

Negative Power Supply Rejection

Ratio?

Common-Mode Rejection Ratio?

Input Common Mode Voltage

Range ?

Output Common Mode Voltage

Range?

Output Voltage Swing?

M1

M3

M5

M7

M2

M4

M6

M8

VDD

M9

Vb1

Vb2

Vb1

Vb4

Vb3

Vin- Vin

+

Vb2

Vb3

VO+ VO

-

Feedback Concepts

Feedback concepts new

to us? 6/19/2014 3 D.Meganathan, Anna University

Harold S. Black, 1927

6/19/2014 4 D.Meganathan, Anna University

Feedback Amplifier by D.Meganathan 5

General feedback structure

A

A

x

xA

xxx

xx

Axx

s

of

fsi

of

io

1

Open loop gain

ALoop gain

Closed-loop gain

Mixer network

Voltage series Current shunt

Sampling network

Voltage shunt Current Series

FEEDBACK CONCEPTS in biasing circuit

ID = n/2 (VGS Vt)2

ID D

G

S

IREF

VDD

SIMPLE FEEDBACK

NO EXTRA CIRCUIT IS INVOLVED 6/19/2014 6 D.Meganathan, Anna University

Integrated Circuit Biasing Circuit

ID D

G

S

IREF

VDD CURRENT Source TO BIAS INTEGREATED CIRCUIT

6/19/2014 7 D.Meganathan, Anna University


Small signal Analysis of Common Source Amplifier

Input and Output Impedance measurement for Common source amplifier

Small signal Analysis of Common Source degenerator Amplifier

Input and Output Impedance measurement for Common source degenerator amplifier


Small signal Analysis of Common Drain Amplifier

Input and Output Impedance measurement for Common Drain amplifier

Small signal Analysis of Common Gate Amplifier

Input and Output Impedance measurement for Common Gate amplifier

Analysis of MOS amplifiers MID BAND GAIN ANALYSIS

Output Voltage swing

Input common-mode voltage range

Output common-mode voltage range

Power supply rejection ratio

Common mode rejection ratio

Small signal analysis

TO DETERMINE MIDBAND GAIN OF THE CIRCUIT

STEP 1 EVALUATE THE SMALL SIGNAL CIRCUIT CONSTANTS using DC Q-Point voltage and currents (gm, r0) gm = n(VGSQ-Vt) and r0 = VA/IDQ

STEP2 DRAW THE SMALL SIGNAL EQUIVALENT DIAGRAM

STEP 3

DETERMINE THE MID BAND VOLTAGE GAIN AV=VO/VS

+

-

vgs gm

vgs

r0 Vo

+

-

Determining Input impedance Step 1 Draw the small signal equivalent circuit diagram

Step 2 Null the output to the circuit

If it is a voltage source then short it

If it is a current source then open it

Step 3 Remove input voltage source from the circuit

Step 4 Connect known voltage or current source at the input terminal

Step 5 Measure the current supplied or voltage across the input source

Step 6 Determine the ratio of Voltage/ current

Determining Output impedance Step 1 Draw the small signal equivalent circuit diagram

Step 2 Null the input to the circuit

If it is a voltage source short circuit it

If it is a current source open circuit it

Step 3 Remove output voltage source From the circuit

Step 4 Connect known voltage or current source at the output terminal

Step 5 Measure the current supplied or voltage across the output source

Step 6 Determine the ratio of Voltage/ current

Common Source Amplifier

gm

vgs

r0

RD

+

-

Vin Vgs

+

-

+

-

Vo

Av= -gm (r0 // RD)

VDD

RD

Vin

Vo

Input impedance It

r0 Vt gm

vgs

Rin =

RD

Output Impedance

Rout = r0 // RD

It

r0 gm vgs Vt

RD

Common Source with Source Degenerator Circuit

+

-

Vo

+ +

gm

Vgs

r0 Vgs

-

Rs

RD

-

Vr0

+

-

VRs

I1

ID

;

;

;

;

;

1 D

D 1

D

D

S

S

S D

D

Vo = I R

I = -I

-VoI =

R

Vin = Vgs + VR

Vgs =Vin VR

-VoVR I Rs = Rs;

R

(1 )

o

D o D

D o D

D

o

D D D

o o

D D D

o D DV

D o o

Vo=Vr + VRs;

Vo = (I -gmVgs) r +I Rs;

-VoVo -gm(Vin I Rs) r I Rs;

R

-Vo -Vo -VoVo -gm(Vin Rs) r Rs;

R R R

-Vo Vo VoVo+ r gm Rsr Rs=-gmVin

R R R

-gmr R -gmRA

R r gmRsr Rs gmRs

VDD

RD

Rs

Vo

+

-

Vin

Input Impedance

Rin = gm Vgs

r0 Vgs

+

-

Rs

Vt RD

Output Impedance

Vt = Vr0 + VRs;

Vt= (ID-gmVgs)r0 +VRs

Vt= (ID + gmVRs) r0 + VRs;

Vt= (ID+ gm IDRs) r0+ IDRs;

VRs= -Vgs;

VRs= IDRs

gm

Vgs

r0 Vgs

+

-

Rs

+

+

-

VRs

Vt

It

ID

I1

RD -

Vr0

Rout Rout

Rout= r0(1+ gm Rs) + Rs r0(1+ gm Rs); Rout = (r0(1+ gm Rs) + Rs) // RD

Common Drain Amplifier

VDD

Rs

Vo

ID

gm

Vgs

r0 Vgs

-

Rs

-

Vr0

+

-

Vo

+

-

Vin

+

Vo= gm Vgs (Rs // r0);

Vin = Vgs + Vo;

Vin = Vgs (1+gm Vgs (Rs // r0));

+

V

gm (ro//Rs)A =

(1+gm(ro//Rs))

Input Impedance

gm

Vgs

r0 Vgs

+

-

Rs

Vt Rin =

Output Impedance

Vt

gm Vgs

r0

Vgs

+

-

Rs

Vgs=-Vt

A

Apply KCL at junction A

gmVgs + It = Vt/Rs + Vt/r0;

It= Vt/Rs + Vt/r0+ gmVt;

It

OUT o

1R = //r // Rs

gm

Common Gate Amplifier

VDD

RD

Rsi

Vo

Vin

I2= (Vo-(Vgs)/r0;

Vgs= Vo/-Av1; (Av1 is the gain of the circuit);

I2= (Vo+ Vo/Av1 )/r0

I2 Vo/r0

ro

Vin

gm Vgs

Vo

+

-

Rsi

Vgs RD

G

D S

I2

Vo = -Av1 Vgs;

I1=(Vgs-Vo)/r0 Vo= -Av1Vgs; (Av1 is the gain of the circuit);

I1=(Vgs-(- Av1Vgs)/r0 I1=Vgs(1+ Av1)/r0 RM = r0 /(1+ Av1)

I1

Common Gate Amplifier

Vo = -gm Vgs (ro // RD)

Vo/Vin = Av=

Apply KCL at node S

Ii +gm Vgs+ I1=0

Ii = -gmVgs-Vgs/RM Vin = Ii Rsi Vgs Vin = (-gmVgs-Vgs/RM)Rsi-Vgs

( / / )

( )

o Dgm r R

1 gm Rsi

Vo Vin

gm Vgs

+

-

Rsi

Vgs RD

G

D S

ro

Ii

I2

RM

I1

;

M M

M

M

M M

M

M

-(gmR Rsi+Rsi+R )Vin Vgs;

R

-RVgs

Vin (gmR Rsi+Rsi+R )

-RVgs -1

Vin (gmRsi+1)R (gmRsi+1)

Input Impedance

It=-gmVgs+I1;

Vt=-Vgs;

Rin = r0 // 1/gm;

Rin 1/gm;

gm Vgs

+

-

Vgs RD

G

S

Vt

It

ro

D

I1

Output Impedance

Rout =ro // RD

gm Vgs

+

-

Vgs RD

G

D S

ro

Vt

It 0

Output impedance and Small Signal gain of MOS IC amplifier

Vo

VDD

Vbias

Vin

gm1

vgs

r01

+

-

Vin Vgs

+

-

M1

M2

r02

Output Impedance of a IC MOS resistor

r02 gm vgs Vt 0

It

Small signal gain of MOS IC amplifier

+

-

Vo

Rout = r02

Small Signal Gain = -gm1(r01//r02)

Differential Amplifier

VDD

RD

VDD

RD

-Vin/2 +Vin/2

-Vo/2 +Vo/2

ID Rs

ID/2 ID/2

Virtual

ground


ADM = -gm (r0 // RD)

VDD

RD

VDD

RD

-Vin/2 +Vin/2

-Vo/2 +Vo/2

ID

Rs

ID/2+ ID ID/2+ID

Vin Vin

0

Virtual

ground

Differential Mode gain

VDD

RD

+Vin

Vo

Rout = r0


VDD

RD

VDD

RD

-Vo -Vo

ID Rss

ID/2+ ID ID/2+ID

Vin Vin

2ID Vin

VDD

RD

Rss

Vo

(1 2 )

DCM

-gmRA =

gmRss

Vin

Rout = (r0(1+ 2gm Rss) + 2Rss) // RD

COMMON MODE GAIN

Power Supply Rejection Ratio

VDD

-Vin/2 +Vin/2

-Vo/2 +Vo/2

Vb1 Vb1

Vb2

M1 M2

M3 M4

Power Supply Rejection Ratio+ Power supply rejection ratio+ = Adm/A+

Adm = -gm (ro1 // ro3)

A+= Vo/Vdd

Vdd

-Vo/2 +Vo/2

Vb1 Vb1

Vb2

M1 M2

M3 M4

M5

Power Supply Rejection Ratio+

M3 device act as common-gate amplifier

Small Signal gain of the M3 is gm3 (r03 // Rdown)

Vdd

Vo

M1

M3

M5

Rdown

M5

M1

Rdown

Rdown gm1ro1ro5

M1

Rdown

r05

r01

A+ =gm3 (r03 // gm1ro1ro5)

PSRR+ = -gm1 (ro1 // ro3)

gm3 (r03 // gm1ro1ro5)

Power Supply Rejection Ratio- Power supply rejection ratio- = Adm/A-

Adm = -gm1 (ro1 // ro3)

A-= Vo/Vss

Vss

-Vo/2 +Vo/2

Vb1 Vb1

Vb2

M1 M2

M3 M4

M5 M5

Power Supply Rejection Ratio-

Vss

Vo

Vb1

M1

M3

M5

A- = Vo/Vss

M5 transistor act as common-gate

amplifier.

The gain of M5 transistor is gm5 RD

RD= Rup // Rdown

Rup

Rdown

Rup = r03

Rdown = gm1r01r05

A- = gm5 (gm1r01r05 // r03)

PSRR- = -gm1 (ro1 // ro3)

gm5 (gm1r01r05 // r03)

Common Mode Rejection Ratio

VDD

-Vin/2 +Vin/2

-Vo/2 +Vo/2

Vb1 Vb1

Vb2

M1 M2

M3 M4

CMRR = Adm/Acm

CMRR= gm (ro1 // ro3) (1+2gm1ro5)

gm1 ro3

Adm = -gm1 (ro1// ro3);

Acm= -gm1 ro3/ (1+2gm1ro5);

M5

Input Common Mode Range

VDD

RD

Vin

Vout

VCMI

Vin

Vt

time

Voltage

VCMI

Vin

Vt

time

Voltage

VCMI


Input common-mode range

(VoV5 + Vgs1 )< VCMI


VoV5

VDD

Vb1

Vb2

M1

M3

Vo

VCMI

+

-

M5

+

-

Vgs1

VCMI (MIN)= Vgs1 + VoV5

From Vss

VDD

Vb1

Vb2

M1

M3

Vo

VCMI

+

-

M5

+

- Vgs1

VoV3

+ +

- M1

+ +

-

+

- -

VoV1

Vgs1

Vdg1 Vdg1

VCMI= VDD-|VoV3|-Vdg1

Vdg1= VoV1-Vgs1 ;

Vdg1= VoV1 (VoV1+Vt1);

Vgs1= VoV1+Vt1

VCMI(MAX) = VDD-|VoV3|-Vt1

VCMI (MIN)


VDD

RD

Vin

VCMO

VCMI

VOUT

VGS-Vt

Voltage

time

VCMO

VOUT

VGS-Vt

Voltage

time

VCMO


VDD

-Vin/2 +Vin/2

-Vo/2 +Vo/2

Vb1 Vb1

Vb2

M1 M2

M3 M4

VoV5 M5

+

-

+

-

VoV1

+

-

VoV3

Output common-mode range

VCMO(MIN) = VoV5+VoV1

VCMO(MAX) = VDD-VoV3

(VoV5+VoV1 )< VCMO< (VDD-VoV3)

Output Voltage Swing

VDD

-Vin/2 +Vin/2

-Vo/2 +Vo/2

Vb1 Vb1

Vb2

M1 M2

M3 M4

VoV5 M5

+

-

+

-

VoV1

+

-

VoV3

Maximum Output Voltage Swing

Differential End

2(VDD-(VoV5 +VoV1+| VoV3|))

Telescopic OTA

Mid Band Gain= ?

M1

M3

M5

M7

M2

M4

M6

M8

VDD

M9

Vb1

Vb2

Vb1

Vb4

Vb3

Vin- Vin

+

Vb2

Vb3

AV=-gm1 RD

RD= Rup // Rdown

Rdown

VO+ VO

-

Vin

RD

M1

VO

Vin+

M1

M3

M5

M7 Vb1

Vb2

Vb3

Virtual

ground

Rup

Single stage

Mid Band Gain of a Telescopic OTA

Rup

M5

M7 Vb1

Vb2

Vo

M1

M3 Vb3

Rdown

Vin+

M5 looks like common source with

degenerator circuit; its output

resistance is (1+gm5ro7)ro5

gm5ro5ro7 Rup gm5ro5ro7

M5

M7 Vb1

Vb2

Vo Rup

M5 r05

r07

Rup

S

D

Mid Band Gain of a Telescopic OTA

M1

M3 Vb3

Rdown

M3

Rdown

r01

r03



resistance is (1+gm3ro1)ro3

gm3ro1ro3

Rdown gm3ro1ro3

Overall gain of the Telescopic OTA is

-gm1 RD

RD= Rup // Rdown

Overall Midband gain -gm1 (gm3ro1ro3)// gm5ro5ro7

Power Supply Rejection Ratio+

Power supply rejection ratio+ = Adm/A+

Adm = -gm1 (gm3ro1ro3)// gm5ro5ro7

Rup

M5

M7 Vb1

Vb2

Vo

M1

M3 Vb3

Rdown

Vdd

A+ =gm7 RD RD = Rup // Rdown

Rup = gm5ro5ro7 and Rdown = gm3ro1ro3

Hence A+ =gm7 (gm5ro5ro7 // gm3ro1ro3)

PSRR+ = -gm1 (gm3ro1ro3)// gm5ro5ro7 gm7 (gm5ro5ro7 // gm3ro1ro3)

Power Supply Rejection Ratio-

Vss

A- = gm1RD RD = Rup // Rdown

Rup gm5ro5ro7 Rdown gm3ro3gm1ro1ro9

Vo

Rup

M5

M7 Vb1

Vb2

Vo

Rdown

M1

M3 Vb3

Vb4 M9 M1

R1

r01

r09

M3 Vb3

Rdown

R1

r03

gm3ro3R1

gm1ro1ro9

Rdown gm3gm1ro1ro3ro9

PSRR- =Adm/A-

PSRR- = -gm1 (gm3ro1ro3)// gm5ro5ro7 gm1 (gm3gm1ro1ro3ro9 // gm5ro5ro7)

Common Mode Rejection Ratio

CMRR = Adm/Acm

Vin+

M1

M3

M5

M7 Vb1

Vb2

Vb3

Virtual

ground

Rup

Single stage

Adm -gm1 (gm3ro1ro3)// gm5ro5ro7

Vo

Vin+

Acm -gm1 (ro3//gm5ro5ro7)

(1+2gm1 ro9) Rup

M5

M7 Vb1

Vb2

Rdown

M1

M3 Vb3

Vb4 M9

CMRR ((gm1 (gm3ro1ro3)// gm5ro5ro7 ) (1+2gm1 ro9))

gm1 (ro3//gm5ro5ro7)

Input Common Mode range

VCMI (MIN) = VOV9 + Vgs1

M5

M7 Vb1

Vb2

Vo

M1

M3 Vb3

VDD

M9

VCMI (MAX) = VDD- |VOV7|- |VOV5| - |VOV3| +Vt1

VCMI (MIN) < VCMI < VCMI (MAX)

Output Common Mode range

M5

M7 Vb1

Vb2

Vo

M1

M3 Vb3

VDD

M9

VCMO(MIN) = VOV9 + VOV1 + VOV3

VCMO(MAX) = VDD- |VOV7 | - | VOV5 |

VCMO (MIN)

Output Voltage Swing

M5

M7 Vb1

Vb2

Vo

M1

M3 Vb3

VDD

M9

For Differential End

2(VDD- |VOV7 | - | VOV5 |- VOV3 VOV1 - VOV9)

Output Voltage Swing is

Mid band gain of Folded Cascoded OTA

VDD

M1

M3

M5

M7 M2

M4

M6

M8

VDD

Vb1

Vb2

Vb1

Vb4

Vb3

Vb2

Vb3 Vin

+ Vin-

M9 M10

Vb4

Vo+ Vo-

Vb5 M11

Mid band gain=?

Vin

RD

M1

AV=-gm1 RD

Vin

VO Vo

Rdown

Rup M1

M3

M5

M7

Vb1

Vb2

Vb3

M9

Vb4

Virtual

Ground

Single Stage

RD= Rup // Rdown

Overall Mid band gain


degenerator circuit; its output resistance is

(1+gm7ro9)ro7 gm7ro7ro9 Rup gm7ro7ro9

M7

M9 Vb1

Vb2

Vo Rup

M7 r07

r09

Rup

S

D M1

M3 Vb3

Rdown

M5

M3

Rdown

r05

r03

r01



resistance is (1+gm3(ro1 // r05))ro3 Rdown gm3 ro3 (ro1//ro5)

-gm1 RD RD= Rup // Rdown

Overall Midband gain -gm1 (gm3 ro3 (ro1//ro5) //(gm7ro7ro9))

Power Supply Rejection Ratio+ Power supply rejection ratio+ = Adm/A+

Mid band gain of Simple Two Stage OTA

VDD

M1 M2

VDD

M3

Vb3 Vin-

Vin+

Vb1 M4

VDD

M5 M6

M7 M8

Vb1

Vb2 Vb2

Stage 1 Stage 2

Vo- Vo+

Overall Midband gain

Vin

M1

M3

V1 M5

M7

Vo+

V1

Stage 1 Gain

AV1=-gm1 (ro1 // ro3)

Stage 2 Gain

AV2= -gm5 (ro5 // ro7)

Overall gain = AV1 AV2

= gm1 gm5 (ro1 // ro3) (ro5 // ro7)

Mid band gain of Two Stage OTA with telescopic first stage

M1

M3

M5

M7

M2

M4

M6

M8

VDD

M9

Vb1

Vb2

Vb1

Vb4

Vb3

Vin- Vin

+

Vb2

Vb3

M10

M12

Vb5

Vo-

VDD VDD

Vo+

Vb4 M11

Stage 2 Stage 1

Mid band gain

M1

M3

M5

M7 Vb1

Vb2

Vb3

Vin

Stage 1

V1 M9

M11 Vb4

Vo

V1

Stage 2

AV1 -gm1 (gm3ro1ro3)// gm5ro5ro7

AV2= -gm9 (ro9 // ro11)

Overall Midband gain = AV1 AV2

gm1 gm9((gm3ro1ro3)// (gm5ro5ro7)) (ro9 // ro11)

Mid band gain of Two Stage OTA with folded cascode first stage

VDD

M1

M3

M5

M7 M2

M4

M6

M8

VDD

Vb1

Vb2

Vb1

Vb4

Vb3

Vb2

Vb3 Vin

+ Vin-

M9 M10

Vb4

M11

M13 Vb5

Vo+

Stage 2

VDD

M12

M14 Vb5

Vo-

VDD

Stage 1

Vb6 M15

Mid band gain

M1

M3

M5

M7

Vb1

Vb2

Vb3

M9

Vb4

Virtual

Ground

Stage 1

M11

M13 Vb4

Vo

V1

Stage 2

V1

Av1 -gm1 ((gm3 ro3 (ro1//ro5) ) //(gm7ro7ro9)) Av2=-gm11 (ro11 // ro13)

Overall gain gm1 gm11 (gm3 ro3 (ro1//ro5) //(gm7ro7ro9)) (ro11 // ro13)

THE END

UNIT V.pdf

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