Unit 9- Combinational Logic Systems 1

Digital Electronic Systems Unit 9

COMBINATIONAL LOGIC SYSTEMS 1Introduction

When logic gates are connected together to produce a specified output for certain specified combinations of input variables, with no storage involved, the resulting circuit is a combinational logic circuit. In combinational logic, the output is at all times dependant on the input levels.

This unit introduces a fundamental combinational logic function – the adder. This is the most important component of the Arithmetic Logic Unit in computing.

Adders

The heart of the digital computer is the arithmetic logic unit (ALU). In practice, two main operations are performed here: addition and subtraction. The basic element used for both addition and subtraction is the adder. When the sum of two bits is greater than 1, a carry of 1 is generated. The carry is transferred to the next pair of bits and is summed with them.

For example:

An …… A6 A5 A4 A3 A2 A1 A0

Cn + Bn …… C6 B6 C5 B5 C4 B4 C3 B3 C2 B2 C1 B1 C0 B0

n …… 6 5 4 3 2 1 0

To design a logic system to perform addition, each addition operation must be performed individually for every bit position in turn. Each adder generates a sum and a carry out.

Half Adder

Examination of the above example shows that the first pair of bits is not summed

with a previous carry. There are two outputs generated, a sum and a carry . A half adder will perform this operation. A half adder accepts two binary digits as inputs and produces two outputs, a sum bit and a carry bit. The Truth table for a half adder is shown below.

Input A Input B Sum Carry C0 0 0 00 1 1 01 0 1 01 1 0 1

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The summary symbol for a Half Adder is shown below.

Before implementing the half adder, first write down the expressions for the outputs, and C. From the Truth table

and

The logic diagram for a Half Adder is shown below.

The sum function is an Exclusive OR (XOR) gate. This means that the Half Adder can be summarised to the logic circuit shown below.

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Full Adder

Consider again the example of the addition of two binary numbers. For the second least significant bit addition, the bits are added to a carry in . For this addition and for subsequent bit additions there will be a carry in from the previous addition. To perform this addition, a full adder is used. A full adder accepts two input bits and an input carry and generates a sum bit and an output carry bit.

The Truth table for a full adder is shown below:

Inputs OutputsA B Cin Cout

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

The functions sum and Carry are now built using various methods. The first step is to derive the Boolean expression for the sum and carry from the Truth Table

and

The logic diagram for these functions is shown below.

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It can be seen that by comparing the half adder logic diagram with that of the full adder shown above, the full adder can be constructed using two half adders and one 2-input OR gate appropiately connected as illustrated by the logic diagram below.

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Note that when the carry in then the Full Adder acts like a Half Adder. This can be proven by substituting into the Boolean expression.

A full adder can also be built using AND/OR/INVERTER (AOI) logic. Consider again the original Boolean expressions. Minimise these expressions by Karnaugh mapping.

These minimised functions are now built using AND/OR/INVERTER (AOI) logic.

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Parallel Adder

Two or more full adders are connected to form parallel binary adders. Consider the case of a four bit adder (four bits is sometimes called a nibble).

A3 A2 A1 A0

B3 C2 B2 C1 B1 C0 B0

3 2 1 0

A four-bit adder is implemented as follows.

This type of adder is called a ripple carry adder. A ripple carry adder is one in which the carry output of each adder is connected to the carry input of the next higher order stage (a stage is one full adder). The sum and the output carry of any stage cannot be produced until the input carry occurs. This results in a time delay in the addition process.

Say that is the propagation delay of a typical logic gate.

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The Half adder propagation delays are

The Full adder propagation delays are

The n-bit Ripple carry adder propagation delays are

Therefore the more bits on a ripple carry adder the longer the time delay before a sum is produced.

A method of speeding up the addition process by eliminating the ripple carry delay is called look-ahead carry addition. The look-ahead carry adder anticipates the output carry of each stage, based on the input bits of each stage. This would be performed by separate carry look-ahead logic.

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Cascading adders

The following is an example where two four-bit adders are cascaded together. The final carry out is the carry out from the bit position. In practice when cascading adders, one should check that the propagation delay of the overall adder is not excessive for the application in question. Note that four-bit adders are available in IC form (e.g. 74LS83A and 74LS283A).

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Ex. 1 (Part of a 20 mark question)

(a) Draw the truth table for a Full Adder.(b) Derive the minimised Boolean expressions for each of the outputs of a Full Adder.(c) Draw the logic diagram for a Full Adder implemented using AND/OR/INVERTER logic elements.

[14 marks]

Ex. 2 (Part of 20 Mark Question)(a) Draw the logic diagram and the truth table for a Half Adder implemented using AND/OR/INVERTER logic elements.

[4 marks]

Ex. 3 (Part of 20 Mark Question)(a) Explain the main difference between combinational logic circuits and sequential logic circuits

[3marks]

(b) Draw the truth table for a Full Adder and show how two Half Adder units may be combined to implement a Full Adder.

[9 marks]

(c) Draw the logic diagram and the truth table for a Half Adder implemented using AND/OR/INVERTER logic elements.

[4 marks]

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Unit 9- Combinational Logic Systems 1

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