Microelectronics Group of IPHC Belle II visiting IPHC - 24/10/2013Claude COLLEDANI.
ULTIMATE: Preliminary Test Results IPHC-LBNL Phone Conference
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Transcript of ULTIMATE: Preliminary Test Results IPHC-LBNL Phone Conference
ULTIMATE: Preliminary Test Results
IPHC-LBNL Phone Conference
Outline Ultimate test status
Analogue outputs (tested by Mathieu)
Pixel array + Discriminators (tested by Mathieu)
Zero suppression logic (tested by Gilles)
Synchronous readout of N Ultimate (proposed by Kader & Gilles)
DAQ development for BT (Gilles et al.)
STARSTARIPHC [email protected] 204/05/2011 Tel meeting LBNL/IPHC
Ultimate: test status
Ultimate sensors have been received at IPHC March 24th 2011 1 wafer (No. 4) with HighRes EPI 15 µm 1 Diced wafer (No. 5) thinned down to 120 µm with HighRes EPI 20 µm
AMS tested each wafer by using integrated PCM (test 5 sites/wafer) Process parameters are out of specification ranges in 2 sites on wafers No.4 and 5
9 chips were bonded on PCB. All have passed the test of power on and JTAG 1 for PLL test 1 for regulator test 7 for analogue & digital characterization
Power on test results: IddA ~150 mA, IddD ~70 mA (low activity) 730 mW (3.3 V) ~150 mW/cm²
In chip regulator for Vclamping worksin 5 tested chips
4 chips have problem Still investigating
STARSTARIPHC [email protected] 304/05/2011 Tel meeting LBNL/IPHC
Ultimate: Analogue Output
Pixel array scan at 40 MHz, T sensor ~ 20°C JTAG Nominal value VddA = 3.3 V Vclamping provided by in chip regulator Good noise uniformity, ENC ~ 14 e-
Gain similar to Mimosa26 ~ 65 µV/ e-
CCE is not sensitive to temperature variation
ChipsCalib peak
(UADC)ENC (e-)
CCE
Seed pixel 2x2 pixels 3x3 pixels 5x5 pixels
Ultimate 395 13.8 24% 62% 82% 94%
Mi22 AHR (S7) 458 13.6 20% 52% 72% 87%
Mimosa26 391 12 23% 59% 77% 89%
Ultimate Sensor Calib peak
(UADC)ENC (e-)
CCE
Seed pixel 2x2 pixels 3x3 pixels 5x5 pixels
~20 °C 395 13.8 24% 62% 82% 94%
~35 °C 385 16.4 24% 62% 83% 96%
~45 °C 369 20.7 23% 63% 85% 99%
STARSTARIPHC [email protected] 404/05/2011 Tel meeting LBNL/IPHC
Ultimate: Analogue Output (2)
Sensor performances remaining almost the same when VddA varies from 3.3 to 3 volt
8 columns run at 160 MHz Problem 1:
Large CDS (Vread-Vcalib) offset value Analogue output is distributed by READ signal
Problem identified Coupling between the bias of the output buffer
& READ in the layout Workaround: possible but need investigation
Problem 2: Marker (MKA) despaired at 160 MHz (156 MHz is ok)
READ period CALIB period
Analogue Output
STARSTARIPHC [email protected] 504/05/2011 Tel meeting LBNL/IPHC
Ultimate: Pixel Array + Discriminators
Temporal noise uniformity TN ~ 0.96 mV
FPN Without offset to 0 adjustment With offset to 0 adjustment, FPN ~ 0.55 mV
STARSTARIPHC [email protected] 604/05/2011 Tel meeting LBNL/IPHC
Ultimate: Pixel Array + Discriminators (2)
A B
C D
No strange behaviours observed
STARSTARIPHC [email protected] 704/05/2011 Tel meeting LBNL/IPHC
Ultimate: Pixel Array + Discriminators (3)
A B
C D
1.003 0.5747 0.9474 0.4896
0.9243 0.4768 0.8995 0.4707
STARSTARIPHC [email protected] 804/05/2011 Tel meeting LBNL/IPHC
Ultimate: Pixel Array + Discriminators (3)
Observed points Large offset in every 16 rows
Still within 4 sigma Structure in the design, try to minimize
Offset dispersion in column & row "half moon" Not seen in Mimosa26
Offset is frequency & temperature sensible Power supply to 3 V
VddA set to 3 V, Ultimate still works with similar performances VddD set to 3 V, Ultimate losses its performances need more investigations
STARSTARIPHC [email protected] 904/05/2011 Tel meeting LBNL/IPHC
Ultimate: Zero suppression logic
Check (but not an exhaustive test) Conditions:
VddD = 3.3V, Frequency at 150 MHz in most case (due to limitation on test board and tight planning)
Test of critical patterns (defined by Guy) – Done on 5000 frames Test N° 1
Line pattern 0 0 Line pattern 1 Discri 0 & 959 = 1
Test N° 2 Line pattern 0 Discri 0 & 959 = 1 Line pattern 1 0
Test N° 3 Line pattern 0 Discri 0, 63, 64, 127, 128 = 1 Line pattern 1 0
Test N° 4 ( Test limited to 500 frames ) Line pattern 0 Shift emulated hit on a single discri ( 0 .. 959 ) Line pattern 1 0
Test N° 5 ( Test limited to 500 frames ) Line pattern 0 0 Line pattern 1 Shift emulated hit on a single discri ( 0 .. 959 )
SUZE works without error
STARSTARIPHC [email protected] 1004/05/2011 Tel meeting LBNL/IPHC
Synchronous readout of N Ultimate (on a ladder)
Standard protocol with Start synchro / clock not applicable Error in Ultimate ( bad clock used to sample Start 80 MHz instead of 160 MHz )
First workaround Difficult to implement Synchronize also Reset with clock ( Reset & Start ) Reset is a slow control signal ( from boards to Ultimate ) NOT a fast signal Never tested
Second workaround Easier to implement & Validated at lab Reset all Ultimates Load JTAG Start clock ( gate controlled by flip/flop to get first clock cycle as full period ) Send Start signal ( synchronized on clock falling edge as usual )
STARSTARIPHC [email protected] 1104/05/2011 Tel meeting LBNL/IPHC
Status of DAQ for Beam Test (BT)
Done Use FW developed for Mimosa26 Upgrade to solve N x Ultimate synchronization problem done Test of FW at 150 MHz done with one Ultimate
To be done Check trigger handling FW running @ 150 MHz Upgrade of DAQ SW & Monitoring
Remark All tests will be performed at 150 MHz because of limitation on test boards
No time to investigate BT foreseen this summer
ULTIMATE: Latch up free design
IPHC-LBNL Phone Conference
Outline Latch-up free SRAM test setup status
Latch up free digital design status
STARSTARIPHC [email protected] 1304/05/2011 Tel meeting LBNL/IPHC
Latch-up free SRAM design status
Latch-up free SRAM (256x8) is designed by a Ph.D student in the last year. BUT: 4 metal layers have been used
If the evaluation of the designed module is OK Redesign with only 3 metal layers! We will extend it to the size of the memory used for Ultimate (2x2 x (2048x16))
Planning proposed last year has to be revisited which was under estimated!
SRAM test status: HW & SW needed to test SRAM
HW ( G. Doziere + O. Clausse ) Mother board Power supply, buffers, connectors Daughter board SRAM holder ( SIMM format )
FW & SW FW Pattern generator & DAQ with NI Flex RIO ( C. Santos ) SW RAM test routines in C ( G. Doziere )
Test planning HW stopped because Guy has “an accident” ( broken knee ~ 5 weeks )
Boards ready for test at lab mid/end July FW & SW
FW Done SW To be done ( M. Specht?/G. Claus?) Ready for mi July
STARSTARIPHC [email protected] 1404/05/2011 Tel meeting LBNL/IPHC
Latch up free digital design status
How? increase the spacing between Nplus and Pplus layer
Stretching all the AMS digital standard cells by 3 µm All the layout for AMS Standard cells have been stretch
by hand or by using skill program (more than 250 cells) Abstract views have been created in a new library A trial has been done:
Integration of these abstract in SOC Encounter flow (Digital placer and rooter)
Design of SLOWCONTROL (JTAG) block with the stretched cells as a test case DRC, LVS without special problem
Next steps: extend this procedure to all mixte and digital blocs
Main difficulties: Limited space: Ultimate already used the maximum reticle size. All above modifications
have to feet to the Ultimate size. Please pay attention that the memory will have 50% size incensement!!!
Memory is a unknown bloc for us. Some questions such as how to simulate it with other digital blocs, how to test it (we have to use the same PAD ring), … are not solved
Several iterations have to be planned due to optimisation of the size & timing (160 MHz)
At least 6 month of development13
µm
16 µ
m