Tsu‐Jae King Liu

Extending the Era of Moore’s Law

Tsu‐Jae King LiuDepartment of Electrical Engineering and Computer Sciences

University of California, Berkeley

September 11, 2017SPIE Photomask Technology + EUV Lithography Conference

14 nm chip X‐SEM from www.intel.com/content/dam/www/public/us/en/documents/pdf/foundry/mark‐bohr‐2014‐idf‐presentation.pdf

IC Technology AdvancementGordon E. Moore, “Cramming more Components onto Integrated Circuits,” Electronics, pp. 114‐117, April 1965

• The minimum cost point moves to a larger number of components per IC over time, with advancements in manufacturing technology.

2

MarketGrowth

Investment

TransistorScaling

Lower Cost/ComponentHigher Performance

Outline

• Transistor Scaling to the Limit

• Extending the Era of Moore’s Law

• Summary

Transistor Basics

GATE VOLTAGE

log (CURRENT)

0 VTH

IOFF

Metal‐Oxide‐Semiconductor (MOS)Field‐Effect Transistor (FET)

Gate length, LGION

VDDElectron Energy Band Profile

increa

sing

E

distance

n(E) exp (‐E/kT)

SourceDrain

increasingVGS

Inverse slope is subthreshold swing, S[mV/dec]

4

invD QvWI )( THGSoxinv VVCQ

effv

Channel width, W

ON

OFF

Complementary MOS Devices & Circuits

0 1

1 0

STATIC MEMORY (SRAM) CELL

DS

G

DS

G

CIRCUIT SYMBOLSN‐channelMOSFET

P‐channelMOSFET

0 V

VDDS

S

DD

CMOS INVERTER CIRCUIT

VIN VOUT

VOUT

VIN0 VDD

VDD

INVERTERLOGIC SYMBOL

BIT LINE

WORD LINE

BIT LINE

CMOS NAND GATE

NOT AND (NAND)TRUTH TABLE

or or

OFF

ONON if VG<VS‐VTHON if VG>VS+VTH

0 V=VDD

VDD

=0 V

5

CMOS Technology Scaling

90 nm node 65 nm node 45 nm node 32 nm node

T. Ghani et al.,IEDM 2003

K. Mistry et al.,IEDM 2007

P. Packan et al.,IEDM 2009

XTEM images with the same scale courtesy V. Moroz (Synopsys, Inc.)

(after S. Tyagi et al., IEDM 2005)

6

strained Si eff

high-k/metal gate Cox

Design for Manufacturing

SRAM bit‐cell layouts

45 nm90 nm 65 nm

courtesy Mike Rieger (Synopsys, Inc.)

7

C. Webb, Intel Technology Journal, vol. 12, No. 2, pp. 121‐130, 2008

PU

PD

PU

PD

PGPG

PUPD

PU PDPG

PG

Impact of Misalignment

Actual layout(corner rounding)

Actual layout w/ vertical misalignment(channel width variations due to active jogs)

W reduced W increased

Actual layout w/ lateral misalignment(gate length variations)

Lg reduced Lg increased

PD

PG

PG

PDPU

PU

6-T SRAM Cell

Desired layout(6‐T SRAM cell)

8

Actual layout after active patterning

Double Patterning of Gate

PD

PG

PG

PDPU

PU

Actual layout after 1st gate patterning

Actual layout after 2nd gate patterning(no gate length variation)

6-T SRAM Cell

Desired layout(6‐T SRAM cell)

9

Impact of Variability on SRAM

• VTH mismatch results in reduced static noise margin. lowers cell yield and/or limits VDD scaling

BUTTERFLY CURVES

SN1 SN2

STATIC MEMORY (SRAM) CELL

BIT LINE

WORD LINE

BIT LINE

VSN2

VSN10 VDD

VDD

SNM1

SNM2

Pre‐charged to VDD

Immunity to short‐channel effects needed!

10

Short‐Channel Effects

• VTH decreases with decreasing Lg and with increasing VDS:

Body

Gate

Drain

CoxCdep

Source

SourceDrain

log ID

VGS

11

• Increased capacitive coupling between Gate and channel provides for better Gate control, hence reduced SCE

Source

DrainGate

LG

FinFET/Tri‐Gate Transistor

• Superior gate control higher ION/IOFF or lower VDD

WFin

HFin

GATE

SOURCE

DRAIN20 nm

10 nm

Y.‐K. Choi et al., (UC Berkeley) IEDM 2001

15nm Lg FinFET

D. Hisamoto et al. (UC Berkeley), IEDM 1998

Intel Corp., May 2011

log ID

VGS

ION

VDD

• Multiple fins can be connected in parallel to achieve higher ON‐state drive current.

ox

total

CCS

12

Spacer Lithography

BOX

SOISiGe

1. Deposit & pattern sacrificial layer

BOX

SOISiGe

2. Deposit mask layer (SiO2 or Si3N4)

BOX

SOISiGe

3. Etch back mask layer to form “spacers”

BOX

fins

4. Remove sacrificial layer;etch SOI layer to form fins

Note that fin pitch is 1/2 that of patterned layer

a.k.a. Sidewall Image Transfer (SIT) and Self‐Aligned Double Patterning (SADP)

Y.‐K. Choi, T.‐J. King, and C. Hu, IEEE Trans. Electron Devices, Vol. 49, No. 3, pp. 436‐441, 2002

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MOSFET Evolution32 nmplanar

P. Packan et al. (Intel), IEDM 2009

beyond 7 nmstacked nanowires?

C. Dupré et al. (CEA‐LETI)IEDM 2008

Stacked gate‐all‐around (GAA) FETs achieve the highest layout efficiency.

22 nmthin body

Intel Corp.

FinFET:

FD‐SOI:

K. Cheng et al. (IBM), VLSI Symp. 201114

Stacked nanosheets

N. Loubet et al. (IBM, Samsung, GLOBALFOUNDRIES)Symp. VLSI Tech 2017

J. Wang et al., IEDM Technical Digest, pp. 707‐710, 2002

Channel‐Length Scaling Limit• Quantum mechanical tunneling sets a fundamental scaling

limit for the channel length (LC).

SOURCE DRAIN

EC

EC

If electrons can easily tunnel through the source potential barrier, the gate cannot shut off the transistor.nMOSFET Energy Band Diagram(OFF state)

15

1‐nm Gate Length MOSFET• A 1‐nm‐diameter CNT‐gated

MoS2 MOSFET is demonstrated with ON/OFF current ratio ∼106(VDD ∼1 V)Heavier meff (0.45m0 vs. 0.26m0 in Si)Bandgap energy ∼1.3 eV

S. B. Desai et al., Science, Vol. 354, No. 6308, pp. 99‐102, 2016

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Future Logic Switches

Steeper switching behavior needed (S < 60mV/dec)

Today

Energy

Delay

Drain Current

Gate Voltage

Future

Future

Today

1/S

• Higher ION/IOFF ratio lower minimum Energy/op

17

Outline



• Summary

Self‐Aligned Double PatterningCross‐sectional View Plan View

19

20Sang Wan Kim02/25/2016

Samsung, EUVL Symposium 2009ASML, SPIE Advanced Lithography 2012

SingleExposure

LELE SingleSpacer

DoubleSpacer

0

1

2

3

4

5

Nor

mal

ized

Cos

t and

Ste

ps

Cost Steps

Multiple‐patterning techniques have extended Moore’s Law beyond the lithographic resolution limit at increasing cost

“The sheer cost and complexity of this lithographic solution could dissuade chipmakers from jumping to future nodes, thereby stunting the growth rates of the IC industry.”

‐ Semiconductor Engineering, April 17th, 201420

Tilted ion implantation (TII) Approach• A sub‐lithographic damage region can be achieved by tilted

ion implantation (TII) + photoresist/hard mask– self‐aligned to pre‐existing mask features on surface

21

Impact of TII on SiO2 Etch Rate

0 10 20 30 40 500.0

0.3

0.6

0.9

1.2

1.5

Etch

rate

[Å/sec

]

SiO2 Depth [Å]

2E14

3E14

0.4

0.8

1.2

1.6

2.0

2.4

no implant

2E14D

amage [x10

22/cm3]

3E14

~9X~6X

Ar+ implant conditions: 15° tilt; 1.5 keV; dose = 0, 2 or 3 x 1014/cm2

Symbols & solid lines: etch rate in 200:1 DHF

Dotted lines: damage profile (SRIM)

S. W. Kim et al., SPIE Advanced Lithography 2016

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hard mask

SiO2

• Thermal SiO2: masking layer• Formation of linear a-Si hard-mask

features by spacer patterning

Double‐Patterning by TII

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Si

Silicon

αα

Wtrench

θ

x x

yhard mask

SiO2



• First implant: positive tilt anglex ≅ Wtrench – y(tan(θ) – cot(α))

24

hard mask

SiO2




• Second implant: negative tilt anglex ≅ Wtrench – y(tan(θ) – cot(α))


25

Si

Silicon

α

WfinWfinx xx x

yhard mask

SiO2




• Second implant: negative tilt anglex ≅ Wtrench – y(tan(θ) – cot(α))

• Selective removal of damaged SiO2• Si substrate dry etch

Wfin ≅ 2y(tan(θ) – cot(α)) – Wtrench


26

Proof of Concept: Single Implant

• Sub‐lithographic features (~45 nm) achieved by 15° tilt, 3.0 keV Ar+ implant into 10 nm‐thick SiO2 hard mask dilute HF etch Si dry etch

Cross‐sectional Scanning Electron Micrographs

S. W. Kim et al. (UC Berkeley), SPIE Advanced Lithography 2016

27

remaining a-Si

Si substrate

etched a-Si15°

①②

③

Ar-ion implantation with θ = 15°

Si substrate

Self‐Aligned Nature of TII Patterning

• The TII‐defined edge closely tracks the HM edge

= a‐Si hard mask = un‐etched c‐Si = etched c‐Si

P. Zheng et al. (UC Berkeley), IEEE Transactions on Electron Devices, vol. 64, no. 1, pp. 231‐236, 2017

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Line‐Edge Roughess Comparison

• TII improves low‐ and mid‐frequency line‐edge roughness

36 samples, 2.74 µm long

P. Zheng et al. (UC Berkeley), IEEE Transactions on Electron Devices, vol. 64, no. 1, pp. 231‐236, 2017

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TII Patterning Resolution LimitP. Zheng et al. (UC Berkeley), IEEE Transactions on Electron Devices, vol. 64, no. 1, pp. 231‐236, 2017

Error bars represent 1 standard deviation

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• TII can be used to pattern features as small as 10 nm.

Double Tilted Implant Results

• Local pitch‐halving achieved with ±15° tilt, 3.0 keV Ar+ implants• ~21 nm half‐pitch of the etched Si features

Cross-sectional SEM Plan-view SEM

S. W. Kim et al. (UC Berkeley), SPIE Advanced Lithography 2016

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①②

③

a-Si

Si substrate

15°

①

②

③

LTO

Silicon

Double‐Patterning ApproachesSpacer lithography (SADP)

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Double‐Patterning Approaches

Silicon

PR PR

Silicon

SiO2 (Oxidation)

PR

Spacer lithography (SADP) Tilted Ion Implantation (TII)

33

SiO2 (Oxidation)

Silicon

Hard mask (CVD)

SiO2 (Oxidation)

Silicon

SiO2 (Oxidation)

Silicon

Silicon Silicon

Tilted Ion Implantation (TII)Spacer lithography (SADP)

Double‐Patterning Approaches

• The cost of TII double‐patterning can be only ~60% of the cost of SADP.

Sub‐Lithographic Hole FormationS. W. Kim et al. (UC Berkeley), Journal of Vacuum Science & Technology B, vol. 34, 040608, 2016

Future Work: 2D Patterning by TII1.Coat IC layer with HM layer;

2.Perform multiple litho+TII processes in sequence, such that each litho+TII process forms a latent 1D pattern in the HM layer;

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< Pmin/2

Pmin/2 A

Pmin/2

C Pmin/2

B

Pmin/2

Pmin/2

< Pmin

< Pmin/2

< Pmin

< Pmin/2

Pmin/2 D

Implant Direction

3.Selectively etch the HM layer to form the composite 2D pattern;

4.Transfer the 2D pattern to the IC layer by a selective etch process.

Outline



• Summary

Summary

• There’s still plenty of room for CMOS technology scaling!– Advancements in transistor structures and materials will enable continued miniaturization and voltage scaling.

• Innovations to mitigate the challenge of growing cost of patterning are needed to extend the era of Moore’s Law

Market Growth

Investment

38

NewInnovations

Lower Cost/FunctionLower Power

Acknowledgements

• TII‐Enhanced Lithography:– Dr. Sang Wan Kim (now with Ajou University)– Dr. Peng Zheng (now with Intel Corporation)– Dr. Leonard Rubin (Axcelis Technologies)– UC Berkeley Marvell Nanofabrication Laboratory– Funding from Applied Materials, Lam Research, National Science Foundation

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3‐D NAND Flash Technology

• Density scaling is not driven by lithography.• Aspect ratios of etched and filled features are large (>40:1).

Vertical FETs (vFETs):

• Poly‐Si is used as the semiconductor material.

• Lithography steps for multiple memory layers are shared.

http://www.monolithic3d.com/uploads/6/0/5/5/6055488/695394.jpg?388 40

J. J.‐Q. Lu et al., Future Fab Int’l, Issue 23, 2007

Heterogeneous IntegrationEnhanced performance & functionality in a compact form factor

• Separate layer fabrication processes

MEM relay

Metal

Si substrate

CMOS layer

Interconnects

Insulator

• Integrated fabrication process

41V. Pott et al., Proc. IEEE, Vol. 98, 2010

IC Technology Advancement

Time

D. C. Edelstein, 214th ECS Meeting, Abstract #2073, 2008

S. Natarajan et al. (Intel), IEDM 2014

Intel’s 14nm CMOS technology

• Advanced back‐end‐of‐line (BEOL) processes have air‐gapped interconnects

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Reconfigurable Interconnect

• A bi‐stable switch is implemented using multiple metal layersVias are for electrical connection and flexural elements for a more compliant electrode, for lower programming voltage.

• Small footprint due to vertically oriented movable electrode, and shared actuation and contacting electrodes across the array

• A non‐linear device can be integrated to prevent sneak leakage current in a cross‐point array

I/O 1

Program 1

Program 1

Program 1

Movable electrode

Bit Line (BL)

I/O 0

Program 0

Program 0

Program 0

K. Kato et al., IEEE Electron Device Letters, vol. 37, no. 12, pp. 1563‐1565, 2016.

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LUT Performance ComparisonArea (μm2)

Program energy (fJ)

Programdelay (ns)

Readout energy (fJ)

Readout delay (ns)

10−1

100

101

102

10310−1

100101

102103

10−210−1

100101

102

100

101

102

103

104

101

102

103

104

105

CMOS+NEMS (F = 20nm)CMOS (F = 45nm)

More compact, faster, and energy‐efficient than CMOS!

K. Kato et al., IEEE Electron Device Letters, vol. 37, no. 12, pp. 1563‐1565, 2016

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