Transmission gate latches. MSL with unprotected input (Gerosa et al. 1994), Copyright © 1994 IEEE.
40
Transmission gate latches (a) (c) Clk D Q Q S (b) Q S S Clk D Clk D
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Transcript of Transmission gate latches. MSL with unprotected input (Gerosa et al. 1994), Copyright © 1994 IEEE.
Transmission gate latches
(a) (c)
Clk
D Q QS
(b)
QS
SClk
D
Clk
D
MSL with unprotected input(Gerosa et al. 1994), Copyright © 1994 IEEE
D
Q
Clk Clk1
Clk
QMSM SS
Clk 1
Clk1
Clk
MSL with input gate isolation(Markovic et al. 2001), Copyright © 2001 IEEE
D
Q
SM SS Q
Clk 1Clk
Clk Clk1
Clk1
Clk
QM
Clk1
removed
Sources of noise affecting the latch state node(Partovi in Chandrakasan et al. 2001), Copyright © 2001 IEEE
D2
3
2
1
Distantdriver
4 5
1
DVSS
VDD
QS
1 noise on input
2 leakage
3 -particle and cosmicrays
4 unrelated signal coupling
5 pow er supplyripple
Dynamic latches with gate isolation: (a) transmission gate, (b) C2MOS
D D
(a) (b)
Clk
Clk
Q QClk
Clk
removed
C2MOS latch (C2MOS)(Suzuki et al. 1973), Copyright © 1973 IEEE
D Q
Clk1
Clk
Clk
Clk 1
Clk
Clk1
Clk
QMClk
Clk 1
Clk1
Clk
Comparison of MSLs: (a) timing, (b) energy
(a) (b)
Hybrid-latch flip-flip(Partovi et al. 1996), Copyright © 1996 IEEE
D
Q
ClkS
Clk1
Semidynamic flip-flop(Klass 1998), Copyright © 1998 IEEE
Q
Clk
Clk 1
S
I
D
Clk
Clk
Illustration of SDFF output glitch
Sense-amplifier-based flip-flop(Montanaro et al. 1996), Copyright © 1996 IEEE
Clk
D D
RS
S-R Latch modifications:
(a) all-n-MOS push-pull (Gieseke et al. 1991); (b) complementary push-pull (Oklobdzija and Stojanovic 2001); (c) complementary push-pull with gated keeper (Nikolic et al. 1999).
QQQQ
QQ(a) (b) (c)
S R
S
RS
R
RS
SR
S
R
SR
S
R
S R
S R
S R
RS
S R
RS
Modified sense-amplifier-based flip-flop(Nikolic et al. 1999), Copyright © 1999 IEEE
SR
SR
Q Q
D D
Clk
CSE delay comparison (0.18 m, high load)
Min D-Q DelayComparison
0.00.5
1.01.52.02.5
3.03.54.04.55.0
MSL C2MOSHLF
FSDF
FSAFF M-SAFF
Del
ay[F
O4]
CSE energy breakdown (0.18 m, high load)
Energy breakdown (50% activity)
0
20
40
60
80
100
120
MSL C2MOSHLF
FSDF
FSAFF M-SAFF
En
erg
y [f
J]
Ext. clockExt. dataInt. clockInternal non-clk
Flip-flop Comparisons: (a) delay, (b) internal race immunity (0.25 m, light load)
(a) (b)
CSE energy-per-transition (0.25 m, light load)(Markovic et al. 2001), Copyright © 2001 IEEE
Gated MSL(Markovic et al. 2001), Copyright © 2001 IEEE
0.5
0.5comp
0.5 *
0.5
0.5
0.5 *
D
Clk
Clk
Clk 1
D
D
Q
QS
SS
Clk
Clk1
QS QSS
Clk1
Clk
SM QM
comp
Gated vs. conventional TG MSL:(a) timing, (b) energy
(a) (b)
Data-transition look-ahead latch(Nogawa and Ohtomo 1998), Copyright © 1998 IEEE
D Q
CP
CPCP
QM
Clk
CP
P1
CPI
CP
Data-TransitionLook-Ahead
Clock ControlPulse Generator
CP
CP
CP
DTLA-L without gating
CP
CPCP
CP
D
ClkCPCP
CP
CP
QQM
Pulse generator
C in(CC)
Clk
CPIPulse Generator
Energy comparison of DTLA-L and CMSL
(a)
(b)
Clock-on-demand PL(Hamada et al. 1999), Copyright © 1999 IEEE
XNOR
Pulse Generator
Data-TransitionLook-Ahead
D
Clk
CPCP
CP
CPCP
Q
Straightforward implementation with CMOS gates (energy inefficient)
"1"
"0"
"1" "1"
C int
Clk
XNOR
Energy-efficient implementation with compound AND-NOR gate
XNOR
inv XNOR
inv
CompoundAND-NOR
"1 "
"0"
Clk
Clk
Clk
Clk
CP
Impact of circuit sizing on the energy efficiency of COD-PL(Markovic et al. 2001), Copyright © 2001 IEEE
Conditional capture flip-flop(Kong et al. 2000), Copyright © 2000 IEEE
D
Clk
D
SS R R
Clk**
N N
R
S
S
R
Clk1
Timing parameters in latches and flip-flops with local clock gating(Markovic et al. 2001), Copyright © 2001 IEEE
(a) (b)
Energy and EDP in latches and flip-flops with local clock gating(Markovic et al. 2001), Copyright © 2001 IEEE
(a) (b)
N-only clocked latches: (a) conventional TG MSL, (b) pulsed-latch, (c) conventional PL, (d) push-pull PL
D
QClkQM
SM
Clk
SS
Clk
D
QCP
SS
D
QCP
SS
N1
N2
d1
D
CP
Clk CP
Pulse Generator (b)-(d)
(a)
(c) (d)
(b)
Clk
Clk
CP
Q
N-MSL
N-PL N-PPL
N-FF
CSE energy and delay: (a) high-Vdd and (b) low-swing Clk
0
0.2
0.4
0.6
0.8
0 1 2 3 4 5 6Data-to-Q delay (FO3 inverter delay)
En
ergy
/ cy
cle
(nor
m)
N-MSL
N-PPL
N-FF
N-PL
Low-Swing Clk
0.0
0.2
0.4
0.6
0.8
1.0
1.2
En
ergy
/ cy
cle
(nor
m)
PL
N-PPLMSL
N-FF
0
High-Vdd
Effect of clock noise on low-swing clock latch delay
0%
4%
8%
12%
16%
20%
0% 3% 6% 9% 12%Noise on low-swing clock
Clk
-Q d
ela
y d
eg
rad
ati
on
N-CLN-PPL
N-FF
DET Latch-mux circuit(Llopis and Sachdev 1996), Copyright © 1996 IEEE
QD
Clk Clk
Clk Clk
Clk ClkClk
Clk Clk
Clk
C2MOS Latch-mux(Gago et al. 1993), Copyright © 1993 IEEE
Clk
ClkN2
N3
Clk
ClkN4
N5
N4
N5
N2
N3
D Q
Pulsed-latch: (a) single - edge, (b) dual - edge triggered
Clk
Clk
Clk Clk 1
Clk
D
D
Clk
(a) (b)
Q
Clk Clk
Q
Clk Clk1 Clk1
Clk 2
ClkClk2
Clk
Clk1
Clk2
Clk2
Clk2
Clk2
Clk1 Clk1
Clk 1
Clk1
Clk
Clk
Clk
DET symmetric pulse generator flip-flop
Clk
D
Clk
D
SX
Clk
1st STAGE: X 1st STAGE: Y2nd STAGE
Q
Clk Clk1 Clk1 Clk2
Clk 1
Clk
Clk
Clk2
SY
Delay comparison, SET vs. DET
0
1
2
3
4
5
6
MSL/LM C2MOS-LM PL SPGFF
Del
ay [
FO
4]
SEDE
Power consumption comparison, SET vs. DET (0.18 m, high load)
0
20
40
60
80
100
120
140
160
180
MSL LM PL SE PL DE C2MOS SE C2MOS DE SPGFF
Po
wer
[u
W]
Clk
Non-clk
EDP comparison, single vs. dual-edge triggered clocks (0.18 m, high load)
0
10
20
30
40
50
60
M SL/LM C2M OS PL SPGFF
ED
P [
fJ/5
00
MH
z],
[fJ
/25
0M
Hz]
Single Edge
Double Edge
