STUDY AND DEVELOPMENT OF 3-LEVEL DIODE CLAMPED MLI

USING SPACE VECTOR PULSE WIDTH MODULATION (SVPWM)

A Project Report

Submitted by

SATYA VENKATA KISHORE P

(Roll No.M090186EE)

In partial fulfillment for the award of the Degree of

MASTER OF TECHNOLOGY

IN

ELECTRICAL ENGINEERING

(Power Electronics)

Under the guidance of

Dr. Mukti Barai

Department of Electrical Engineering

NATIONAL INSTITUTE OF TECHNOLOGY CALICUT

NIT Campus P.O., Calicut - 673601, India

May 2011

CERTIFICATE

This is to certify that the project report entitled “STUDY AND DEVELOPMENT

OF 3-LEVEL DIODE CLAMPED MULTILEVEL INVERETER USING

SVPWM” is a bonafide record of the project presented by SATYA VENKATA KISHORE P

(Roll No.M090186EE) during the final year in partial fulfillment of the requirements for the

award of Degree of Master of Technology in Electrical Engineering from National Institute of

Technology Calicut for the year 2011

Dr. Mukti Barai Dr.R. Sreeram Kumar

(Project guide) Professor & Head

Assistant Professor Dept. of Electrical Engineering

Dept. of Electrical Engineering

Place:

Date:

AACCKKNNOOWWLLEEDDGGEEMMEENNTTSS

“The satisfaction that accompanies the successful completion of any task would be in complete

without introducing the people who made it possible and whose constant guidance and

encouragement crowns all the efforts with success”

I am thankful to my Project guide Dr. Mukti Barai who guided me during the course and

helped me to give my best. Her constant encouragement and suggestions were of immense help

to me throughout my project work.

I express my sincere gratitude to the Head of the Department Dr. R. Sreeram Kumar for

permitting me to do this.

I would like to express my thanks to Dr. Saly George, professor and course coordinator

of power electronics, Department of Electrical Engineering, N.I.T. Calicut, for her valuable

advices and help in completion of this work.

I would like to thank all the faculty and staff members of electrical department, who

extended full cooperation for completion of this work.

I take the opportunity to thank all my friends who helped me through their patient

discussions, suggestions and for their timely help at various stages in completion of this work.

SATYA VENKATA KISHORE P

M090186EE

DECLARATION

"I hereby declare that this submission is my own work and that, to the best of

my knowledge and belief. It presents study and development of three level diode

clamped multilevel inverter using Space vector pulse width modulation technique.”

Place: Name:

Date: Reg.No:

CONTENTS

ABSTRACT i

LIST OF FIGURES ii

LIST OF TABLES iv

LIST OF SYMBOLS iv

Chapter 1 INTRODUCTION 1

1.1 IGBT Switching Characteristics 1

1.2 Design of Regulated Power supply circuits 2

1.3 Summary 2

Chapter 2 TWO LEVEL VOLTAGE SOURCE INVERTER AND SVPWM 3

2.1 Introduction 3

2.2 Space vector modulation 3

2.2.1 Switching States 3

2.2.2 Space Vectors 4

2.2.3 Dwell time calculation 7

2.2.4 Modulation index 8

2.2.5 Switching Sequence 10

2.3 Summary 11

Chapter 3 MULTILEVEL INVERTERS 12

3.1 Introduction 12

3.2 Diode Clamped Multilevel Inverters 12

3.3 Three-level inverter 13

3.4 Switching State 13

3.5 Space vector modulation 14

3.5.1 Stationary Space Vectors 14

3.5.2 Dwell Time Calculation 15

3.5.3 Relationship between Vref Location and Dwell Times 19

3.5.4 Switching Sequence Design 20

3.6 Summary 26

Chapter 4 SOFTWARE AND HARDWARE IMPLEMENTATION

AND RESULTS 27

4.1 Two level inverter 27

4.1.1 Software implementation 27

4.1.2 Hardware implementation 28

4.2 Three level diode clamped multilevel inverter 30

4.2.1 Hardware implementation 30

Chapter 5 CONCLUSION AND FUTURE SCOPE 35

REFERENCES 36

APPENDIX 37

i

ABSTRACT

The three level diode clamped multilevel inverter is widely used in high power,

medium voltage applications. This project refers to study and development of three level

diode clamped multilevel inverter using Space Vector Pulse Width Modulation (SVPWM)

technique. Diode clamped multilevel inverter is also called Neutral Point Clamped (NPC)

Inverter. This NPC inverter is most suitable for induction motor drives.

Initially Space vector modulation technique is applied to the two levels inverter and

then it is applied to the three level diode clamped multilevel inverter. Simulation and

hardware prototype implementation of two level inverter and the three level NPC inverter

using SVPWM technique are completed. PIC18F452 microcontroller is used to generate

switching pulses for power IGBT’s.

ii

LIST OF FIGURES

FIG NO FIGURE NAME PAGE NO

Fig 1.1 IGBT turn on and turn off characteristics 1

Fig 1.2 Supply to the Optocoupler 2

Fig 1.3 Supply to the PIC 18F452 2

Fig 1.4 Supply input to the three level inverter 2

Fig 2.1 Simplified two level inverter for high power applications. 3

Fig 2.2 Space vector diagram for two level inverter 5

Fig 2.3 Vref synthesized by V1,V2 and V0 7

Fig 2.4 Seven segment switching sequence for Vref in sector I 11

Fig 3.1 Three level diode clamped multilevel inverter 13

Fig 3.2 Space vector diagram of the NPC inverter 17

Fig 3.3 Division of sectors and regions 17

Fig 3.4 Voltage vectors and their dwell times 18

Fig 3.5 Relationship between the the location of Vref and dwell times 20

Fig 3.6 Effect of switching states on neutral point voltage deviation 21

Fig 3.7 Seven segment switching sequence for Vref in sector I-4 23

Fig 3.8 Division of six regions of sector I for the minimisation of neutral point

voltage deviation 24

Fig 3.9 Graphical representation of extra switchings when Vref moves from

region a to b 25

Fig 4.1 Phase and line voltages of 2-level inverter using SVPWM 27

Fig 4.2 Driver circuit 28

iii

Fig 4.3 Hardware setup for two level inverter 28

Fig 4.4 Line voltage Vab 29

Fig 4.5 Phase voltage Vao 29

Fig 4.6 Line voltage (Vab) when inductive load and 24v are applied 29

Fig 4.7 Supply to the inverter from rectifier 31

Fig 4.8 Voltage across the DC bus capacitors 31

Fig 4.9 Pulses to the four IGBT’s in the first leg from PIC18F452 31

Fig 4.10 Voltage Vab 32

Fig 4.11 Voltage Vaz 32

Fig 4.12 Voltage Vao 32

Fig 4.13 Voltage across the clamping diodes 33

Fig 4.14 Voltage across the switch 33

Fig 4.15 Current flowing through the load 33

Fig 4.16 Volatage Vab with harmonic spectrum 34

Fig 4.17 Hardware setup of three level diode clamped multilevel inverter 34

iv

LIST OF TABLES

TABLE NO TABLE NAME PAGE NO

Table 2.1 Definition of switching states 7

Table 2.2 Space vectors, switching states and on state switches 7

Table 2.3 Vref location and dwell times 11

Table 2.4 Seven segment switching sequence 14

Table 3.1 Definition of switching states 17

Table 3.2 Voltage vectors and switching states 19

Table 3.3 Dwell time calculation for Vref in sector I 22

Table 3.4 Seven segment switching sequence for Vref in sector I-2a 26

Table 3.5 Seven segment switching sequence 27

LIST OF SYMBOLS

Vd DC link input voltage to the inverter

ma Modulation index

Ts Sampling period

fsp Switching frequency

fsw,dev Switching frequency of device

Ta,Tb,Tc Dwell times for the nearest three vectors

1

CHAPTER 1

INTRODUCTION

1.1 IGBT Switching Characteristics:

Switching characteristics of an IGBT during turn on and turn off are sketched in

fig1.1.The turn on time is defined as the time between the instants of forward blocking to

forward on state.Turn on time is composed of delay time tdn and rise time tr,that is

ton=td+tr.The delay time is defined as the time for the collector emitter voltage to fall from

Vce to 0.9 Vce.Here Vce is the initial collector emitter voltage.Time tdn may also be defined

as the time for the collector current rise from its initial leakage current Ice to 0.1Ic. Here Ic is

the final value of collector current.The rise time tr is the time during which collector emitter

voltage falls from 0.9 Vce to 0.1 Vce.It is also defined as the time for the collector current to

rise from 0.1 Ic to its final value Ic.After time ton,the collector current is Ic and the collector

emitter voltage falls to small value called conduction drop Vces where subscript s denotes

saturated value.

The turn off time also consists of two intervals:delay time,td(off) and fall time tf that

is toff=td(off)+tf.The delay time is the time during which the collector currnt falls from

Ic(where Vge falls from 90% of its maximum value) to 0.9Ic.The fall time is defined as the

time during which collector current falls from 90 to 10% of its initial value Ic.

Fig 1.1: IGBT turn on and turn off characteristics

2

1.2 Design of Regulated Power supply circuits:

Fig 1.2:Supply to the Optocoupler

Fig 1.3: Supply to the PIC 18F452

Fig 1.4: Supply input to the three level inverter

1.3 Summary:

In this chapter switching characteristics of IGBT,introduction to PIC microcontroller and

power supply circuits are discussed.

3

CHAPTER 2

TWO LEVEL VOLTAGE SOURCE INVERTER AND SVPWM

2.1 Introduction:

The primary function of a voltage source inverter (VSI) is to convert a fixed dc

voltage to a three-phase ac voltage with variable magnitude and frequency. A simplified

circuit diagram for a two-level voltage source inverter for high-power medium voltage

applications is shown in Fig2.1. The inverter is composed of six group of active switches, S1

~ S6, with a free-wheeling diode in parallel with each switch. Depending on the dc operating

voltage of the inverter, each switch group consists of two or more IGBT switching devices

connected in series.

Fig 2.1: Simplified two level inverter for high power applications.

2.2 Space vector modulation:

Space vector modulation (SVM) is one of the preferred real-time modulation

techniques and is widely used for digital control of voltage source inverters. This section

presents the principle and implementation of the space vector modulation for the two-level

inverter.

2.2.1 Switching States:

The operating status of the switches in the two-level inverter in Fig2.1 can be

represented by switching states. As indicated in Table 2.1, switching state ‘P’ denotes that the

upper switch in an inverter leg is on and the inverter terminal voltage (Van, Vbn, or Vcn) is

positive (+Vd) while ‘O’ indicates that the inverter terminal voltage is zero due to the

conduction of the lower switch.

There are eight possible combinations of switching states in the two-level inverter as

listed in Table2.2. The switching state [POO], for example, corresponds to the conduction of

4

S1, S6, and S2 in the inverter legs A, B, and C, respectively. Among the eight switching

states, [PPP] and [OOO] are zero states and the others are active states.

2.2.2 Space Vectors:

The active and zero switching states can be represented by active and zero space

vectors, respectively. A typical space vector diagram for the two-level inverter is shown in

Fig2.2, where the six active vectors V1 to V6 form a regular hexagon with six equal sectors (I

to VI). The zero vector V0 lies on the centre of the hexagon.

Table 2.1: Definition of switching states

Table 2.2: Space vectors, switching states and on state switches

5

Fig 2.2: Space vector diagram for two level inverter

To derive the relationship between the space vectors and switching states, refer to the

two-level inverter in Fig2.1. Assuming that the operation of the inverter is three-phase

balanced, we have

Vao(t) + Vbo(t) + Vco(t) = 0 (2.1)

where Vao, Vbo, and Vco are the instantaneous load phase voltages. From mathematical point

of view, one of the phase voltages is redundant since given any two phase voltages, the third

one can be readily calculated. Therefore, it is possible to transform the three-phase variables

to equivalent two-phase variables.

�VαVβ� = � 1 �� ��0 √� √�� �VaoVboVco� (2.2)

The coefficient 2/3 is somewhat arbitrarily chosen. The commonly used value is 2/3 or

√(2/3). The main advantage of using 2/3 is that the magnitude of the two-phase voltages will

be equal to that of the three-phase voltages after the transformation. A space vector can be

generally expressed in terms of the two-phase voltages in the α-β plane.

6

V(t) = Vα(t) + jVβ(t) (2.3)

Substituting (2.2) into (2.3), we have

V(t) = [Vao(T)ej0 + Vbo(t)ej2π/3 + Vco(t)e j4π/3] (2.4)

where ejx = cosx + jsinx and x = 0, 2π/3 or 4π/3. For active switching state [POO], the

generated load phase voltages are

Vao(t) =� Vd, Vbo(t) = – � Vd, and Vco(t) = –

�Vd (2.5)

The corresponding space vector, denoted as V1, can be obtained by substituting (2.5) into

(2.4)

V1=�Vd*ej0 (2.6)

Following the same procedure, all six active vectors can be derived

Vk=�Vd*ej(k-1)

� (2.7)

The zero vector V0 has two switching states [PPP] and [OOO], one of which seems

redundant. As will be seen later, the redundant switching state can be utilized to minimize the

switching frequency of the inverter or perform other useful functions. The relationship

between the space vectors and their corresponding switching states is given in Table 2.2.

Note that the zero and active vectors do not move in space, thus they are referred to as

stationary vectors. On the contrary, the reference vector Vref in Fig2.2 rotates in space at an

angular velocity.

w= 2*pi*f1

Where f1 is the fundamental frequency of the inverter output voltage.

For a given magnitude (length) and position, Vref can be synthesized by three nearby

stationary vectors, based on which the switching states of the inverter can be selected and gate

signals for the active switches can be generated. When Vref passes through sectors one by

one, different sets of switches will be turned on or off. As a result, when Vref rotates one

7

revolution in space, the inverter output voltage varies one cycle over time. The inverter output

frequency corresponds to the rotating speed of Vref, while its output voltage can be adjusted

by the magnitude of Vref.

2.2.3 Dwell time calculation:

As mentioned earlier, the reference Vref can be synthesized by three stationary vectors.

The dwell time for the stationary vectors essentially represents the duty-cycle time (on-state

or off-state time) of the chosen switches during a sampling period Ts of the modulation

scheme. The dwell time calculation is based on ‘volt-second balancing’ principle, that is, the

product of the reference voltage Vref and sampling period Ts equals the sum of the voltage

multiplied by the time interval of chosen space vectors.

Fig 2.3: Vref synthesized by V1,V2 and V0

Assuming that the sampling period Ts is sufficiently small, the reference vector Vref can

be considered constant during Ts. Under this assumption, Vref can be approximated by two

adjacent active vectors and one zero vector. For example, when Vref falls into sector I as

shown in Fig2.3, it can be synthesized by V1, V2, and V0. The volt-second balancing

equation is

Vref Ts=V1 Ta + V2 Tb + V0 T0

Ts=Ta + Tb + T0 (2.8)

8

Where Ta,Tb and T0 are the dwell times for the vectors V1,V2 and V0 respectively. The

space vectors in (2.8) can be expressed as

V1 = �Vd, V2 =

�Vde��/, V0=0 and Vref = Vref e�� (2.9)

Substituting (2.9) into (2.8) and then splitting the resultant equation into the real (α-axis) and

imaginary (β-axis) components in the α-β plane, we have

Re: Vref (cosθ) Ts = �VdTa +

�VdTb

Im: Vref (sinθ) Ts =�√ VdTb (2.10)

Solving (2.10) together with Ts = Ta + Tb + T0 yields

Ta=√��� !"�# sin (

� − θ)

Tb=√��� !"�# sinθ for 0 ≤ θ ≤

� (2.11)

T0=Ts-Ta-Tb

To visualize the relationship between the location of Vref and the dwell times, let us

examine some special cases. If Vref lies exactly in the middle between V1 and V2 (i.e.,θ =

π/6), the dwell time Ta for V1 will be equal to Tb for V2. When Vref is closer to V2 than V1,

Tb will be greater than Ta. If Vref is coincident with V2, Ta will be zero. With the head of

Vref located right on the central point Q in figure2.3, Ta = Tb = T0. The relationship between

the Vref location and dwell times is summarized in Table2.3.

Table 2.3: Vref location and dwell times

2.2.4 Modulation index:

Equation2.11 can be also expressed in terms of modulation index ma

9

Ta=Ts*ma* sin (� − θ)

Tb=Ts*ma* sinθ for 0 ≤ θ ≤ � (2.12)

T0=Ts-Ta-Tb

Where ma=√� !"�# (2.13)

The maximum magnitude of the reference vector, Vref,max, corresponds to the radius of

the largest circle that can be inscribed within the hexagon shown in Fig2.2. Since the hexagon

is formed by six active vectors having a length of 2Vd/3, Vref,max can be found from

Vref,max=�Vd *

√� = &'√ (2.14)

Substituting (2.14) into (2.13) gives the maximum modulation index:

ma,max = 1

from which the modulation index for the SVM scheme is in the range of 0≤ma≤1

The maximum fundamental line-to-line voltage (rms) produced by the SVM scheme can be

calculated by

Vmax,SVM = √3(Vref,max/√2) = 0.707Vd (2.15)

where Vref,max/√2 is the maximum rms value of the fundamental phase voltage of the

inverter.

With the inverter controlled by the SPWM scheme, the maximum fundamental line-to-line

voltage is

Vmax,SPWM = 0.612Vd (2.16)

from which

�*+,,.�/�*+,,.01/ = 1.155 (2.17)

10

Equation (2.17) indicates that for a given dc bus voltage the maximum inverter line-to-

line voltage generated by the SVM scheme is 15.5% higher than that by the SPWM scheme.

However, the use of third harmonic injection SPWM scheme can also boost the inverter

output voltage by 15.5%. Therefore, the two schemes have essentially the same dc bus voltage

utilization.

2.2.5 Switching Sequence:

With the space vectors selected and their dwell times calculated, the next step is to

arrange switching sequence. In general, the switching sequence design for a given Vref is not

unique, but it should satisfy the following two requirements for the minimization of the device

switching frequency:

(a) The transition from one switching state to the next involves only two switches in the same

inverter leg, one being switched on and the other switched off.

(b) The transition for Vref moving from one sector in the space vector diagram to the next

requires no or minimum number of switchings. Figure2.4 shows a typical seven-segment

switching sequence and inverter output voltage waveforms for Vref in sector I, where Vref is

synthesized by V1, V2 and V0. The sampling period Ts is divided into seven segments for the

selected vectors.The following can be observed:

• The dwell times for the seven segments add up to the sampling period (Ts = Ta + Tb +

T0).

• Design requirement (a) is satisfied. For instance, the transition from [OOO] to [POO] is

accomplished by turning S1 on and S4 off, which involves only two switches.

• The redundant switching sates for V0 are utilized to reduce the number of switchings per

sampling period. For the T0/4 segment in the center of the sampling period, the switching

state [PPP] is selected, whereas for the T0/4 segments on both sides, the state [OOO] is

used.

• Each of the switches in the inverter turns on and off once per sampling period. The

switching frequency fsw of the devices is thus equal to the sampling frequency fsp, that is,

fsw = fsp = 1/Ts.

11

Fig 2.4: Seven segment switching sequence for Vref in sector I

Table2.4 gives the seven-segment switching sequences for Vref residing in all six sectors.

Note that all the switching sequences start and end with switching state [OOO], which

indicates that the transition for Vref moving from one sector to the next does not require any

switchings. The switching sequence design requirement (b) is satisfied.

Table 2.4: Seven segment switching sequence

2.3 Summary:

In this chapter two level inverter and space vector modulation technique to the two level

inverter are discussed.

12

CHAPTER 3

MULTILEVEL INVERTERS

3.1 Introduction:

In recent years, industry has begun to demand higher power equipment, which now

reaches the megawatt level. Controlled ac drives in the megawatt range are usually connected

to the medium-voltage network. Today, it is hard to connect a single power semiconductor

switch directly to medium voltage grids (2.3, 3.3, 4.16, or 6.9 kV). For these reasons, a new

family of multilevel inverters has emerged as the solution for working with higher voltage

levels. Multilevel inverters include an array of power semiconductors and capacitor voltage

sources, the output of which generate voltages with stepped waveforms. The commutation of

the switches permits the addition of the capacitor voltages, which reach high voltage at the

output, while the power semiconductors must withstand only reduced voltages.

The most attractive features of multilevel inverters are as follows.

1) They can generate output voltages with extremely low distortion and lower.

2) They draw input current with very low distortion.

3) They generate smaller common-mode (CM) voltage, thus reducing the stress in the motor

bearings. In addition, using sophisticated modulation methods, CM voltages can be

eliminated.

4) They can operate with a lower switching frequency.

There are three types of multilevel inverters

1. Diode clamped multilevel inverter.

2. Capacitor clamped multilevel inverter.

3. Cascaded multilevel inverter.

3.2 Diode Clamped Multilevel Inverters:

The diode-clamped multilevel inverter employs clamping diodes and cascaded dc

capacitors to produce ac voltage waveforms with multiple levels. The inverter can be

generally configured as a three, four, or five-level topology, but only the three-level inverter,

often known as neutral-point clamped (NPC) inverter, has found wide application in high-

power medium-voltage (MV) drives. The main features of the NPC inverter include reduced

13

dv/dt and THD in its ac output voltages in comparison to the two-level inverter discussed

earlier. More importantly, the inverter can be used in the MV drive to reach a certain voltage

level without switching devices in series. For instance, the NPC inverter using 6000V devices

is suitable for the drives rated at 4160V.

In this chapter, various aspects of the three-level NPC inverter are discussed, including

the inverter topology and operating principle. A conventional space vector modulation (SVM)

scheme for the NPC inverter is discussed in detail. The dc input voltage of the inverter is

normally split by two cascaded dc capacitors, providing a floating neutral point.

3.3 Three-level inverter:

Figure3.1 shows the simplified circuit diagram of a three-level NPC inverter. The

inverter leg A is composed of four active switches S1 to S4. In practice, either IGBT or GCT

can be employed as a switching device. On the dc side of the inverter, the dc bus capacitor is

split into two, providing a neutral point Z. The diodes connected to the neutral point, DZ1 and

DZ2, are the clamping diodes. When switches S2 and S3 are turned on, the inverter output

terminal A is connected to the neutral point through one of the clamping diodes. The voltage

across each of the dc capacitors is E, which is normally equal to half of the total dc voltage

Vd. With a finite value for Cd1 and Cd2, the capacitors can be charged or discharged by

neutral current iz, causing neutral-point voltage deviation.

Fig 3.1: Three level diode clamped multilevel inverter

3.4 Switching State:

The operating status of the switches in the NPC inverter can be represented by

switching states shown in Table3.2. Switching state ‘P’ denotes that the upper two switches in

14

leg A are on and the inverter terminal voltage Vaz, which is the voltage at terminal A with

respect to the neutral point Z, is +E, whereas ‘N’ indicates that the lower two switches

conduct, leading to Vaz = –E. Switching state ‘O’ signifies that the inner two switches S2 and

S3 are on and Vaz is clamped to zero through the clamping diodes. Depending on the

direction of load current ia, one of the two clamping diodes is turned on. For instance, a

positive load current (ia > 0) forces DZ1 to turn on, and the terminal A is connected to the

neutral point Z through the conduction of DZ1 and S2.

It can be observed from Table3.1 that switches S1 and S3 operate in a complementary

manner. With one switched on, the other must be off. Similarly, S2 and S4 are a

complementary pair as well.

Table 3.1: Definition of switching states

3.5 Space vector modulation:

Various space vector modulation (SVM) schemes have been proposed for the three

level NPC inverter. This section presents a “conventional” SVM scheme for the NPC inverter.

3.5.1 Stationary Space Vectors:

As indicated earlier, the operation of each inverter phase leg can be represented by

three switching states [P], [O], and [N]. Taking all three phases into account, the inverter has

a total of 27 possible combinations of switching states. As listed in Table3.2, these three-

phase switching states are represented by three letters in square brackets for the inverter

phases A, B, and C. To find the relationship between the switching states and their

corresponding space voltage vectors, we can follow the same procedures presented in Chapter

2. The 27 switching states listed in the table correspond to 19 voltage vectors whose space

vector diagram is given in Fig3.3. Based on their magnitude (length), the voltage vectors can

be divided into four groups:

15

Zero vector (V0), representing three switching states [PPP], [OOO], and [NNN]. The

magnitude of V 0 is zero.

Small vectors (V1 to V6), all having a magnitude of Vd/3. Each small vector has two

switching states, one containing [P] and the other containing [N], and therefore can be further

classified into a P- or N-type small vector.

Medium vectors (V7 to V12), whose magnitude is √3Vd/3.

Large vectors (V13 to V18), all having a magnitude of 2Vd/3.

3.5.2 Dwell Time Calculation:

To facilitate the dwell time calculation, the space vector diagram of Fig3.2 can be

divided into six triangular sectors (I to VI), each of which can be further divided into four

triangular regions (1 to 4) as illustrated in Fig3.3. The switching states of all the vectors are

also shown in the figure. Similar to the SVM algorithm for the two-level inverter, the space

vector modulation for the NPC inverter is also based on “volt-second balancing” principle;

that is, the product of the reference voltage Vref and sampling period Ts equals the sum of the

voltage multiplied by the time interval of chosen space vectors. In the NPC inverter, the

reference vector Vref can be synthesized by three nearest stationary vectors. For instance,

when Vref falls into region 2 of sector I as shown in Fig3.4, the three nearest vectors are V1,

V2, and V7, from which

V1 Ta + V7 Tb + V2 Tc = Vref Ts

Ta + Tb + Tc = Ts (3.1)

where Ta, Tb, and Tc are the dwell times for V1, V7, and V2, respectively. Note that Vref can

also be synthesized by other space vectors instead of the “nearest three.” However, it will

cause higher harmonic distortion in the inverter output voltage, which is undesirable in most

cases.

16

Table 3.2: Voltage vectors and switching states

17

Fig 3.2: Space vector diagram of the NPC inverter

Fig 3.3: Division of sectors and regions.

18

Fig 3.4: voltage vectors and their dwell times.

The voltage vectors V1,V2,V7, and Vref in Fig3.5 can be expressed as

V1 = �Vd, V2 =

�Vde��/, V7 = √ Vde��/4, and Vref = Vref e�� (3.2)

Substituting (3.2) into (3.1) yields

� VdTa +√ Vde��/4Tb +

�Vde��/Tc = Vref e��Ts (3.3)

from which

�VdTa + √ Vd_(cos

�4 + j sin�4)Tb + Vd(cos

� + j sin �)Tc = Vref (cosθ + j sinθ)Ts (3.4)

Splitting (3.4) into the real and imaginary parts, we have

Re: Ta + 3/2 Tb + 1/2 Tc = 3 � !"�# (cosθ)Ts (3.5)

Im: 3/2Tb + √3/2Tc = 3&567&' (sinθ)Ts

Solve (3.5) together with Ts = Ta + Tb + Tc for dwell times

Ta=Ts[1-2ma*sinθ]

Tb=Ts[2ma*sin(�+θ)-1] for 0≤θ≤ � (3.6)

Tc=Ts[1-2ma*sin(�-θ)]

where ma is the modulation index, defined by

The maximum length of the reference vector

circle that can be inscribed within the hexagon of Fig3.3, which

the medium voltage vectors

Substituting Vref,max into (8.3

ma,max =

from which the range of ma

Table3.3 gives the equations for the calculation of dwell times for

Table 3.3: Dwell time calculation for Vref

The equations in Table3.3 can also be used to calculate the dwell times when

sectors (II to VI) provided that a multiple of

displacement θ such that the modified angle falls into the r

in the equations.

3.5.3 Relationship between Vref location and dwell Times:

To demonstrate the relationship between the

an example shown in Fig3.5. Assuming that the head of

4, the dwell times for the nearest three vectors

distance from Q to these vectors is the same.

and θ= 49.1° into the equations in Table 3.3, from which the calculated dwell times are

Tb = Tc = 0.333Ts.

19

ma= √3VrefVd

The maximum length of the reference vector Vref corresponds to the radius of the largest

circle that can be inscribed within the hexagon of Fig3.3, which happens to be the length of

the medium voltage vectors

Vref,max = √3Vd/3

,max into (8.3-7) yields the maximum modulation index

,max = √3Vref,max/Vd = 1

ma is 0 ≤ma ≤1

Table3.3 gives the equations for the calculation of dwell times for Vref

3.3: Dwell time calculation for Vref in sector I

The equations in Table3.3 can also be used to calculate the dwell times when

sectors (II to VI) provided that a multiple of π/3 is subtracted from the actual angular

such that the modified angle falls into the range between zero and

3.5.3 Relationship between Vref location and dwell Times:

To demonstrate the relationship between the Vref location and dwell times, consider

an example shown in Fig3.5. Assuming that the head of Vref points to the centre

4, the dwell times for the nearest three vectors V2, V7, and V14 should be identical since the

distance from Q to these vectors is the same. This can be verified by substituting

= 49.1° into the equations in Table 3.3, from which the calculated dwell times are

(3.7)

corresponds to the radius of the largest

happens to be the length of

7) yields the maximum modulation index

(3.8)

Vref in sector I.

The equations in Table3.3 can also be used to calculate the dwell times when Vref is in other

/3 is subtracted from the actual angular

ange between zero and π/3 for use

location and dwell times, consider

points to the centre Q of region

14 should be identical since the

This can be verified by substituting ma = 0.882

= 49.1° into the equations in Table 3.3, from which the calculated dwell times are Ta =

20

With Vref moving toward V2 from Q along the dashed line, the influence of V2 on Vref

becomes stronger, which translates into a longer dwell time for V2. When Vref is identical to

V2, the dwell time Tc for V2 reaches its maximum value (Tc = Ts) while Ta and Tb for V14

and V7 diminish to zero.

Fig 3.5: Relationship between the location of Vref and dwell times

3.5.4 Switching Sequence Design:

The neutral point voltage Vz, which is defined as the voltage between the neutral point

Z and the negative dc bus, normally varies with the switching state of the NPC inverter. When

designing the switching sequence, we should minimize the effect of the switching state on

neutral point voltage deviation. Taking into account the two requirements presented in

previous chapter for the two-level inverter, the overall requirements for switching sequence

design in the NPC inverter are as follows:

(a) The transition from one switching state to the next involves only two switches in the same

inverter leg, one being switched on and the other switched off.

(b)The transition for Vref moving from one sector (or region) to the next requires no or

minimum number of switchings.

(c) The effect of switching state on the neutral-point voltage deviation is minimized.

21

(1) Effect of Switching States on Neutral-Point Voltage Deviation:

The effect of switching states on neutral voltage deviation is illustrated in Fig3.6. When

the inverter operates with switching state [PPP] of zero vector V0, the upper two switches in

each of the three inverter legs are turned on, connecting the inverter terminals A, B, and C to

the positive dc bus as shown in Fig3.6a. Since the neutral point Z is left unconnected, this

switching state does not affect Vz. Similarly, the other two zero switching states, [OOO] and

[NNN], do not cause Vz to shift either.

Figure3.6b shows the inverter operation with P-type switching state [POO] of small

vector V1. Since the three-phase load is connected between the positive dc bus and neutral

point Z, the neutral current iz flows into Z, causing Vz to increase. On the contrary, the N-

type switching state [ONN] of V1 makes Vz to decrease as shown in Fig3.6c.

Fig 3.6: Effect of switching states on neutral point voltage deviation

22

The medium-voltage vectors also affect the neutral-point voltage. For medium vector V7

with switching state [PON] in Fig3.6d, load terminals A, B, and C are connected to the

positive bus, the neutral point, and the negative bus, respectively. Depending on the inverter

operating conditions, the neutral-point voltage Vz may rise or drop.

Considering a large vector V13 with switching state [PNN] shown in Fig3.6e, the load

terminals are connected between the positive and negative dc buses. The neutral point Z is left

unconnected, and thus the neutral voltage is not affected.

It can be summarized that

• Zero vector V0 does not affect the neutral point voltage Vz.

• Small vectors V1 to V6 have a dominant influence on Vz. A P-type small vector makes

Vz rise, while an N-type small vector causes Vz to decline.

• Medium vectors V7 to V12 also affect Vz, but the direction of voltage deviation is

undefined.

• The large vectors V13 to V18 do not play a role in neutral-point voltage deviation.

Note that the above summary is made under the assumption that the inverter is in normal

(motoring) operating mode.

(2) Switching Sequence with Minimal Neutral-Point Voltage Deviation:

As mentioned earlier, a P-type small vector causes the neutral-point voltage Vz to rise

while an N-type small vector makes Vz fall. To minimize the neutral- point voltage deviation,

the dwell time of a given small vector can be equally distributed between the P- and N-type

switching states over a sampling period. According to the triangular region that the reference

vector Vref lies in, the following two cases are investigated.

Case 1: One Small Vector among Three Selected Vectors:

When the reference vector Vref is in region 3 or 4 of sector I shown in Fig3.4, only

one of the three selected vectors is the small vector. Assuming that Vref falls into region 4, it

can be synthesized by V2, V7, and V14. The small vector V2 has two switching states [PPO]

and [OON]. To minimize the neutral voltage deviation, the dwell time for V2 should be

equally distributed between the P- and N-type states. Figure3.7 shows a typical seven-

segment switching sequence for the NPC inverter, from which we can observe that

• The dwell times for the seven segments add up to the sampling period of the PWM pattern

(Ts = Ta + Tb + Tc).

23

• Design requirement (a) is satisfied. For instance, the transition from [OON] to [PON] is

accomplished by turning S1 on and switching S3 off, which involves only two switches.

• The dwell time Tc for V2 is equally divided between the P- and N-type switching states,

which satisfies design requirement (c).

• Among the four switching devices in an inverter leg, only two are tuned on and off once

per sampling period. Assuming that the transition for Vref moving from one sector (or

region) to the next does not involve any switchings, the device switching frequency

fsw,dev is equal to half of the sampling frequency fsp, that is,

fsw,dev = fsp/2 = 1/(2Ts)

Fig 3.7: Seven segment switching sequence for Vref in sector I-4

Case 2: Two Small Vectors among Three Selected Vectors:

When Vref is in region 1 or 2 of sector I in Fig3.5, two of the three selected vectors

are small vectors. To reduce the neutral voltage deviation, each of the two regions is further

divided into two sub regions as shown in Fig3.8. Assuming that Vref lies in region2a, it can

be approximated by V1, V2, and V7. Since Vref is closer to V1 than V2, the corresponding

dwell time Ta for V1 is longer than Tc for V2. The vector V1 is referred to as dominant small

vector, whose dwell time is equally divided between V1P and V1N as shown in Table 3.4.

Based on the above discussions, all the switching sequences in sectors I and II are

summarized in Table3.5. It can be observed that (1) when Vref crosses the border between

24

sectors I and II, the transition does not involve any switchings; and (2) an extra switching

takes place when Vref moves from region a to b within a sector. The graphical representation

is illustrated in Fig3.9, where the large and small circles are the steady-state trajectories of

Vref and the dots represent the locations at which an extra switching takes place. Since each

of these extra switchings involves only two devices (out of twelve) and there are only six

extra switchings per cycle of fundamental frequency, the average switching frequency of the

device is increased to

fsw,dev = fsp/2 + f1/2

Fig 3.8: Division of six regions of sector I for the minimisation of neutral point voltage

deviation.

Table 3.4: Seven segment switching sequence for Vref in sector I-2a

25

Table 3.5: Seven segment switching sequence

Fig 3.9: Graphical representation of extra switchings when Vref moves from

region a to b

26

3.6 Summary:

In this chapter three level diode clamped inverter and space vector modulation technique

to the three level diode clamped inverter are discussed.

27

CHAPTER 4

SOFTWARE AND HARDWARE IMPLEMENTATION AND RESULTS

4.1 Two level inverter:

4.1.1 Software implementation:

The circuit diagram for the two level inverter is shown in fig2.1. Simulation of this 2-level

inverter is done using SVPWM in Simulink and the phase and line voltages are shown in

fig4.1

In the hardware implementation PIC18F452 is used to generate the gating pulses to the

IGBT’s. Optocoupler MCT2E is used as a driver circuit as well as isolation. Combined PIC

and Optocoupler circuit is shown in fig 4.2. 12/24V DC supply is given to the inverter and the

output waveforms are shown in figures below.

Fig 4.1: Phase and line voltages of 2-level inverter using SVPWM

28

4.1.2 Hardware implementation:

Fig 4.2: Driver circuit

Fig 4.3: Hardware setup for two level inverter

29

Fig 4.4: Line voltage Vab

Fig 4.5: Phase voltage Vao

Fig 4.6: Line voltage (Vab) when inductive load and 24v are applied

30

4.2 Three level diode clamped multilevel inverter:

4.2.1 Hardware implementation:

The following specifications are used in writing the program

• Modulation index, ma=0.7

• Sampling period, Ts=0.667ms

• Sampling Frequency, fsp=1.5kHz=1500Hz

• Switching frequency, fsw.dev=775Hz

• Frequency of output voltage=50 Hz

The circuit diagram for the three level diode clamped multilevel inverter is shown in

fig3.1. The hardware set up is shown in figure 4.17 below. In the hardware implementation

PIC18F452 is used to generate the gating pulses to the IGBT’s. Optocoupler MCT2E is used

as a driver circuit as well as isolation. Combined PIC and Optocoupler circuit is shown in fig

4.2. 50V DC supply is given to the inverter and the output waveforms are shown in figures

below. Fig 4.7 shows the DC voltage supply to the three level diode clamped multilevel

inverter from the rectifier circuit shown in the figure 1.5. The given 50V DC is equally

divided between the two DC link capacitors as we use good SVPWM technique. Fig 4.8

shows the 25V across the DC bus capacitors shown in fig 3.1. Fig 4.9 shows the four pulses

with 5v peak from the pic microcontroller and these four pulses are applied to the four

IGBT’s in the first leg of the three level inverter. The pulses to the second and third legs are

similar to these pulses and are phase shifted by 120 and 240 degrees respectively. Fig 4.10

shows the voltage between the points A and B in the fig 3.1 when the resistive load is

connected. Fig 4.11 is the voltage waveform measured between the points A and Z in the

circuit shown in fig3.1. Fig 4.12 shows the voltage waveform between the points A and O in

the fig shown in 3.1. Fig 4.13 shows the voltage waveform across the upper/lower clamping

diode. Fig 4.14 shows the voltage across the switch S1 shown in fig3.1. A current probe is

connected where iA is present in the circuit 3.1 and the wave form is taken and is shown in fig

4.15. It shows the peak to peak voltage above 833.33mv that means 0.833A current is flowing

in that wire as the probe setting is 1000mv/A. Fig4.16 gives the harmonic spectrum of the line

voltage Vab and the value of the fundamental voltage is about 24V.

31

Fig 4.7: Supply to the inverter from rectifier

Fig 4.8: Voltage across the DC bus capacitors

Fig 4.9: Pulses to the four IGBT’s in the first leg from PIC18F452

32

Fig 4.10: Voltage Vab

Fig 4.11: Voltage Vaz

Fig 4.12: Voltage Vao

33

Fig 4.13: Voltage across the clamping diodes

Fig 4.14: Voltage across the switch

Fig 4.15: Current flowing through the load

34

Fig 4.16: Volatage Vab with harmonic spectrum

Fig 4.17: Hardware setup of three level diode clamped multilevel inverter

35

CHAPTER 5

CONCLUSION

The Space vector pulse width modulation technique to the two levels inverter and three

levels diode clamped multilevel inverter have been studied, designed and implemented in

hardware. The functionality and switching operation of three levels diode clamped multilevel

inverter in open loop have been depicted with experimental results for three phase resistive

load. MPLAB IDE 8.30 is used to program the PIC 18F452 microcontroller and this program

is verified using Proteus software.

FUTURE SCOPE

In this project pulses are generated using PIC microcontroller, these pulses can be

generated using DSP module also. Open loop operation is carried out in this project, closed

loop operation of the three level inverter can be implemented with both the controlling

techniques i.e., using PIC microcontroller and DSP module.

36

REFERENCES

1. Rodriguez, J.; Jih-Sheng Lai; Fang Zheng Peng:’Multilevel Inverters: A Survey of

Topologies,Controls, and Applications’ IEEE TRANSACTIONS ON INDUSTRIAL

ELECTRO.NICS, VOL. 49, NO. 4, AUGUST 2002.

2. Text book:”Multilevel voltage source converters” by Bin Wu

3. Baohua Lang, Miao Miao, Weiguo Liu, Guangzhao Luo:” Simulation and experiment

Study of Space Vector Pulse Width Modulation” The Ninth International Conference on

Electronic Measurement & Instruments.

4. Haitham Abu-Rub, Joachim Holtz, Jose Rodriguez, Ge Baoming;’ Medium-Voltage

Multilevel Converters—State of the Art, Challenges, and Requirements in industrial

Applications’ IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57,

NO. 8, AUGUST 2010.

5. Madhav D. Manjrekar, Peter K. Steimer, and Thomas A. Lipo:’ Hybrid Multilevel Power

Conversion System:A Competitive Solution for High-Power Applications’ IEEE

TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 36, NO. 3, MAY/JUNE

2000.

6. Data sheets of 15N120,MCT2E,7805,7812

7. Text book “PIC Microcontroller and Embedded Systems Using Assembly and C for

PIC18” by MUHAMMAD ALI MAZIDI, ROLIN D.MCKINLAY, DANNY CAUSEY.

37

APPENDIX

PIC microcontroller:

Fig: Pin diagram of PIC 18F452

Microcontroller PIC18f452 has the following features.

a. High Performance RISC CPU:

• C compiler optimized architecture/instruction set source code compatible with the PIC16

and PIC17 instruction sets

• Linear program memory addressing to 32 Kbytes

• Linear data memory addressing to 1.5 Kbytes

• Up to 10 MIPs operation:- DC 40 MHz osc./clock input 4 MHz - 10 MHz osc./clock input

with PLL active

• 16-bit wide instructions, 8-bit wide data path

38

• Priority levels for interrupts

• 8 x 8 Single Cycle Hardware Multiplier

b. Peripheral Features:

• High current sink/source 25 mA/25 mA

• Three external interrupt pins

• Timer0 module: 8-bit/16-bit timer/counter with 8-bit programmable prescaler

• Timer1 module: 16-bit timer/counter

• Timer2 module: 8-bit timer/counter with 8-bit period register (time-base for PWM)

• Timer3 module: 16-bit timer/counter

• Secondary oscillator clock option - Timer1/Timer3

• Two Capture/Compare/PWM (CCP) modules. CCP pins that can be configured as capture

input: capture is 16-bit, maximum resolution 6.25 ns (TCY/16) Compare is 16-bit, maximum

resolution 100 ns (TCY) PWM output: PWM resolution is 1 to 10-bit, max. PWM freq. @: 8-

bit resolution = 156 kHz 10-bit resolution = 39 kHz

• Master Synchronous Serial Port (MSSP) module, Two modes of operation: 3-wire SPI™

supports all 4 SPI modes) I2C™ Master and Slave mode Peripheral Features (Continued):

• Addressable USART module Supports RS-485 and RS-232

• Parallel Slave Port (PSP) module

c. Analog Features:

• Compatible 10-bit Analog-to-Digital Converter module (A/D) with fast sampling rate

conversion available during SLEEP Linearity ≤1 LSB

• Programmable Low Voltage Detection (PLVD) Supports interrupt on-Low Voltage

detection

39

• Programmable Brown-out Reset (BOR)

d. Special Microcontroller Features:

• 100,000 erase/write cycle Enhanced FLASH program memory typical

• 1,000,000 erase/write cycle Data EEPROM memory

• FLASH/Data EEPROM Retention: > 40 years

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own On-Chip RC Oscillator for reliable operation

• Programmable code protection

• Power saving SLEEP mode

• Selectable oscillator options including 4X Phase Lock Loop (of primary oscillator) –

Secondary Oscillator (32 kHz)

• Single supply 5V In-Circuit Serial Programming™ (ICSP™) via two pins

• In-Circuit Debug (ICD) via two pins

e. CMOS Technology:

• Low power, high speed FLASH/EEPROM technology

• Fully static design

• Wide operating voltage range (2.0V to 5.5V)

• Industrial and Extended temperature ranges