TMS320DM6437 Evaluation Module - C6000 DSP...
Transcript of TMS320DM6437 Evaluation Module - C6000 DSP...
TMS320DM6437Evaluation Module
2006 DSP Development Systems
ReferenceTechnical
TMS320DM6437 Evaluation Module Technical Reference
509105-0001 Rev. C December 2006
SPECTRUM DIGITAL, INC.12502 Exchange Drive, Suite 440 Stafford, TX. 77477
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WARNING
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Copyright © 2006 Spectrum Digital, Inc.
Contents
1 Introduction to the DM6437 Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides you with a description of the DM6437 Evaluation Module, key features, and block diagram. 1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.7 Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-62 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the operation of the major board components on the DM6437 Evaluation Module. 2.1 EMIF Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 DDR2 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.2 Flash, NAND Flash, SRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Peripheral Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.1 VLYNQ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.2 UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.3 CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 Video Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3.1 Input Video Port Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3.2 On Chip Video Output DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.4 AIC33 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.4.1 Audio PLL/VCXO Circuit/PLL1705 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.5 Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.6 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.6.1 I/O Expanders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.6.2 I2C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.7 S/PDIF Analog, and Optical Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.8 Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.9 DM6437 Core CPU Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.10 DM6437 Core Voltage Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
3 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Describes the physical layout of the DM6437 Evaluation Module and its connectors. 3.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.2.1 J1, DAC A Video Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.2 J2, DAC B Video Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.3 J3, DAC C Video Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.4 J4, DAC A Video Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.5 J5, Video In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.6 J10, S/PDIF Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.2.7 J16, +5V Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.2.8 J20, Mini PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.2.9 J501, Embedded Mini USB Emulation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.2.10 P1, Video Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.2.11 P2, Video In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.2.12 P3, Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.2.13 P4, PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.2.14 P7, CAN Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.2.15 P8, RS-232 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.2.16 P10, Stereo Line In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.2.17 P11, Microphone In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.2.18 P12, Headphone Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.2.19 P13, Stereo Line Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.2.20 P14, S/PDIF Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.2.21 DC_P1, Memory/Video Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.2.22 DC_P2, Peripheral Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.2.23 DC_P3, VLYNQ Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.3 Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.3.1 JP1 Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.3.2 JP2 Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.3.3 JP3 Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3.3.4 JP4 Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3.4 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3.5 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.5.1 SW1, Bootload Mode Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.5.2 SW2, Bootload Configuration Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.5.3 SW3, EMDATA Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.5.4 SW4, 4 Position User Readable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.5.5 SW5, Power On Reset Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.5.6 SW6, Reset Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.5.7 SW7, Slide Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3.6 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Contains the schematics for the DM6437 Evaluation ModuleB Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Contains the mechanical information about the DM6437 Evaluation Module
About This Manual
This document describes the board level operations of the DM6437 Evaluation Module(EVM). The EVM is based on the Texas Instruments TMS320DM6437 Processor.
The DM6437 Evaluation Module is a table top card that allows engineers and softwaredevelopers to evaluate certain characteristics of the DM6437 processor to determine ifthe processor meets the designers application requirements. Evaluators can createsoftware to execute on board or expand the system in a variety of ways.
Notational Conventions
This document uses the following conventions.
The DM6437 Evaluation Module will sometimes be referred to as the DM6437 EVM orEVM.
Program listings, program examples, and interactive displays are shown in a specialitalic typeface. Here is a sample program listing.
equations!rd = !strobe&rw;
Information About Cautions
This book may contain cautions.This is an example of a caution statement.A caution statement describes a situation that could potentially damage your software,or hardware, or other equipment. The information in a caution is provided for yourprotection. Please read each caution carefully.
Related Documents, Application Notes and User Guides
Information regarding this device can be found at the following Texas Instrumentswebsite:
http://www.ti.com
Table 1: Manual History
Revision History
A Alpha Release
B Beta Release
Table 2: Board History
Revision History
A Alpha Release
B Beta Release
1-1
Chapter 1
Introduction to the DM6437 EVM
Chapter One provides a description of the DM6437 EVM along with thekey features and a block diagram of the circuit board.
Topic Page
1.1 Key Features 1-21.2 Functional Overview 1-31.3 Basic Operation 1-41.4 Memory Map 1-51.5 Configuration Switch Settings 1-61.6 Power Supply 1-61.7 Power Measurement 1-6
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1.1 Key Features
The DM6437 EVM is a PCI based or standalone development platform that enables
users to evaluate and develop applications for the TI DaVinciTM processor family.Schematics, list of materials, and application notes are available to ease hardwaredevelopment and reduce time to market.
The EVM comes with a full complement of on board devices that suit a wide variety ofapplication environments. Key features include:
• A Texas Instruments DM6437 processor operating up to 600 Mhz.
• 1 TVP5146M2 video decoder, supports composite or S video
• 4 video DAC outputs - component, RGB, composite (3 populated)
• 128 Mbytes of DDR2 DRAM
• UART, CAN I/O Interfaces
• 16 Mbytes of non-volatile Flash memory, 64 Mbytes NAND Flash, 2 Mbytes SRAM
• AIC33 stereo codec
• I2C Interface with onboard eeprom and expanders
• 10/100 MBS Ethernet Interface
• Configurable boot load options
• Embedded JTAG emulation interface
• 4 user LEDs and 4 position user switch
Figure 1-1, DM6437 EVM
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• Single voltage power supply (+5V)
• Expansion connectors for daughter card use
• VLYNQ Interface
• S/PDIF Interface, analog, and optical
1.2 Functional Overview of the DM6437 EVM
The DM6437 on the EVM interfaces to on-board peripherals through integrated deviceinterfaces and a 8-bit wide EMIF bus. The DDR2 memory is connected to its owndedicated 32 bit wide bus. The EMIF bus is jumper selectable to be connected to theFlash, SRAM, NAND, and daughter card expansion connectors which are used foradd-on boards.
On board video decoder and on chip encoders interface video streams to the DM6437processor. One TVP5146M2 decoder and 4 on chip DAC channels are standard on theEVM (only 3 output connectors are populated so that the board can fit in a PCI slot). On screen display functions are implemented in software on the DM6437 processor.
An on-board AIC33 codec allows the DSP to transmit and receive analog audio
signals. The I2C bus is used for the codec control interface, while the McBSP controlsthe audio stream. Signal interfacing is done through 3.5mm audio jacks that correspondto microphone input, line input, line output, and headphone outputs.
The EVM includes 4 user LEDs, and 4 position user DIP switch which can be used toprovide the user with interactive feedback. These interfaces are implemented via
I2C expanders.
Figure 1-2, Block Diagram DM6437 EVM
VLNQMini PCI
ENETRJ45
SVHSIN
PW
R
MIC IN
LINE IN
LINE OUT
NORFlash
32
EMIF
Video Port
McBSP1 or McASP0
PCI Connector
I2C Bus
LEDs
Ext JTAG
RS-232
US
BE
MU
RST
12AEM2
AEM1AEM0
AEAW2
PCI
NA
ND
Fla
sh
SR
AM
1 2 3 4
CAN
HP Out
3.3V I/O Supply
DA
C A POR
1.2V Core Supply
1.8V Supply
Video IN
DIP
DD
R2
DD
R2
SPI ROM
EmbeddedJTAG Emulator
AIC33Codec
DACOut
UART/CAN Switches
UARTs
ENETPHY
MII
S/PDIF(optical)
S/PDIF
DM6437 McBSP0SVHSOUT
DAC D
DAC C
DAC B
VideoDecoder
34
12
34
56
7
BM0BM1BM2BM3
FASTB
JTAGDC
_P1
DC
_P2
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VLYNQ, and ethernet MAC interfaces are integrated peripherals on the DM6437processor exploiting its system on a chip architecture. VLYNQ is available when thePCI is not used.
An included 5V external power supply is used to power the board. On-board switchingvoltage regulators provide the +1.2V CPU core voltage and +3.3V for peripherals and+1.8V DDR2 memory. The board is held in reset until these supplies are withinoperating specifications.
Code Composer communicates with the EVM through an embedded emulator or viathe 14 pin external JTAG connector.
1.3 Basic Operation
The EVM is designed to work with TI’s Code Composer Studio development. CodeComposer communicates with the board through the embedded emulator or anexternal JTAG emulator. To start, follow the instructions in the Quick Start Guide toinstall Code Composer. This process will install all of the necessary development tools,documentation and drivers.
Detailed information about the EVM including examples and reference material isavailable on the EVM’s CD-ROM.
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1.4 Memory Map
The DaVinci family of processors have a large byte addressable address space, somelimitations to byte addressing are determined by peripheral interconnection to theDM6437 device. Program code and data can be placed anywhere in the unifiedaddress space. Addresses are multiple sizes depending on hardware implementation.Refer to the appropriate device data sheets for more details.
The memory map shows the address space of a DM6437 processor on the left withspecific details of how each region is used on the right. By default, the internal memorysits at the beginning of the address space. Portions of memory can be remapped insoftware as L2 cache rather than fixed RAM.
The part incorporates a dual EMIF interface. One dedicated EMIF directly interfaces tothe DDR2 memory. The Flash, NAND Flash, or SRAM are mapped into CS2 space andselectable via JP2. When CS2 is used for daughter card interfacing JP2 must be setappropriately.
Cache/RAM
DM6437 EVMAddress0x10800000
0x42000000
0x44000000
0x48000000
0x4C000000
0x80000000
Figure 1-3, Memory Map, DM6437 EVM
CS2
CS3
0x46000000CS4
CS5
VLNQ
DDR
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1.5 Configuration Switch Settings
The EVM has a two configuration switches that allow users to control the operationalstate of the processor when it is released from reset. The configuration switches arelabeled SW1 and SW2 on the EVM board.
Switch SW1 configures the boot mode that will be used when the DSP starts executing.By default the switches are configured to EMIF boot (out of 8-bit Flash). The DM6437EVM only supports little endian mode and is not configurable. Refer to section 3.5.1 forthe boot load options using switch SW1.
1.6 Power Supply
The EVM operates from a single +5V external power supply connected to the mainpower input (J16), a 2.5 MM. barrel-type plug. Internally, the +5V input is convertedinto +1.2V, +1.8V and +3.3V using Texas Instruments swift voltage regulators. The+1.2V supply is used for the DSP core while the +3.3V supply is used for the DSP's I/Obuffers and other chips on the board. The +1.8 volt supply is used for DM6437DDR2 interface, and DDR2 memory.
There are three power test points on the EVM; TP23, TP34, and TP38. These testpoints provide a convenient mechanism to check the EVM’s multiple power supplies.The table below shows the voltages for each test point and what the supply is used for.
1.7 Power Measurement
The EVM supports power test points to allow measurement of the various power railson the DM6437 device. Series resistors are used in the device’s power domainsthereby measuring the voltage across these resistors. The current can be calculatedvia V = I * R.
Refer to the test point section in chapter 3 for detailed information on measuring currenton the DM6437 device.
Table 1: Power Test Points
Test Point Voltage Voltage Use
TP23 +1.2 V DM6437 Core
TP34 +3.3V DSP I/O and logic
TP38 +1.8 V DDR2 Memory, DSP I/O, and logic
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Chapter 2
Board Components
This chapter describes the operation of the major board components onthe DM6437 EVM.
Topic Page
2.1 EMIF Interfaces 2-22.1.1 DDR2 Memory Interface 2-22.1.2 Flash, NAND Flash, SRAM Memory Interface 2-22.2 Peripheral Interfaces 2-22.2.1 VLYNQ Interface 2-22.2.2 UART Interface 2-22.2.3 CAN Interface 2-32.3 Video Interfaces 2-32.3.1 Input Video Port Interfaces 2-32.3.2 On Chip Video Output DACs 2-32.4 AIC33 Interface 2-42.4.1 Audio PLL/VCXO Circuit/PLL1705 Clock Generator 2-52.5 Ethernet Interface 2-62.6 I2C Interface 2-62.6.1 I/O Expanders 2-72.6.2 I2C EEPROM 2-92.7 S/PDIF Analog, and Optical Interfaces 2-92.8 Daughter Card Interface 2-102.9 DM6437 Core CPU Clock 2-102.10 DM6437 Core Voltage Select 2-10
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2.1 EMIF Interfaces
A separate 8 bit EMIF with multiple chip selects divide up the address space and allowfor asynchronous accesses on the EVM. On board the CS2 is used for Flash, NANDFlash, or SRAM.
2.1.1 DDR2 Memory Interface
The DM6437 device incorporates a dedicated 32 bit wide DDR2 memory bus. TheEVM uses two 512 megabit 16 bit wide memories on this bus, for a total of 128megabytes of memory for program, data, and video storage. The internal DDRcontroller uses a PLL to control the DDR memory timing. The interface supports ratesup to 166 Mhz., and is clocked on differential edges for optimal performance. Memoryrefresh for DDR2 is handled automatically by the DM6437 internal DDR controller.
2.1.2 Flash, NAND Flash, SRAM Memory Interface
The DM6437 has 16 megabytes of NOR Flash, or 64 megabytes of NAND Flash, or2 megabyte of SRAM memory mapped into the CS2 space. This NOR Flash memory,and NAND Flash memory are used primarily for boot loading. SRAM is used fordebugging application code. The CS2 space is configured as 8 bits wide on theDM6437 EVM for NOR Flash, SRAM, or NAND flash usage.
2.2 Peripheral Interfaces
The DM6437 has several peripheral interfaces which allow the user to interface toexternal devices. These interfaces are outlined in the following sections.
2.2.1 VLYNQ Interface
The DM6437 brings its internal VLYNQ interface out to a mini PCI connector J20 andsmall 20 pin connector DC_P3. The VLYNQ interface is multiplexed on the PCI/EM busand this bus must be reconfigured after boot up to support VLYNQ. A multiplexer isused to minimize board layout stubs and allow as direct as possible interface for theVLYNQ signals. VLYNQ is not operational if the board is used in a PCI slot.
2.2.2 UART Interface
The internal UART0 on the DM6437 device is driven to connector P8. The UART’sinterface is routed to a Texas Instruments MAX3221 RS-232 line driver prior to beingbrought out to a male DB-9 connector, P8. The on board UART signals can be disabledby pulling the RS232_ENABLEn signal high via the daughter card connectors.
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2.2.3 CAN Interface
The internal CAN controller on the DM6437 device is driven to connector P7. Thecontroller is routed to a Texas Instruments SN65HVD235 CAN controller prior to beingrouted to female DB-9 connector, P7. The on board CAN signals can be disabled bypulling CAN_ENABLEn high via the daughter card connector.
2.3 Video Interfaces
The DM6437 EVM has video input and output ports to support a variety of userapplications. These are discussed in the two sections below.
2.3.1 Input Video Port Interfaces
The DM6437 EVM supports video capture via the devices internal video ports. A TexasInstruments TVP5146M2 is used to decode composite video or S-video inputs into thedevice. P2 is used for the S-video inputs and J5 for the composite inputs on the EVM.
User inputs can be driven via daughter card connector DC_P1 when the on board CBTsare disabled by driving control TVP5146_ENABLEn signal high on DC_P1.
2.3.2 On Chip Video Output DACs
The DM6437 incorporates 4 output DACs to interface to various output standards. TheDACs are buffered via opamps and driven to four RCA jacks, J1-J4. The outputs of theDACs are programmable to support composite video, component video, or RGB.
S-video output is available from connector P1. This connector is driven by video DACsB and C from the DM6437. Video DAC B is the chroma and video DAC C is the luma.
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2-4 DM6437 EVM Technical Reference
2.4 AIC33 Interface
The EVM uses a Texas Instruments TLV320AIC33 stereo codec for input and output ofaudio signals. The codec samples analog signals on the microphone or line inputs andconverts them into digital data so it can be processed by the DSP. When the DSP isfinished with the data it uses the codec to convert the samples back into analog signalson the line output so the user can hear the output.
The codec communicates using two serial channels, one to control the codec’s internal
configuration registers and one to send and receive digital audio samples. The I2C busis used as the unidirectional control channel. The control channel is generally only usedwhen configuring the codec, it is typically idle when audio data is being transmitted,
The default configuration is to use the McBSP is used as the bi-directional datachannel. However, optionally the McASP can be used to drive the data channel. Data
channel selection is controller via an on board I2C expander. All audio data flowsthrough the data channel. Many data formats are supported based on the threevariables of sample width, clock signal source and serial data format. The EVMexamples generally use a 16-bit sample width with the codec in master mode so itgenerates the frame sync and bit clocks at the correct sample rate without effort on theDSP side.
The codec has a programmable clock from a PLL1705 PLL device. The default systemclock is 18.432 Mhz. The internal sample rate generate subdivides the 18.432 MHzclock to generate common frequencies such as 48KHz and 8KHz. The sample rate isset by a codec register. The figure below shows the codec interface on the DM6437EVM.
Figure 2-2, DM6437 EVM CODEC INTERFACE
DOUTDIN
BCLKWCLK
MIC IN
LINE IN
LINE OUT
HP OUT
McASP or McBSP
I2S Format
AIC33 Codec
Digital Analog
MIC IN
LINE IN
LINE OUT
HP OUT
SCLSDA
I2CControlSCL
SDAI2C Format
DXDRCLKRCLKXFSRFSX
Control Registers
ADC
DAC
AXR[0]AXR[1]ACLKRACLKXAFSRAFSX
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2-5
2.4.1 Audio PLL/VCXO Circuit/PLL1705 Clock Generator
The DM6437 EVM implements a multiple PLL clock generator for creating the Audioclocks for the board.
In streaming video applications the audio and video sequences can losesynchronization. The DM6437 uses a VCXO interpolation circuit to incrementally speedup or slow down the STCLK input to allow for this synchronization to remain locked.
The PWM1 and timer inputs on DM6437 are used to control this feature. The PWM0pin drives a PICX100-27W Voltage Controlled Oscillator which is and fed back into thetimer input pin.
The STCLK is also a source clock for the PLL1705 programmable PLL device. Thisdevice creates the clocks for the AIC33 Codec, daughter card VIDCLK an AUDIOCLK.
The PLL1705 is programmable via an I2C and Expander U13. Software sequencing onthe I/O expander is required to interface correctly to the PLL1705’s programmableinputs.
The diagram below is a simplified diagram of this clocking scheme.
DM6437
VCXOCircuit UsingPICX100-27
PLL1705
SCK03SCK02
MCK02MCK01
XT1
PWM1 IN
PLLMS
PLLMC
PLLMD
To I/O Expander
Figure 2-3, Audio PLL/VCXO Circuit/PLL1705 Clock Generator
STCLKTIMER
AUDIO_CLKSCK01SCK00
VID_CLK
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2-6 DM6437 EVM Technical Reference
2.5 Ethernet Interface
The DM6437 integrates an ethernet MAC on chip. This interface is routed to the PHYvia CBT switches. The EVM uses an Micrel KS8001L PHY. The 10/100 Mbitinterface is isolated and brought out to a RJ-45 standard ethernet connector, P3. The
PHY directly interfaces to the DM6437. The ethernet address is stored in the I2C serialROM during manufacturing.
The RJ-45 has 2 LEDs integrated into its connector. The LEDs are green and yellowand indicate the status of the ethernet link. The green LED, when on, indicates link andwhen blinking indicates link activity. The yellow LED, when illuminated, indicates fullduplex mode.
2.6 I2C Interface
The I2C bus on the DM6437 is ideal for interfacing to the control registers of many
devices. On the DM6437 EVM the I2C bus is used to configure the video decoder,
stereo Codec, I/O expanders. An I2C ROM is also interfaced via the serial bus. Theformat of the bus is shown in the figure below.
The addresses of the on board peripherals are shown in the table below.
Table 1: I2C Memory Map
Device Address R/W Device Function
TVP5146M2 0x5D R/W U50 Video Decoder
PCF 8574A 0x38 R/W U10 User Input
PCF 8574A 0x39 R/W U11 User LEDs
PCF 8574A 0x3A R/W U13 PLL, User I/O
PCF8574A 0x3B R/W U64 User I/O
TLV320AIC33 0x1B R/W U43 CODEC
24WC256 0x50 R/W U25 I2C EEPROM
Figure 2-4, I2C Bus Format
Start Slave Address W ACK Sub Address ACK-S Data ACK-S Stop
Write Sequence
Start Slave Address R Data STOP
Read Sequence
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2-7
2.6.1 I/O Expanders
The DM6437 EVM uses four I2C expanders to handle various bit I/O functions. Eachof these is an 8 bit I/O expander, a PCF8574A. At Power Up Reset the expanders areinitialized to 0xFF, all ones. The functions for each of the I/O expanders are shown inthe tables below.
Table 2: U10 I/O Expander
Pin Number Function Decription
P0 JP1 NTSC/PAL Select Read only video mode,1=NTSC,0=PAL
P1 SW7 Slide Switch Read only slide switch
P2 Reserved None
P3 Reserved None
P4 SW4-1 Read only user switch
P5 SW4-2 Read only user switch
P6 SW4-3 Read only user switch
P7 SW4-4 Read only user switch
Table 3: U11 I/O Expander
Pin Number Function Description
P0 User LED DS1 0=Turns LED on, 1=Turns LED off
P1 User LED DS2 0=Turns LED on, 1=Turns LED off
P2 User LED DS3 0=Turns LED on, 1=Turns LED off
P3 User LED DS4 0=Turns LED on, 1=Turns LED off
P4 VLYNQ Reset 0=Removes Reset, 1=Applies Reset
P5 Reserved None
P6 User I/O DC_P2 To daughter card, DC_P2 Pin 81
P7 User I/O DC_P2 To daughter card, DC_P2 Pin 82
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2-8 DM6437 EVM Technical Reference
* only one should be enabled at a time
Table 4: U13 I/O Expander
Pin Number Function Mode Description
P0 User I/O RW Daughter Card, DC_P2 Pin 87
P1 User I/O RW Daughter Card, DC_P2 Pin 88
P2 User I/O RW Daughter Card, DC_P2 Pin 85
P3 User I/O RW Daughter Card, DC_P2 Pin 84
P4 PLL -SR W Write PLL1705 SR Pin
P5 PLL - FS2 W Write PLL1705 FS2 Pin
P6 PLL - FS1 W Write PLL1705 FS1 Pin
P7 PLL-CSEL W Write PLL1705 CSEL Pin
Table 5: U64 I/O Expander
Pin Number Function Description
P0 McBSP_Enable to AIC23 * 1=Enable, 0=Disable
P1 McASP_Enable to AIC23 * 0=Enable, 1=Disable
P2 SPDIF Enable * 0=Enable, 1=Disable
P3 Reserved None
P4 Reserved None
P5 Reserved None
P6 Reserved None
P7 Core Voltage Select 0 = 1.05 Volt, 1 = 1.2 Volt
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2.6.2 I2C EEPROM
The DM7436 EVM incorporates an I2C eeprom that can be used for booting orgeneral purpose storage.
This eeprom is also used to store the ethernet MAC address and the board’s revision.The MAC address is also labeled on the board. Care should be taken not to erasethese items when user information is stored in the eeprom. Spectrum Digital usesaddresses 0x7F00 to 0x7FFF for manufacturing information. This information isshown in the table below.
2.7 S/PDIF Analog, and Optical Interfaces
The McBSP’s FSR pin on the DM6437 can be configured to operate as a S/PDIFtransmitter. The DM6437 EVM supports both analog and optical interfaces. Theanalog S/PDIF output pin is routed to a driver and filter circuit before being output on
J10. I2C Expander U64 output P2 is used to enable the S/PDIF interface. When S/PDIF is selected on the expamder (P2=0), the McASP enable should be disabled andthe McBSP enable should be disabled.Another driver is used to interface the opticaltransmitter P14. When the S/PDIF interface is enabled the TLV320AIC33 codec isdisabled, the WCLK should be disabled prior to enabling the S/PDIF output.
The McBSP interface can be disabled for daughter card use by pulling theAIC_ENABLEn signal high from the daughter card connector.
Table 6: DM6437 MAC Addresses
Address Contents
0x7F00 EMAC Address 0 (most significant)
0x7F01 EMAC Address 1
0x7F02 EMAC Address 2
0x7F03 EMAC Address 3
0x7F04 EMAC Address 4
0x7F05 EMAC Address 5
0x7F06 Reserved
0x7F07 Board Revision
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2-10 DM6437 EVM Technical Reference
2.8 Daughter Card Interfaces
The EVM provides expansion connectors that can be used to accept plug-in daughtercards. The daughter card allows users to build on their EVM platform to extend itscapabilities and provide customer and application specific I/O. The expansionconnectors are for all major interfaces including memory, peripherals, and videoexpansion.
The pin outs for this interface are documented in Section 3.
The connectors provide access to the DSP’s EMIF signals to interface with memoriesand memory mapped devices. The video capture port is brought out to the daughtercard interface.
Several signals are used to disable the on board video peripherals so that they can beused by the expansion connector. The table below indicates the operation of thesesignals.
Other than the buffering, most daughter card signals are not modified on the board.
2.9 DM6437 Core CPU Clock
The DM6437 EVM uses a 27 Megahertz crystal to generate the input clock. TheDM6437 has an internal PLL which can multiply the input clock to generate the internalclock. The PLL multiplier is set via software on the DM6437 device.
2.10 DM6437 Core Voltage Select
The DM6437 EVM has the ability to adjust the core voltage between 1.2 volts and
1.05 volts. an I/O expander is used to control this I2C feature.
Table 7: Daughter Card Interface
Signal Function
AIC33_ENABLEn Disconnects CPU from on board codec
CI_EMA_ENABLEn Disables CI0 to CI7 from upper on board EMIF address lines
MEM_EMD7-0_ENABLEn Disables CPU from on board data bus
VIC_TINPOL_ENABLEn Disable CPU TINPOL pin from on board use
ENET_ENABLEn Disconnects CPU from on board ethernet PHY
CAN_ENABLEn Disconnects CPU from on board CAN
RS232_ENABLEn Disconnects CPU from on board UART
TVP5146_ENABLEn Disconnects CPU from on board video decoder
3-1
Chapter 3
Physical Description
This chapter describes the physical layout of the DM6437 EVM and itsinterfaces.
Topic Page
3.1 Board Layout 3-33.2 Connectors 3-43.2.1 J1, DAC A Video Out 3-53.2.2 J2, DAC B Video Out 3-53.2.3 J3, DAC C Video Out 3-53.2.4 J4, DAC D Video Out 3-63.2.5 J5, Video In 3-63.2.6 J10, S/PDIF Out 3-73.2.7 J16, +5V Input 3-73.2.8 J20, Mini PCI Interface 3-83.2.9 J501, Embedded Mini USB Emulation Interface 3-93.2.10 P1, Video Out 3-93.2.11 P2, Video In 3-103.2.12 P3, Ethernet Interface 3-103.2.13 P4, PCI Connector 3-113.2.14 P7, CAN Connector 3-133.2.15 P8, RS-232 UART 3-153.2.16 P10, Stereo Line In 3-153.2.17 P11, Microphone In 3-153.2.18 P12, Headphone Out 3-153.2.19 P13, Stereo Line Out 3-163.2.20 P14, S/PDIF Out (Optical) 3-163.2.21 DC_P1, Memory/Video Expansion 3-173.2.22 DC_P2, Peripheral Expansion 3-183.2.23 DC_P3, VLYNQ Connector 3-19
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3-2 DM6437 EVM Technical Reference
Topic Page
3.3 Jumpers 3-193.3.1 JP1 Jumper 3-203.3.2 JP2 Jumper 3-203.3.3 JP3 Jumper 3-213.3.4 JP4 Jumper 3-213.4 LEDs 3-213.5 Switches 3-223.5.1 SW1, Bootload Mode Selections 3-223.5.2 SW2, Bootload Configuration Select 3-233.5.3 SW3, EMIF Data Select 3-233.5.4 SW4, 4 Position User Readable 3-233.5.5 SW5, Power On Reset Switch 3-233.5.6 SW6, Reset Switch 3-233.5.7 SW7, Slide Switch 3-243.6 Test Points 3-25
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3.1 Board Layout
The DM6437 EVM is a 8.75 x 4.5 inch (210 x 115 mm.) ten (10) layer printed circuitboard which is powered by an external +5 volt only power supply. Figure 3-1 shows thelayout of the DM6437 EVM.
Figure 3-1, DM6437 EVM, Interfaces Top Side
SW2
J5
J501
P11
J16
J10
DC_P1
J4 P1J2
SW6
DC_P2
P3
P4
P2
P8
J1
DS501
DS5
J3
DS1-DS4
J6
J5
P7
P10
P14
P12P13
SW4
SW5
SW7
SW3
SW1
JP4
JP3
JP1
JP2
DC_P3
J20
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3-4 DM6437 EVM Technical Reference
3.2 Connectors
The EVM has twenty three (23) connectors providing interfaces to various peripherals.These connectors are described in the following sections.
* Not populated
Table 1: Connectors
Connector Size Function
J1 RCA DAC A *
J2 RCA DAC B
J3 RCA DAC C
J4 RCA DAC D
J5 RCA Video In
J6 14 External Emulation Header
J10 RCA S/PDIF Out
J16 2.5 mm +5V In
J20 2 x 62 Mini PCI Interface
J501 Mini USB Embedded USB Emulation Interface
P1 4 Pin DIN S-Video Out
P2 4 Pin DIN S-Video In
P3 RJ-45 Ethernet
P4 PCI PCI
P7 9 Pin D-sub CAN
P8 9 Pin D-sub RS-232 UART
P10 3.5 mm Stereo Line In
P11 3.5 mm Microphone In
P12 3.5 mm Headphone Out
P13 3.5 mm Stereo Line Out
P14 Optical S/PDIF Out
DC_P1 2x50 Expansion
DC_P2 2x45 Expansion
DC_P3 2x10 Expansion
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3.2.1 J1, DAC A Video Out
J1 is an RCA jack used to interface to DAC A of the DM6437 to a video device. Thisconnector is driven directly by the VPSS back end via an opamp. This connector is notinstalled for clearance reasons when using the PCI bus. The pinout of this connector isshown below.
3.2.2 J2, DAC B Video Out
J2 is an RCA jack used to interface to DAC B of the DM6437 to a video device. Thisconnector is driven directly by the VPSS back end via an opamp. This connector is notinstalled for clearance reasons when using the PCI bus. The pinout of this connector isshown below.
3.2.3 J3, DAC C Video Out
J3 is an RCA jack used to interface to DAC C of the DM6437 to a video device. Thisconnector is driven directly by the VPSS back end via an opamp. This connector is notinstalled for clearance reasons when using the PCI bus. The pinout of this connector isshown below.
Figure 3-2, J1, RCA Jack
Shield (ground)
Signal Output
Figure 3-3, J2, RCA Jack
Shield (ground)
Signal Output
Figure 3-4, J3, RCA Jack
Shield (ground)
Signal Output
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3-6 DM6437 EVM Technical Reference
3.2.4 J4, DAC D Video Out
J1 is an RCA jack used to interface to DAC D of the DM6437 to a video device. Thisconnector is driven directly by the VPSS back end via an opamp. This connector is notinstalled for clearance reasons when using the PCI bus. The pinout of this connector isshown below.
3.2.5 J5, Video In
J5 is an RCA jack used as a video input to the TVP5146M2 video decoder. Thisconnector brings in a video signal to the TVP5146M2. Do NOT plug into thisconnector with the power on. The figure below shows this connector as viewed from thecard edge.
Table 2: J5, Video In, RCA Jack
Pin # Signal Name
1 Pin 8, TVP5146M2
2 GND
Figure 3-5, J4, RCA Jack
Shield (ground)
Signal Output
Figure 3-6, J5, Video In RCA Jack
Pin 2, Shield (ground)
Pin 1, Signal Input
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3.2.6 J10, S/PDIF Out
J10 is an RCA jack used as an analog output from the McBSP FSR signal on the DSP.This connector brings out the SPDIF signal. Do NOT plug into this connector with thepower on. The figure below shows this connector as viewed from the card edge.
3.2.7 J16, +5V Input
Connector J16 is the input power connector. This connector bring in +5 volts to theEVM. This is a 2.5 mm. jack. The figure below shows this connector as viewed fromthe card edge.
Table 3: J10, S/PDIF, RCA Jack
Pin # Signal Name
1 S/PDIF Analog output
2 GND
Figure 3-7, J10, S/PDIF Out, RCA Jack
Pin 2, Shield (ground)
Pin 1, Signal Output
PC Board
J14+5V
Ground
Front ViewFigure 3-8, J16, +5 Volt Input Connector
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3-8 DM6437 EVM Technical Reference
3.2.8 J20, Mini PCI Interface
Connector J20 provides a mini-PCI on the DM6437 EVM. Do NOT plug into thisconnector with the power on. The table below shows the signals on this connector.
Table 4: J16, VLYNQ Card Interface
Pin # Signal
2,3,4,5,6,7,8,10,11,12,13,15,17,18,29,30,38,39,47,49,51,53,55,57,71,73,75,77,80,82,84,86,93,98,100,104,105,106,107,108,109,113,115,116,117,118,120,122,123,
124
NC
9,14,20,23,25,2732,33,34,35,37,41,42,44,45,46,48,50,52,54,56,58,60,62,64,66,68,69,72,74,76,78,79,81,83,85,87,90,91,92,94,95,
96,99,101,102, 110,114,119
GND
111 VCC_1.8V
1,19,28,31,40,63,70,88,89
VCC_3.3V
97,103 VCC_5V
16 VLYNQ_CLK
21 VLYNQ_RXD0
22 VLYNQ_RXD1
24 VLYNQ_SCRUN
26 VLYNQ_RESET
59 VLYNQ_RXD2
61 VLYNQ_RXD3
36 VLYNQ_TXD0
65 VLYNQ_TXD2
67 VLYNQ_TXD3
43 VLYNQ_TXD1
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3.2.9 J501, Embedded Mini USB Emulation Interface
This connector allows the user to run software development tools and emulationwithout an external emulator. The signals on this connector are shown in the tablebelow.
3.2.10 P1, Video Out
Connector P1 is a four pin mini din connector which interfaces to an S-video outputdisplay device. This connector brings out the DAC B and DAC C. Do NOT plug into thisconnector with the power on. The figure below shows this connector as viewed from thecard edge.
Table 5: J501, Embedded Mini USB Emulation Interface
Pin # Signal Name
1 VBUS
2 D-
3 D+
4 ID (not used)
5 Ground
Table 6: P1, Video Out, Mini Din Connector
Pin # Signal Name
1 Ground
2 Ground
3 DAC_IOUTB, Luma
4 DAC_IOUTC, Chroma
Pin 1 Pin 2Pin 3 Pin 4
Figure 3-9, P1, Front View, Mini Din Connector
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3-10 DM6437 EVM Technical Reference
3.2.11 P2, Video In
Connector P2 is a four pin mini din S-video connector which interfaces to theTVP5146M2 encoder. This connector brings in a video signal (LUMA) to pin 9 on theTVP5146M2. Do NOT plug into this connector with the power on. The figure belowshows this connector as viewed from the card edge.
3.2.12 P3, Ethernet Interface
The P3 connector is used to provide an 10/100 Mbps Ethernet interface. This is astandard RJ-45 connector. The pinout for the P3 connector is shown in the table below.
Two LEDs are embedded into the connector to report link status.
Table 7: J11, Video In, Mini Din Connector
Pin # Signal Name
1 GND
2 GND
3 LUMA
4 Chroma
Table 8: P3, Ethernet Interface
Pin # Signal Pin # Signal
1 LXT_TDP 2 LXT_TDM
3 LXT_RDP 4 LXT_TDCT
5 NC 6 LXT_RDM
7 NC 8 GND
Table 9: Ethernet LEDs
LED # Color
LED1 Green
LED2 Yellow
Pin 1 Pin 2Pin 3 Pin 4
Figure 3-10, P2,Front View, Mini Din Connector
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3-11
3.2.13 P4, PCI Connector
The P4 connector is a card edge PCI interface. This connector has an “A” and “B” side.Because of the card seating notches the pin numbers are not contiguous. The “B” sideis the top component side. The I/O direction field is referenced from the PCI slot.
Table 10: P4, PCI Connector, “A” Side
Pin Signal I/O Description Pin Signal I/O Description
1 TRST- Not Used 2 +12 Volts Not Used
3 TMS Not Used 4 TDI I/O Tied to TDO
5 +5 Volts +5 Volts Power 6 INTA- O Interrupt Out
7 INTC- O Interrupt Out 8 +5 Volts +5 Volts Power
9 Rsvd.0 Not Used 10 +V I/O Not Used
11 Rsvd.1 Not Used 12 Key.1 Key
13 Key.2 Key 14 +3.3 Vaux Not Used
15 RST- I PCI_Resetn 16 +V I/O O Not Used
17 GNT- O Grant- 18 GND Ground
19 PME- 20 AD30 I/O/Z Address/Data 30
21 +3.3 Volts Not Used 22 AD28 I/O/Z Address/Data 28
23 AD26 I/O/Z Address/Data 26 24 GND
25 AD24 I/O/Z Address/Data 24 26 IDSEL I Initialization Device Select
27 +3.3 Volts Not Used 28 AD22 I/O/Z Address/Data 22
29 AD20 I/O/Z Address/Data 20 30 GND Ground
31 AD18 I/O/Z Address/Data 18 32 AD16 I/O/Z Address/Data 16
33 +3.3 Volts Not Used 34 FRAME- I Frame
35 GND Ground 36 TRDY- I/O/Z Target Ready
37 GND Ground 38 STOP- I/O/Z Stop Direction
39 +3.3 Volts Not Used 40 SDONE O Done
41 SBO- 42 GND Ground
43 PAR I/O/Z Parity 44 AD15 I/O/Z Address/Data 15
45 +3.3 Volts Not Used 46 AD13 I/O/Z Address/Data 13
47 AD11 I/O/Z Address/Data 11 48 GND Ground
49 AD9 I/O/Z Address/Data 9 50 Key.3 Key
51 Key.4 Key 52 C/BE0 Command/Byte Enable0
53 +3.3 Volts Not Used 54 AD6 I/O/Z Address/Data 6
55 AD4 I/O/Z Address/Data 4 56 GND Ground
57 AD2 I/O/Z Address/Data 2 58 AD0 I/O/Z Address/Data 0
59 +V I/O Not Used 60 REQ64- Not Used
61 +5 Volts +5 Volts Power 62 +5 Volts +5 Volts Power
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The signals on the “B” side of the connector are shown in the table below.
Table 11: P4, PCI Connector, “B” Side
Pin Signal I/O Description Pin Signal I/O Description
1 -12 Volts Not Used 2 TCK I Not Used
3 GND Ground 4 TDO I Tied to TDO
5 +5 Volts +5 Volt Power 6 +5 Volts I +5 Volt Power
7 INTB- Interrupt OUT 8 INTD- Interrupt Out
9 PRSNT1- O Power Requirement 10 Rsvd.2
11 PRSNT2- O Power Requirement 12 Key.5 Key
13 Key.6 Key 14 Rsvd.3
15 GND Ground 16 CLK System Clock
17 GND Ground 18 REQ-
19 +V I/O Not Used 20 AD31 I/O/Z Address/Data 31
21 AD29 I/O/Z Address/Data 29 22 GND Ground
23 AD27 I/O/Z Address/Data 27 24 AD25 I/O/Z Address/Data 25
25 +3.3 Volts Not Used 26 C/BE3 I/O/Z Command/Byte Enable 3
27 AD23 I/O/Z Address/Data 23 28 GND Ground
29 AD21 I/O/Z Address/Data 21 30 AD19 I/O/Z Address/Data 19
31 +3.3 Volts Not Used 32 AD17 I/O/Z Address/Data 17
33 C/BE2- I/O/Z Command/Byte Enable 2 34 GND Ground
35 IRDY- I Initiator Ready 36 +3.3 Volts Not Used
37 DEVSEL- I/O/Z Device Select 38 GND Ground
39 LOCK- I Resource Locked 40 PERR- I/O/Z Parity Error
41 +3.3 Volts Not Used 42 SERR- O System Error
43 +3.3 Volts Not Used 44 C/BE1- I/O/Z Command/Byte Enable 1
45 AD14 I/O/Z Address/Data 14 46 GND Ground
47 AD12 I/O/Z Address/Data 12 48 AD10 I/O/Z Address/Data 10
49 M66EN O 66 Mhz Enable 50 Key.7 Key
51 Key.8 Key 52 AD8 I/O/Z Address/Data 8
53 AD7 I/O/Z Address/Data 7 54 +3.3 Volts Not Used
55 AD5 I/O/Z Address/Data 5 56 AD3 I/O/Z Address/Data 3
57 GND Ground 58 AD1 I/O/Z Address/Data 1
59 +V I/O Not Used 60 ACK64- Not Used
61 +5 Volts +5 Volt Power 62 +5 Volts +5 Volt Power
Spectrum Digital, Inc
3-13
3.2.14 P7, CAN Connector
The DM6437 EVM has a 9 Pin female D-connector which brings out the CAN transmitand receive signals. This CAN interface uses the SN65HVD235 CAN driver. The pinpositions for the P7 connector as viewed from the edge of the printed circuit board areshown below.
The pin numbers and their corresponding signals are shown in the table below.
Table 12: P7, CANA Pinout
Pin # Signal Name
1 No Connect
2 CANL
3 GND
4 No Connect
5 No Connect
6 No Connect
7 CANH
8 No Connect
9 No Connect
Figure 3-11, P7, DB9 Female Connector
6789
12345
Spectrum Digital, Inc
3-14 DM6437 EVM Technical Reference
3.2.15 P8, RS-232 UART Connector
The DM6437 EVM has an RS-232 connector which brings out the SCI transmit andreceive signals to be used as UART. This UART uses the MAX3221 RS-232 line driverand is routed to a male 9 pin D-connector, P8. The pin positions for the P8 connectoras viewed from the edge of the printed circuit board are shown below.
The pin numbers and their corresponding signals are shown in the table below. Thiscorresponds to a standard dual row to DB-9 connector interface used on personalcomputers.
Table 13: P8, RS-232 UART Pinout
Pin # Signal Name
1 No Connect
2 RXD
3 TXD
4 No Connect
5 GND
6 No Connect
7 No Connect
8 No Connect
9 No Connect
Figure 3-12, P8, DB9 Male Connector
6789
12345
Spectrum Digital, Inc
3-15
3.2.16 P10, Audio Line In Connector
The audio line in is a stereo input. The input connector is a 3.5 mm stereo jack. Thesignals on the mating plug are shown in the figure below.
3.2.17 P11, Microphone Connector
The input is a 3.5 mm. stereo jack. Both inputs are connected to the microphone so it ismonaural. The signals on the plug are shown in the figure below.
3.2.18 P12, Headphone Connector
Connector P12 is a headphone/speaker jack. It can drive standard headphones or ahigh impedance speaker directly. The standard 3.5 mm jack is shown in the figurebelow.
Left Line In
Ground
Figure 3-13, Audio Line In Stereo Jack
Right Line In
Microphone In
Ground
Figure 3-14, Microphone Stereo Jack
Microphone Bias
Left Headphone
Ground
Figure 3-15, Headphone Jack
Right Headphone
Spectrum Digital, Inc
3-16 DM6437 EVM Technical Reference
3.2.19 P12, Audio Line Out Connector
The audio line out is a stereo output. The output connector is a 3.5 mm stereo jack. Thesignals on the mating plug are shown in the figure below.
3.2.20 P14, S/PDIF Out (Optical)
P14 is an optical transmitter connector used as an output from the McBSP FSR signalon the DM6437 DSP. This connector brings out an optical S/PDIF signal. Do NOT pluginto this connector with the power on. The figure below shows this connector as viewedfrom the card edge.
Left Line Out
Ground
Figure 3-16, Audio Line Out Stereo Jack
Right Line Out
Spectrum Digital, Inc
3-17
3.2.21 DC_P1, Memory/Video Expansion-
Table 14: DC_P1, Memory/Video Expansion
Pin Signal Conn Pin Signal Conn1 GROUND 2 GROUND
3 PCLK_GP[54] 4 Y1_EMD_ENABLEn
5 TVP5146_ENABLEn 6 GROUND
7 YI3_(CCD3)_GP39] 8 YI4_(CCD4)_GP40]
9 YI2_(CCD2)_GP[38] 10 YI5_(CCD5)_GP[41]
11 TI1_(CCD1)_GP[37] 12 TI6_(CCD6_GP[42]
13 YI0_(CCD0_GP[36] 14 YI7_(CCD7)_GP[43]
15 GROUND 16 GROUND
17 C_WE_RNW_GP[35] 18 C_FIELD_EM_A[21]_GP[34]
19 VD_GP[53] 20 HD_GP[52]
21 CI3_(CDD11)_EM_A[17]_EM_D[04]_GP[47] 22 CI4_(CDD12)_EM_A[16]_EM_D[03]_GP[48]
23 CI2_(CDD10)_EM_A[18]_EM_D[05]_GP[46] 24 CI5_(CDD13)_EM_A[15]_EM_D[02]_GP[49]
25 CI1_(CDD9)_EM_A[19]_EM_D[06]_GP[45] 26 CI6_(CDD14)_EM_A[14]_EM_D[01]_GP[50]
27 CI0_(CDD8)_EM_A[20]_EM_D[07]_GP[44] 28 CI7_(CDD15)_EM_A[13]_EM_D[00]_GP[51]
29 GROUND 30 GROUND
31 VCLK_GP[31] 32 VSYNC_EM_CS4n_GP[32]
33 GROUND 34 GROUND
35 VPBECLK_GP[30] 36 HSYNC_EM_CS5n_GP[33]
37 GROUND 38 GROUND
39 YOUT3_GP[25]_BOOTMODE3 40 YOUT4_GP[26]_FASTBOOT
41 YOUT2_GP[24]_BOOTMODE2 42 YOUT5_GP[27]
43 YOUT1_GP[23]_BOOTMODE1 44 YOUT6_GP[28]
45 YOUT0_GP[22]_BOOTMODE0 46 YOUT7_GP[29]
47 GROUND 48 GROUND
49 COUT3_EM_D[3]_GP[17] 50 COUT4_EM_D[4]_GP[18]
51 COUT2_EM_D[2]_GP[16] 52 COUT5_EM_D[5]_GP[19]
53 COUT1_EM_D[1]_GP[15] 54 COUT6_EM_D[6]_GP[20]
55 COUT0_EM_D[0]_GP[14] 56 COUT7_EM_D[7]_GP[21]
57 GROUND 58 GROUND
59 B0_LCD_FIELD_EM_A[3]_GP[11] 60 R0_EM_A[4]_GP[10]_(AEAW2)
61 G1_EM_A[1]_(ALE)_GP[9]_(AEAW1) 62 B1_EMA[2]_(CLE)_GP[8]_(AEAW0)
63 R2_EM_BA[0]_GP[6]_(AEM1) 64 R1_EM_A[0]_GP[7]_(AEM2)
65 B2_EM_BA[1]_GP[6]_(AEM0) 66 G0_EM_CS2n__GP[12]
67 EM_WAIT_(RDY/BSTn) 68 LCD_OE_EM_CS3n_GP[13]
69 GROUND 70 GROUND
71 EM_A[5]_GP[96] 72 EM_A[9]_GP[92]
73 EM_A[6]_GP[95] 74 EM_A[10]_GP[91]
75 EM_A[7]_GP[94] 76 EM_A[11]_GP[90]
77 EM_A[8]_GP[93] 78 EM_A[12]_GP[89]
79 EM_WEn 80 EM_OEn
81 GROUND 82 GROUND
83 MEM_EMD7-7_ENABLEn 84 CLK_OUT_PWM2_GP[84]
85 CI_EMA_ENABLEn 86 GROUND
87 RESETn 88 GP[4]_PWM1
89 SYS_RESETn 90 I2C_INT_ENABLEn
91 VCC_1V8 92 VCC_1V8
93 GROUND 94 GROUND
95 VCC_3V3 96 VCC_3V3
97 GROUND 98 GROUND
99 VCC_5V 100 VCC_5V
Spectrum Digital, Inc
3-18 DM6437 EVM Technical Reference
3.2.22 DC_P2, Peripheral Expansion
Table 15: DC_P2, Peripheral Expansion
Pin Signal Conn Pin Signal Conn
1 GROUND 2 GROUND
3 VCC_5V 4 VCC_5V
5 VCC_3V3 6 VCC_3V3
7 VIC_TINPOL_ENABLEn 8 GROUND
9 CLKS1_TINPOL_GP[98] 10 CLKS0_TINPOL_GP[97]
11 GP[00] 12 GP[01]
13 GP[02] 14 GP[03]
15 RS232_ENABLEn 16 GROUND
17 URXD0_GP[85] 18 URTS0_PWM0_GP[88]
19 UTXD0_GP[86] 20 UCTS0_GP[87]
21 GROUND 22 GROUND
23 HECC_RX_TINP1L_URXD1_GP[56] 24 HECC_tX_TOUT1L_UTXD1_GP[55]
25 GROUND 26 CAN_ENABLEn
27 AUDIO_CLK 28 GROUND
29 AXR0[3]_FSR0_GP[102] 30 AXR0[2]_FSX0_GP[103]
31 AFSR0_DR0_GP[100] 32 AXR0[1]_DX0_GP[104]
33 AHCLKR0_CLKR0_GP[101] 34 ACLKR0_CLKX0_GP[99]
35 GROUND 36 GROUND
37 I2C_CLK 38 I2C_DATA
39 AIC33_ENABLEn 40 GROUND
41 AXR0_FSR1_GP[106] 42 AMUTEIN0_FSX1_GP[109]
43 AMUTE0_DR1_GP[110] 44 ACHLKX0_CLKR1_GP[108]
45 ACLKX0_CLKX1_GP[106] 46 AFSX0_DX1_GP[107]
47 GROUND 48 GROUND
49 RESET_OUTn 50 SPARE
51 SPARE 52 HCNTL0_MRXER_GP[76]
53 HDS1n_RXD1_GP[79] 54 HDS2n_RXD0_GP[78]
55 HINTn_RXD3_GP[82] 56 HRDYn_RXD2_GP[80]
57 GROUND 58 HD09_COL_GP[67]
59 HHWIL_RXDV_GP[74] 60 GROUND
61 HD10_CRS_GP[68] 62 HRNW_RXCLK_GP[77]
63 GROUND 64 GROUND
65 HCSnMDC_GP[81] 66 HASn_MDIO_GP[83]
67 GROUND 68 GROUND
69 HD11_TXD3_GP[69] 70 HD12_TXD2_GP[70]
71 HD13_TXD1_GP[71] 72 HD14_TXD0_GP[72]
73 HCNTL1_TXEN_GP[75] 74 ENET_ENABLEn
75 GROUND 76 GROUND
77 SPARE 78 HD15_TXCLK_GP[73]
79 GROUND 80 GROUND
81 USER_I2C_IO.A0P6 82 USER_I2C_IO.A0P7
83 SPARE 84 SPARE
85 USER_I2C_IO.A1P2 86 USER_I2C_IO.A1P3
87 USER_I2C_IO.A1P0 88 USER_I2C_IO.A1P1
89 GROUND 90 GROUND
Spectrum Digital, Inc
3-19
3.2.23 DC_P3, VLYNQ Connector
The DC_P3 connector allows the user to connect the VLYNQ interface to other logic.The pinout for the DC_P3 connector is shown in the table below.
3.3 Jumpers
The DM6437 EVM has four (4) jumpers which are used to make certain logic or featuredeterminations on the board. The function of each jumper is described in the tablebelow.
* Not populated
Table 16: DC_P3, VLYNQ Header
Pin # Signal Conn Pin # Signal Conn
1 HD00_VLYNQ_SCRUN_GP[58] 2 VLYNQ_CLOCK_GP[57]
3 GROUND 4 GROUND
5 HD01_VLYNQ_RXD0_GP[59] 6 HD05_VLYNQ_TXD0_GP[63]
7 HD02_VLYNQ_RXD1_GP[60] 8 HD06_VLYNQ_TXD1_GP[64]
9 GROUND 10 GROUND
11 VCC_3V3 12 DC_P3_VLYNQ_RESETn
13 HD03_VLYNQ_RXD2_GP[61] 14 HD07_VLYNQ_TXD2_GP[65]
15 HD04_VLYNQ_RXD3_GP[62] 16 HD08_VLYNQ_TXD3_GP[66]
17 GROUND 18 GROUND
19 VCC_5V 20 VCC_5V
Table 17: Jumpers
Jumper # Function Size
JP1 NTSC/PAL Select 1x3
JP2 CS2 Select 2x4
JP3 * Reset 1x2
JP4 * Power Up Reset 1x2
Spectrum Digital, Inc
3-20 DM6437 EVM Technical Reference
3.3.1 JP1 Jumper
Jumper JP1 is used to select the display output format, NTSC or PAL. This jumpermust be populated in one of the two configurations. When the center to NTSC isselected the display output will be NTSC format. When the center to PAL is selectedthe display output will be in PAL format. These positions are shown in the figure below.
3.3.2 JP2 Jumper
Jumper JP2 is a jumper bank used to select the routing of the CS2 signal. It can berouted to Flash ROM, SRAM, NAND Flash, and daughter card connector. Only one ofthese 1-2 selections should be made. The positions are shown in the figure below.
Boardedge
Boardedge
PAL Selection
NTSC SelectionFigure 3-18, JP1 Jumper
Figure 3-19, JP2 Jumper
CS
2-S
EL
1 2
FLASH
SRAM
NAND
DC
JP2
Spectrum Digital, Inc
3-21
3.3.3 JP3 Jumper
Jumper JP3 is a jumper used to allow external switches to interface to the DM6437power up reset signal.
3.3.4 JP4 Jumper
Jumper JP4 is a jumper used to allow external switches to interface to the DM6437reset signal.
3.4 LEDs
The DM6437 EVM has eight (8) LEDs. Four of these LEDs (DS1-4) are under user
control and addressed over the I2C bus. LED DS5 indicates the presence of +5 volts onthe board. The remaining LEDs, DS501 and DS502 indicate embedded USB status.DS502 is on when embedded USB emulation is selected and off when the externalJTAG emulator is plugged into connector J6. DS501 blinks as packets are sent to andfrom the embedded USB emulator. The LED functions are summarized in the tablebelow.
Table 18: LEDs
LED # Use Color
DS1 User Defined Green
DS2 User Defined Green
DS3 User Defined Green
DS4 User Defined Green
DS5 +5V present Red
DS501 Embedded Emulation Status Green
DS502 Embedded/external EMU Green
Spectrum Digital, Inc
3-22 DM6437 EVM Technical Reference
3.5 Switches
The DM6437 EVM has seven (7) switches. These switches are used to create certainactions on the board or to select certain functions on the board. The switch functionsare summarized in the table below.
3.5.1 SW1, Bootload Mode Select
Switch SW1 is an 8 position switch used to select the source of the bootload. Five (5) ofthe eight (8) positions are used. The selections are shown in the table below.
x = don’t care, * these boot modes must be accompanied with FASTBOOT = 1.
Table 19: Switches
SW # Function
SW1 Bootload Mode Select
SW2 DM6437 Muxing Configuration
SW3 EMIF Data Select
SW4 4 position user readable
SW5 Power On Reset
SW6 Reset
SW7 Slide Switch
Table 20: SW1, Bootload Mode Select
SW1[4:1] SW1[5] Auto Detected
BootDescription Notes DSPBOOTADDR
default
0000 x xEmulation Boot
In this mode, FASTBOOT setting is don’t care (not
used by bootloader code)
DM6437 is master 0x0010 0000
0001 1* 0 HPI Boot DM6437 is slave 0x0010 0000
0001 1* 1 PCI Boot without auto-initialization
DM6437 is slave 0x0010 0000
0010 1* 0 PCI Boot with auto-initialization
DM6437 is slave 0x0010 0000
0010 1* 1 HPI Boot DM6437 is slave 0x0010 0000
0100 0 x EMIFA ROM Direct Boot DM6437 is master 0x4200 0000
0100 1 x EMIFA ROM Fast Boot DM6437 is master 0x0010 0000
0101 x x I2C Boot DM6437 is master 0x0010 0000
0110 1* x SPI Boot (McBSP peripheral)
DM6437 is master 0x0010 0000
0111 1* x NAND Flash DM6437 is master 0x0010 0000
1000 x x UART DM6437 is master 0x0010 0000
1011 x x EMAC Boot through secondary bootloader
DM6437 is slave 0x0010 0000
Spectrum Digital, Inc
3-23
3.5.2 SW2, Bootload Configuration Select
Switch SW2 is an 4 position switch used to select the DM6437 multiplexing optionsat reset. The selection are shown in the table below.
3.5.3 SW3, EMIF Data Select
Switch SW3 is used to select between data bus pins for the asynchronous EMIFcontroller. The functions of this switch are shown in the table below.
3.5.4 SW4, 4 Position User Readable
Switch SW4 is a 4 position bank of user readable switches via the I2C expander. Theindividual switches can be placed in any position and read by the user software
from the expander. See the section on I2C expanders for more information.
3.5.5 SW5, Power On Reset Switch
Switch SW5 is a momentary switch that asserts power on reset to the DM6437 device.
3.5.6 SW6, Reset Switch
Switch SW6 is a momentary switch that asserts a reset to the DM6437 processor.
Table 21: SW2, Bootload Configuration Select
Position Function Description
1 AEM2 Specifies EMIF mode at reset
2 AEM1 Specifies EMIF mode at reset
3 AEM0 Specifies EMIF mode at reset
4 AEAW2 Specifies EMIF mode at reset
Table 22: SW3, EMDATA Select
Position Function Description
1 Not used Not Used
2 MEM_EMD7-0_SELECT 0=Selects CI0-7 as EMIF data bus D0:D7 pins1=Selects CI0-7 as COUT data bus D0:D7 pins
Spectrum Digital, Inc
3-24 DM6437 EVM Technical Reference
3.5.7 SW7, Slide Switch
Switch SW7 is a 2 position slide switch used by demonstration software. The switch is
read via a I2C expander. Refer to the I2C section for more information.
Spectrum Digital, Inc
3-25
3.6 Test Points
The EVM has 51 test points. All test points appear on the top of the board. Thefollowing figure identifies the position of each test point. the next table list each testpoint and the signal appearing on that test point.
Figure 3-20, DM6437 EVM, Test Points
TP1
TP8
TP7
TP6,TP2
TP4,TP5
TP10
TP36
TP19
TP20
TP23
TP22
TP14
TP25TP15
TP16
TP17
TP26
TP18
TP27
TP28
TP29
TP31
TP30
TP33TP37
TP32
TP34
TP12
TP48,TP49
TP38
TP46
TP43
TP47
TP58
TP41
TP70
TP59
TP21
TP42
TP64
TP69
TP40
TP13
Spectrum Digital, Inc
3-26 DM6437 EVM Technical Reference
Table 23: DM6437 EVM Test Points
Test Point #
SignalTest Point
#Signal
TP1 RESETOUTn TP27 GND
TP2 RSV4 TP28 GND
TP6 RSV5 TP29 GND
TP7 GND TP30 GND
TP8 GND TP31 VCC_5V
TP10 GND TP32 3V3_PWR_OK
TP12 Ethernet PHY Interrupt Pin TP36 1V8_PWR_OK
TP13 CAN Driver Output B_CANH TP40 DM6437 I2CCLK
TP14 CAN Driver Output B_CANL TP41 DM6437 I2CDATA
TP15 Codec MFP2 Pin TP52 VDD_1P1V
TP16 Codec MPF3 Pin TP53 VDD_1P1V
TP17 Codec GPIO1 Pin TP58 VIDEO DECODER GLCO/I2C Pin
TP18 Codec GPIO2 Pin TP59 VIC INPUT CLOCK
TP19 VIDEO DECODER AVID/GPIO Pin TP61 DM6437 HECC_RX
TP20 VIDEO DECODER INTREQ Pin TP64 DM6437 HECC_TX
TP21 CORE_PWR_OK TP69 DM6437 PWM1
TP25 GND TP70 DM6437CLK_OUT
TP26 GND
Table 24: Power Pair Test Points
Power PairsInput1 Input2
Power DomainResistance Between
Inputs
TP4 TP5 DDR_VDDL 0.1 ohms
TP22 TP23 DSP_CORE_VDD 0.025 ohms
TP33 TP34 VCC_3V3 0.025 ohms
TP37 TP38 VCC_1V8 0.025 ohms
TP42 TP43 DVD_3V3 0.025 ohms
TP47 TP46 DVDD_1V8 0.025 ohms
TP48 TP49 PLLPWR18 0.1 ohms
TP52 TP53 VDDA_1P1V 0.1 ohms
TP54 TP55 VDDA_1P8V 0.1 ohms
A-1
Appendix A
Schematics
This appendix contains the schematics for the DM6437 EVM.
Spectrum Digital, Inc
A-2 DM6437 EVM Technical Reference
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Siz
e:
Da
te:
DW
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OR
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Sh
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TIT
LE
SH
EE
T
SHEET01 - TITLE
SHEET02 - BLOCK DIAGRAM
SHEET03 - DSP CLKS/RST/EMU
SHEET04 - EMULATION
SHEET05 - DSP
Serial/CAN/I2C
SHEET06 - DSP VP/EMIF/PCI/ENET
SHEET07 - DSP DDR Interface
SHEET08 - DSP DACS/GND-pins
SHEET09 - DSP Power Pins
SHEET10 - Boot DIP Switches
SHEET11 - VIC
SHEET12 - I2C Expanders
SHEET13 - I2C Expanders 2
SHEET14 - DDR2 Memories
SHEET15 - EMIF Muxing
SHEET16 - NAND-Flash/SRAM
SHEET17 - NOR-Flash/EEPROM
SHEET18 - ENET Muxing
SHEET19 - ENET
SHEET20 - CAN
SHEET21 - RS232
SHEET22 - PCI-Mux
SHEET23 - PCI-Mux II
SHEET24 - PCI-Connector
SHEET25 - VLYNQ
SHEET26 - AIC33
SHEET27 - SPDIF/TVP5146-Switch
SHEET28 - TVP5146
SHEET29 - Video Out
SHEET30 - VIDEO DC Conn.
SHEET31 - EMAC/MCBSP DC Conn.
SHEET32 - VLYNQ/EMIF DC Conn.
SHEET33 - RESET SUPERVISOR
SHEET34 - POWER
SCHEMATIC CONTENTS
REV
ENGR
2REVISION STATUS OF SHEETS
111
SH
DATE
14
12
13
DATE
ENGR-MGR
MFG
7
DWN
DATE
8
DATE
10
SH
DATE
CHK
RLSE
APPLICATION
REV
35
NEXT ASSY
DATE
6
DATE
9
QA
USED ON
4
15
AA
AA
A
AC
CA
R.R.P.
T.W.K.
R.R.P.
R.R.P.
C.M.D.
R.R.P.
R.R.P.
06/01/2006
06/01/2006
16
17
18
19
20
21
22
23
24
25
06/01/2006
06/01/2006
06/01/2006
06/01/2006
06/01/2006
REV
SH
AC
BC
AA
A
AA
26
27
28
29
30
AB
31
32
A
CAB
A
CA
A
AA
A
A
33
34
BB
I2C
Address Table
00111000B
USER INPUT Expander - 0111(A2)(A1)(A0)
PCF8574
00111001B
PCF8574
ADDRESS BINARY
DEVICE
FUNCTION
LED Expander - 0111(A2)(A1)(A0)
00111010B
00111011B
PCF8574
PCF8574
VLYNQ IO Expander - 0111(A2)(A1)(A0)
VIC PLL Expander - 0111(A2)(A1)(A0)
01010000B
00011011B
01011101B
EEPROM - 1010(A2)(A1)(A0)
AUDIO CODEC - 00110(MFP1)(MFP0)
AIC33
VIDEO DECODER - 101110(I2CA)
TVP5146
HEX
CAT24C256
0x38
0x39
0x3A
0x3B
0x50
0x1B
0x5D
Spectrum Digital, Inc
A-3
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Siz
e:
Da
te:
DW
G N
OR
evi
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n:
Sh
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of
Titl
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Pa
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Co
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nts
:
A
SP
EC
TR
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DIG
ITA
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CO
RP
OR
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ED
5091
02-0
001
Wed
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sda
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06
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62
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BL
OC
K D
IAG
RA
M
I2C Expanders
Video In
DC Connector
I2C EEPROM
Video Switch
Video Decoder
EMIF Switch
NAND/NOR/SRAM
Boot DIP Switches
Video Out
DC Connector
ENET Switches
ENET XCVR
EMAC
DC Connector
PCI Switches/Mux
PCI Edge Conn
I2C
CCDC/EMIF/
McASP1/PCI
EMIF-Ctrl
EMIF-Addr/PCI
VENC/EMIF
UHPI/PCI/EMAC
GIO/PCI
PWM1
Timer0
McBSP1/MCASP0
Timer1/HECC/
UART1
UART0/PWM0
DACs
DDR2 IF
PLL
Emulator
VLYNQ/PCI/
UHPI
PCI AD
VIC
S/PDIF Out
Audio Switch
Stereo Codec
McBSP
DC Connector
CAN Switch
CAN XCVR
UART Switches
RS-232 XCVR
Video Out
Connectors
DDR2 SDRAM
Crystal/Osc
EMU Header
VLYNQ
mPCI Connector
VLYNQ
DC Connector
McBSP0/McASP0
SPI EEPROM
Socket
DSP
Power Supplies
Reset Logic
MISC
DC Connector
Embedded
EMU
EMU Muxes
Spectrum Digital, Inc
A-4 DM6437 EVM Technical Reference
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
VC
C_
3V
3
VC
C_1
V8
PC
IEN
23
RE
SE
T_O
UT
n2
2,3
1
SY
S_
RE
SE
Tn
17
,19
,26
,28
,30,
33
RE
SE
Tn
4,2
2,3
0
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Da
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:
C
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DIG
ITA
L I
NC
OR
PO
RA
TE
D
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02-0
001
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De
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ber
06
, 2
00
63
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OPTIONAL OSCILLATOR POPULATION
CRYSTAL AND CAPS REMOVED WHEN
OSCILLATOR IS USED
ASFL3-27.000MHZ-EK-T
102229-0027
Y1
27M
Hz
C1
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Spectrum Digital, Inc
A-5
5 5
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3 3
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Siz
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Sh
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of
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Co
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DIG
ITA
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OR
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ED
5091
02-0
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Wed
nesd
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43
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S32
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15
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Spectrum Digital, Inc
A-6 DM6437 EVM Technical Reference
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
PW
M1
_I2
C_I
NT
VC
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111
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023
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223
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123
CLK
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17
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31
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Siz
e:
Da
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DW
G N
OR
evi
sio
n:
Sh
eet
of
Titl
e:
Pa
ge
Co
nte
nts
:
A
SP
EC
TR
UM
DIG
ITA
L IN
CO
RP
OR
AT
ED
5091
02-0
001
Wed
nesd
ay, D
ecem
ber 0
6, 2
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53
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TM
S32
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valu
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M6
437
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_CLK
M2
CLK
S1/
TIN
P0L
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[98]
K2
AC
LKR
0/C
LKX
0/G
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9]H
1
CLK
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TO
UT
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UT
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09]
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GP
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SR
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4
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06]
F1
AH
CLK
R0/
CLK
R0/
GP
[101
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AH
CLK
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CLK
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GP
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1
AX
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GP
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3
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33
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31
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Spectrum Digital, Inc
A-7
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
YI0
YI1
YI3
YI5
YI7
YI2
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16
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L23
CR
S23
TXD
323
TXD
223
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123
TX
CLK
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D0
23
RX
CLK
23
RX
D3
23
RX
D2
23
RX
D1
23
RX
D0
23
RX
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23
TX
EN
23
RX
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23
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23
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10
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10
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10
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E2
10
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10
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26
22
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28
22
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22
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27,3
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NC
30
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22
CI6
22
CI5
22
CI4
22
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CI2
22
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22
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15
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5,3
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15
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YI7
27
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YI6
27
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YI5
27
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YI4
27
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YI3
27
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YI2
27
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YI1
27
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YI0
27
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C_
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0
EM
_A
09
22
EM
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06
22
EM
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05
22
EM
_A
07
22
EM
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08
22
EM
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11
22
EM
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10
22
EM
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12
22
PT
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23
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BE
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K22
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BS
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16
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ITE
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6,1
7,3
0 VID
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LK11
CLK
_OU
T5
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VP
BE
CL
K30
Siz
e:
Da
te:
DW
G N
OR
evi
sio
n:
Sh
eet
of
Titl
e:
Pa
ge
Co
nte
nts
:
A
SP
EC
TR
UM
DIG
ITA
L I
NC
OR
PO
RA
TE
D
5091
02-0
001
Wed
nesd
ay, D
ecem
ber 0
6, 2
006
634
B
TM
S3
20D
M64
37 E
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DS
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P/E
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8
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20/G
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8
EM
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22/G
P[9
4]C
9
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21/G
P[9
3]B
9
EM
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SE
L/G
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2]D
9
EM
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0]/A
D23
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[91]
A9
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1]/A
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C10
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2]/P
CB
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GP
[89]
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19
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M_A
[15]
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11
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15
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P[1
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P[1
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CO
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B13
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C13
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(CC
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[40]
D14
YI3
(CC
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[39]
B14
YI2
(CC
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[38]
C14
YI1
(CC
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B15
YI0
(CC
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C15
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_A[1
9]/P
RE
Qn/
EM
_D[6
]/GP
[45]
B12
CI0
(CC
D8)
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0]/P
INT
An/
EM
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]/GP
[44]
C12
CO
UT
2/E
M_D
[2]/G
P[1
6]D
17C
OU
T1/
EM
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]/GP
[15]
D18
CO
UT
0/E
M_D
[0]/G
P[1
4]D
16
HD
0/V
LYN
Q_S
CR
UN
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18/G
P[5
8]C
8
HD
1/V
LYN
Q_R
XD
0/A
D16
/GP
[59]
D7
HD
2/V
LYN
Q_R
XD
1/A
D17
/GP
[60]
A8
HD
3/V
LYN
Q_R
XD
2/P
CB
E2n
/GP
[61]
B7
HD
4/V
LYN
Q_R
XD
3/P
FR
AM
En/
GP
[62]
C7
HD
5/V
LYN
Q_T
XD
0/P
IRD
Yn/
GP
[63]
A6
HD
6/V
LYN
Q_T
XD
1/P
TR
DY
n/G
P[6
4]D
6
HD
7/V
LYN
Q_T
XD
2/P
DE
VS
ELn
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[65]
B6
HD
8/V
LYN
Q_T
XD
3/P
PE
RR
n/G
P[6
6]A
5
HD
9/M
CO
L/P
ST
OP
n/G
P[7
]C
6
HD
10/M
CR
S/P
SE
RR
n/G
P[6
8]B
5
HD
11/M
TX
D3/
PC
BE
1/G
P[6
9]C
5
HD
12/M
TX
D2/
PP
AR
/GP
[70]
D5
HD
13/M
TX
D1/
AD
14/G
P[7
1]B
4
HD
14/M
TX
D0/
AD
15/G
P[7
2]D
4
HD
15/M
TX
CLK
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12/G
P[7
3]A
4
HR
DY
n/M
RX
D2/
PC
BE
0/G
P[8
0]D
2
HC
NT
L0/M
RX
ER
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10/G
P[7
6]B
3
HC
NT
L1/M
TX
EN
/AD
11/G
P[7
5]D
3
HA
Sn/
MD
IO/A
D3/
GP
[83]
D1
HC
Sn/
MD
CLK
/AD
5/G
P[8
1]C
1
HD
S1n
/MR
XD
1/A
D7/
GP
[79]
B2
HD
S2n
/MR
XD
0/A
D9/
GP
[78]
C3
HH
WIL
/MR
XD
V/A
D13
/GP
[74]
C4
HIN
Tn/
MR
XD
3/A
D6/
GP
[82]
C2
HR
NW
/MR
XC
LK/A
D8/
GP
[77]
A3
VP
BE
CLK
/GP
[30]
G19
YO
UT
7/G
P[2
9]H
15
YO
UT
6/G
P[2
8]H
16
YO
UT
5/G
P[2
7]H
17
YO
UT
4/G
P[2
6]/(
FA
ST
BO
OT
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17
YO
UT
3/G
P[2
5]/(
BO
OT
MO
DE
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16
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UT
2/G
P[2
4]/(
BO
OT
MO
DE
2)G
15
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UT
1/G
P[2
3]/(
BO
OT
MO
DE
1)F
15
YO
UT
0/G
P[2
2]/(
BO
OT
MO
DE
0)F
18
VLY
NQ
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CK
/PC
ICLK
/GP
[57]
A7
AD
26E
10
AD
28E
11
AD
30E
12
C_W
E/R
NW
/GP
[35]
D13
R1
84
0R
N1
4D
RP
AC
K8-
22
A4
B13
R1
66
20K
RN
14F
RP
AC
K8
-22
A6
B11
RN
14
AR
PA
CK
8-2
2A
1B
16
R3
13
0
R2
722
R1
68
NO
-PO
P
RN
1R
PA
CK
8-22
123456789 10 11 12 13 14 15 16
R1
83
NO
-PO
P
Spectrum Digital, Inc
A-8 DM6437 EVM Technical Reference
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
BD
DR
_A
1B
DD
R_
A2
BD
DR
_A
0
BD
DR
_A
3B
DD
R_
A4
BD
DR
_A
5B
DD
R_
A6
BD
DR
_A
7B
DD
R_
A8
BD
DR
_A
9B
DD
R_A
10
BD
DR
_A1
1B
DD
R_A
12
DD
R_
A0
DD
R_
A1
DD
R_
A2
DD
R_
A3
DD
R_
A4
DD
R_
A5
DD
R_
A6
DD
R_
A7
DD
R_
A8
DD
R_
A9
DD
R_A
10
DD
R_A
11
BD
DR
_B
S0
2B
DD
R_
BS
01
BD
DR
_B
S0
0D
DR
_A1
2D
DR
_BS
00
DD
R_B
S0
1D
DR
_BS
02
DD
R_
CA
S
DD
R_
WE
DD
R_
RA
SB
DD
R_
CA
S
BD
DR
_W
EB
DD
R_
RA
S
BD
DR
_CL
K_
ND
DR
_C
LK
_N
BD
DR
_CLK
DD
R_
CL
K
DD
R_
CK
EB
DD
R_
CK
E
BD
DR
_C
SD
DR
_C
S
BD
DR
_D
QM
0B
DD
R_
DQ
M1
BD
DR
_D
QM
2B
DD
R_
DQ
M3
DD
R_
DQ
S0
DD
R_
DQ
S1
DD
R_
DQ
S2
DD
R_
DQ
S3
DD
R_
PA
DR
EF
ND
DR
_P
AD
RE
FP
VR
EF
_ST
L
DD
R_
D6
DD
R_
D8
DD
R_
D1
2
DD
R_
D1
4
DD
R_
D2
0
DD
R_
D1
6
DD
R_
D1
9
DD
R_
D2
1D
DR
_D
22
DD
R_
D2
3
DD
R_
D1
7
DD
R_
D2
5D
DR
_D
26
DD
R_
D2
8
DD
R_
D3
1
DD
R_
D2
7
DD
R_
D2
9
DD
R_
D0
DD
R_
D1
DD
R_
D2
DD
R_
D3
DD
R_
D4
DD
R_
D5
DD
R_
D7
DD
R_
D9
DD
R_
D1
0D
DR
_D
11
DD
R_
D1
3
DD
R_
D1
5
DD
R_
D1
8
DD
R_
D2
4
DD
R_
D3
0
DD
R_
DQ
M0
DD
R_
DQ
M1
DD
R_
DQ
M2
DD
R_
DQ
M3
VC
C_1
V8
VC
C_
1V8
DD
R_
A[0
:12
]14
DD
R_
BS
02
14D
DR
_B
S0
114
DD
R_
BS
00
14
DD
R_
WE
14
DD
R_
CA
S14
DD
R_
RA
S14
DD
R_
CL
K_
N14
DD
R_
CL
K14
DD
R_
CK
E14
DD
R_
CS
14
DD
R_
DQ
M0
14
DD
R_
DQ
M3
14
DD
R_
DQ
M1
14
DD
R_
DQ
M2
14
DD
R_
DQ
S2
14D
DR
_D
QS
314
DD
R_
DQ
S1
14D
DR
_D
QS
014
DD
R_
D[0
:31
]14
VR
EF
_ST
L14
Siz
e:
Da
te:
DW
G N
OR
evi
sio
n:
Sh
eet
of
Titl
e:
Pa
ge
Co
nte
nts
:
A
SP
EC
TR
UM
DIG
ITA
L IN
CO
RP
OR
AT
ED
5091
02-0
001
Wed
ne
sda
y, D
ece
mb
er
06
, 2
00
67
34
B
TM
S32
0DM
64
37 E
valu
atio
n M
odul
e
DS
P D
DR
In
terf
ace
Designers must use routing techniques from
DDR2 PCB
Layout Application Note
RN
10
RP
AC
K4
-22
12345 6 7 8
RN
9R
PA
CK
4-2
2
12345 6 7 8
TP
8T
P-6
0
R8
522
R7
61
K 1
%
C9 0.1
uF
R7
71
K 1
%
C8
0.1
uF
L3 BL
M21
PG
221
SN
1D1
2
R3
220
0
TP
4T
P-3
0
R29
22
TP
10T
P-6
0
C5
0.1
uF
C1
01
uF
TP
5T
P-3
0
RN
8R
PA
CK
4-2
2
12345 6 7 8
R30
10
R8
422
TP
9T
P-6
0
TP
7T
P-6
0
R8
622
TP
6T
P-3
0
R31
10
RN
7R
PA
CK
4-2
2
12345 6 7 8
R3
40R
33
200
R3
50
.00
X
R8
722
C1
11
0.1
uF
U1C
DM
6437
DD
R_A
[0]
W13
DD
R_Z
NT
10
DD
R_D
[0]
T1
DD
R_D
QS
[0]
U4
DD
R_D
QM
[0]
T4
DD
R_C
Sn
T9
DD
R_C
LK0n
W8
DD
R_C
LK0
W7
DD
R_C
KE
V8
DD
R_C
AS
nT
7
DD
R_B
S[0
]U
8
RS
V5
R13
DD
R_A
[1]
U13
DD
R_A
[2]
V13
DD
R_A
[3]
U12
DD
R_A
[4]
V12
DD
R_A
[5]
W12
DD
R_A
[6]
W11
DD
R_A
[7]
V11
DD
R_A
[8]
V10
DD
R_A
[9]
U11
DD
R_A
[10]
U10
DD
R_A
[11]
W10
DD
R_A
[12]
W9
DD
R_B
S[1
]V
9
DD
R_B
S[2
]U
9
DD
R_D
QM
[1]
T6
DD
R_D
QM
[2]
T14
DD
R_D
QM
[3]
T16
DD
R_D
QS
[1]
U6
DD
R_D
QS
[2]
U14
DD
R_D
QS
[3]
U16
DD
R_Z
PT
11
DD
R_R
AS
nU
7
DD
R_W
En
T8
DD
R_D
[1]
T2
DD
R_D
[2]
U1
DD
R_D
[3]
U2
DD
R_D
[4]
V2
DD
R_D
[5]
U3
DD
R_D
[6]
V3
DD
R_D
[7]
W3
DD
R_D
[8]
V4
DD
R_D
[9]
W4
DD
R_D
[10]
U5
DD
R_D
[11]
V5
DD
R_D
[12]
W5
DD
R_D
[13]
V6
DD
R_D
[14]
W6
DD
R_D
[15]
V7
DD
R_D
[16]
W14
DD
R_D
[17]
V14
DD
R_D
[18]
W15
DD
R_D
[19]
V15
DD
R_D
[20]
U15
DD
R_D
[21]
W16
DD
R_D
[22]
V16
DD
R_D
[23]
T17
DD
R_D
[24]
V17
DD
R_D
[25]
U17
DD
R_D
[26]
T18
DD
R_D
[27]
W17
DD
R_D
[28]
U18
DD
R_D
[29]
V18
DD
R_D
[30]
U19
DD
R_D
[31]
T19
DD
R_V
DD
DLL
T12
DD
R_V
SS
DLL
T13
DD
R_V
RE
FT
15
RN
11
RP
AC
K4
-22
12345 6 7 8
Spectrum Digital, Inc
A-9
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
VR
EF
_0.5
V
VC
C_
1V
8
DS
P_
CO
RE
_V
DD
VC
C_
3V3
DA
C_
IOU
T_B
29
DA
C_
IOU
T_A
29
DA
C_I
OU
T_
D29
DA
C_I
OU
T_
C29
DA
C_
RB
IAS
29
Siz
e:
Da
te:
DW
G N
OR
evi
sio
n:
Sh
eet
of
Titl
e:
Pa
ge
Co
nte
nts
:
A
SP
EC
TR
UM
DIG
ITA
L IN
CO
RP
OR
AT
ED
5091
02-0
001
Wed
ne
sda
y, D
ece
mb
er
06
, 2
00
68
34
B
TM
S32
0DM
64
37 E
valu
atio
n M
odul
e
DS
P D
AC
S/G
ND
-pin
s
VREF =1.24 VOLTS
R3
77
.5K
1%
C1
8.0
01u
F
TP
54T
P-3
0
R3
220
.1
C1
4.0
01u
F
L4
BLM
21P
G2
21S
N1D
12
U4
TLV
431
AD
BV
53
421
C1
7.1
uF
R4
1N
O-P
OP
+C
15
10u
F
U1D
DM
6437
DA
C_I
OU
T_A
P19
DA
C_I
OU
T_B
P18
DA
C_I
OU
T_C
N18
DA
C_I
OU
T_D
N17
DA
C_V
RE
FN
19
DA
C_R
BIA
SN
16
VS
SA
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1VP
15
VS
SA
_1P
8VP
16
VD
DA
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1VN
15
VD
DA
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8VP
17
R3
80
C1
1.1
uF
TP
52T
P-3
0
C1
3.1
uF
U1H
DM
6437
Vss
.1A
19
Vss
.2B
1
Vss
.3B
19
Vss
.6E
9
Vss
.4E
13
Vss
.5E
7
Vss
.8F
12
Vss
.9F
14
Vss
.10
F4
Vss
.11
F6
Vss
.12
F8
Vss
.13
G11
Vss
.14
G13
Vss
.15
G18
Vss
.16
G5
Vss
.18
G9
Vss
.19
H10
Vss
.20
H12
Vss
.21
H14
Vss
.22
H19
Vss
.23
H6
Vss
.24
H8
Vss
.25
J11
Vss
.26
J13
Vss
.27
J15
Vss
.28
J17
Vss
.29
J18
Vss
.30
J5
Vss
.31
J7
Vss
.32
J9
Vss
.33
K1
Vss
.34
K10
Vss
.37
K16
Vss
.38
K6
Vss
.39
K8
Vss
.40
L11
Vss
.41
L13
Vss
.42
L17
Vss
.43
L19
Vss
.44
L7
Vss
.45
L9
Vss
.46
M10
Vss
.47
M12
Vss
.48
M14
Vss
.49
M16
Vss
.50
M17
Vss
.51
M18
Vss
.52
M19
Vss
.53
M6
Vss
.35
K12
Vss
.36
K14
Vss
.7F
10
Vss
.17
G7
Vss
.54
M8
Vss
.55
N11
Vss
.56
N13
Vss
.57
N14
Vss
.58
N5
Vss
.59
N7
Vss
.60
N9
Vss
.61
P10
Vss
.62
P12
Vss
.63
P14
Vss
.64
P6
Vss
.65
P8
Vss
.66
R1
Vss
.67
R11
Vss
.68
R15
Vss
.69
R17
Vss
.70
R18
Vss
.71
R19
Vss
.72
R5
Vss
.73
R7
Vss
.74
R9
Vss
.75
V19
Vss
.76
W1
Vss
.77
W2
R39
4.9
9K
1%
C1
21
uF R3
230
.1TP
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P-3
0
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10u
F
TP
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P-3
0
R3
6 1K
L5
BLM
21P
G2
21S
N1D
12
Spectrum Digital, Inc
A-10 DM6437 EVM Technical Reference
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
DV
DD
_3V
3
DV
DD
_1
V8
DV
DD
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V3
CV
DD
_C
OR
E
CV
DD
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OR
E
CV
DD
_C
OR
E
DV
DD
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V3
DV
DD
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8
DS
P_
CO
RE
_V
DD
VC
C_
3V
3
VC
C_
1V
8
VC
C_
1V
8
Siz
e:
Da
te:
DW
G N
OR
evi
sio
n:
Sh
eet
of
Titl
e:
Pa
ge
Co
nte
nts
:
A
SP
EC
TR
UM
DIG
ITA
L IN
CO
RP
OR
AT
ED
5091
02-0
001
Wed
ne
sda
y, D
ece
mb
er
06
, 2
00
69
34
B
TM
S32
0DM
64
37 E
valu
atio
n M
odul
e
DS
P P
ow
er P
ins
Place
near DDR side of package
POWER TEST POINT AT THE REGULATOR FOR 1.2 V
TP
49T
P-3
0
U1
BD
M6
437
DV
DD
R2.
1L1
4
MX
VD
DL1
8
DV
DD
R2.
2P
11
DV
DD
R2.
3P
13
DV
DD
R2.
4P
5
DV
DD
R2.
5P
7
DV
DD
R2.
6P
9
DV
DD
R2.
7R
10
DV
DD
R2.
8R
12
DV
DD
R2.
9R
14
DV
DD
R2.
10R
16
DV
DD
R2.
11R
4
DV
DD
R2.
12R
6
DV
DD
R2.
13R
8
DV
DD
R2.
14T
5
DV
DD
R2.
15V
1
DV
DD
R2.
16W
18
DV
DD
R2.
17W
19
C3
3
0.1
uF
C70
0.1
uF
U1J
DM
643
7
DV
dd33
.2A
18D
Vdd
33.1
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A-18 DM6437 EVM Technical Reference
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A-20 DM6437 EVM Technical Reference
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Spectrum Digital, Inc
A-22 DM6437 EVM Technical Reference
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A-24 DM6437 EVM Technical Reference
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6B1
43
7B1
41
8B1
39
10B
134
2B2
51
3B2
48
4B2
46
5B2
44
6B2
42
7B2
40
8B2
37
11B
231
12B
229
NC
.922
NC
.10
24
NC
.11
26
NC
.12
28
11B
132
12B
130
9B2
35
10B
233
C1
76
0.1
uF
R3
15
0
R33
40
C1
74
0.1
uF
U3
9S
N7
4A
HC
1G
14D
CK
RG
4
3
4
5
2 1
R33
62
2
C1
21
0.1
uF
Spectrum Digital, Inc
A-25
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
PC
I_P
_A
D0
PC
I_P
_A
D2
PC
I_P
_A
D4
PC
I_P
_A
D6
PC
I_P
_AD
11P
CI_
P_A
D13
PC
I_P
_AD
15
PC
I_P
_AD
16P
CI_
P_A
D18
PC
I_P
_AD
20P
CI_
P_A
D22
PC
I_P
_AD
24
PC
I_P
_AD
26P
CI_
P_A
D28
PC
I_P
_AD
30P
CI_
P_
AD
31P
CI_
P_
AD
29
PC
I_P
_A
D27
PC
I_P
_A
D25
PC
I_P
_A
D23
PC
I_P
_A
D21
PC
I_P
_A
D19
PC
I_P
_A
D17
PC
I_P
_A
D14
PC
I_P
_A
D12
PC
I_P
_A
D10
PC
I_P
_AD
8P
CI_
P_A
D7
PC
I_P
_AD
5P
CI_
P_A
D3
PC
I_P
_AD
1
PC
I_P
_A
D9
VC
C_
5V
PC
IVC
C_3
V3
PC
IVC
C_
3V
3
VC
C_
5V
PC
I_V
IO
PC
I_V
IO
VC
C_5
V
VC
C_3
V3
PC
I_V
IO
PC
IVC
C_
3V
3
PC
I_P
_A
D[3
1:0
]2
2,2
3
PC
I_P
_R
ST
n22
PC
I_P
_G
NT
n22
PC
I_P
_ID
SE
L22
PC
I_P
_F
RA
ME
n22
PC
I_P
_T
RD
Yn
23
PC
I_P
_S
TO
Pn
23
PC
I_P
_PA
R23
PC
I_P
_C
/BE
n0
23
PC
I_P
_C
/BE
n1
23
PC
I_P
_C
/BE
n3
22
PC
I_P
_C
/BE
n2
22
PC
I_P
_S
ER
Rn
23P
CI_
P_
PE
RR
n23
PC
I_P
_D
EV
SE
Ln
23
PC
I_P
_IR
DY
n22
PC
I_P
_R
EQ
n22
PC
I_P
_C
LK
22
PC
I_P
_P
INT
An
22
PC
I_P
LU
Gn
23
Siz
e:
Da
te:
DW
G N
OR
evi
sio
n:
Sh
eet
of
Titl
e:
Pa
ge
Co
nte
nts
:
A
SP
EC
TR
UM
DIG
ITA
L IN
CO
RP
OR
AT
ED
5091
02-0
001
Wed
ne
sda
y, D
ece
mb
er
06
, 2
00
624
34
B
TM
S32
0DM
64
37 E
valu
atio
n M
odul
e
PC
I-C
on
ne
cto
r
PCI_VIO
A10,A16,A59
B19,B59
A10,A16,B19
A59,B59
Length to Cap no greater that 0.25 inches
Any number of pin shares as long as does not exceed length
Trace size to cap 20 mil
B25,B31,B36,B41,B43,B54
A21,A27,A33,A39,A45,A53
A53,B54
PCIVCC_3V3
A21,A27,B25,B31
A33,A39,B41,B43
Length to Cap no greater that 0.25 inches
Any number of pin shares as long as does not exceed length
Trace size to cap 20 mil
Length to Cap no greater that 0.25 inches
Any number of pin shares as long as does not exceed length
Trace size to cap 20 mil
R1
6310
K
C1
820
.1uF
C2
03
0.1
uF
C1
800
.1u
F
R1
64N
O-P
OP
R1
780
R1
800
C1
81
0.1
uF
C17
20
.1u
F
P4
PC
I C
on
nec
tor
TR
ST
A1
+12V
A2
TM
SA
3
TD
IA
4
+5V
A5
INT
AA
6
INT
CA
7
+5V
A8
Rsv
d.0
A9
+V I/
OA
10
Rsv
d.1
A11
Key
.1K
ey.2
3.3V
aux
A14
RS
TA
15
+V I/
OA
16
GN
TA
17
GN
DA
18
PM
EA
19
AD
30A
20
+3.3
VA
21
AD
28A
22
AD
26A
23
GN
DA
24
AD
24A
25
IDS
EL
A26
+3.3
VA
27
AD
22A
28
AD
20A
29
GN
DA
30
AD
18A
31
AD
16A
32
+3.3
VA
33
FR
AM
EA
34
GN
DA
35
TR
DY
A36
GN
DA
37
ST
OP
A38
+3.3
VA
39
SD
ON
EA
40
SB
OA
41
GN
DA
42
PA
RA
43
AD
15A
44
+3.3
VA
45
AD
13A
46
AD
11A
47
GN
DA
48
AD
9A
49
Key
.3K
ey.4
C/B
E0
A52
+3.3
VA
53
AD
6A
54
AD
4A
55
GN
DA
56
AD
2A
57
AD
0A
58
+V I/
OA
59
RE
Q64
A60
+5V
A61
+5V
A62
-12V
B1
TC
KB
2
GN
DB
3
TD
OB
4
+5V
B5
+5V
B6
INT
BB
7
INT
DB
8
PR
SN
T1
B9
Rsv
d.2
B10
PR
SN
T2
B11
Key
.5K
ey.6
Rsv
d.3
B14
GN
DB
15
CLK
B16
GN
DB
17
RE
QB
18
+V I/
OB
19
AD
31B
20
AD
29B
21
GN
DB
22
AD
27B
23
AD
25B
24
+3.3
VB
25
C/B
E3
B26
AD
23B
27
GN
DB
28
AD
21B
29
AD
19B
30
+3.3
VB
31
AD
17B
32
C/B
E2
B33
GN
DB
34
IRD
YB
35
+3.3
VB
36
DE
VS
EL
B37
GN
DB
38
LOC
KB
39
PE
RR
B40
+3.3
VB
41
SE
RR
B42
+3.3
VB
43
C/B
E1
B44
AD
14B
45
GN
DB
46
AD
12B
47
AD
10B
48
M66
EN
B49
Key
.7K
ey.8
AD
8B
52
AD
7B
53
+3.3
VB
54
AD
5B
55
AD
3B
56
GN
DB
57
AD
1B
58
+V I/
OB
59
AC
K64
B60
+5V
B61
+5V
B62
+
C20
4
33u
F
R1
790
C1
79
0.1
uF
Spectrum Digital, Inc
A-26 DM6437 EVM Technical Reference
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
WLA
N_
RS
Tn
VC
C_
1V
8
VC
C_
3V
3V
CC
_5
V
VC
C_1
V8
VC
C_
3V
3V
CC
_3
V3
VL
YN
Q_
CL
OC
K22
,32
VL
YN
Q_
RX
D0
22,
32
VL
YN
Q_
RX
D1
22,
32
VLY
NQ
_TX
D0
22
,32
VL
YN
Q_
SC
RU
N2
2,3
2
VLY
NQ
_TX
D1
23
,32
VLY
NQ
_R
ES
ET
12
,32
VL
YN
Q_
RX
D2
22
,32
VL
YN
Q_
RX
D3
22
,32
VLY
NQ
_T
XD
22
3,32
VLY
NQ
_T
XD
32
3,32
Siz
e:
Da
te:
DW
G N
OR
evi
sio
n:
Sh
eet
of
Titl
e:
Pa
ge
Co
nte
nts
:
C
SP
EC
TR
UM
DIG
ITA
L IN
CO
RP
OR
AT
ED
5091
02-0
001
Wed
ne
sda
y, D
ece
mb
er
06
, 2
00
625
34
B
TM
S32
0DM
64
37 E
valu
atio
n M
odul
e
BT
H_
WL
AN
_C
ON
NE
CT
OR
Check the layout library regarding pins 125-128.
SILKSCREEN: MINI PCI
C3
73
47
0pF
C3
72
22
uF
C3
86
0.3
3uF
C3
92
0.3
3u
F
C3
74
0.3
3u
F
C4
05
47
0pF
C3
81
0.3
3uF
C3
82
47
0pF
U6
7S
N7
4L
VC
1G
06D
BV
RG
4
3
4
5
2 1
C3
76
47
0pF
C3
94
47
0pF
C3
75
22
uF
C3
83
0.3
3u
F
C3
77
0.3
3u
F
C1
71
0.1
uF
C3
79
47
0pF
C3
84
4.7
uF
C3
78
22
uF
mPCI_Host_WLAN_CONNECTOR
Debug Signals(Do not connect in the host)
Power Supplies
VLYNQSDIO
VLYNQ2
BTHUART
BTHPCM
BTHCTLs
WLANCTLs
Check your
Layout Lib
J20 m
PC
I_H
OS
T_
WL
AN
_C
ON
NE
CT
OR
VB
AT
1
D1_
5V2
SLP
_CLK
_EN
3
WLA
N_E
LP_R
EQ
4
PM
_EN
5
WLA
N_/
INT
R6
OS
C32
_768
KH
z7
JTA
G_W
LAN
_TD
O8
GN
D_9
9
JTA
G_W
LAN
_TR
ST
N10
JTA
G_W
LAN
_TD
I11
JTA
G_W
LAN
_TM
S12
JTA
G_W
LAN
_TC
K13
GN
D_1
414
RE
SE
RV
ED
_15
15
WLA
N_V
LYN
Q_C
LK/S
DIO
_CLK
16
DB
G_J
TA
G_W
LAN
_3V
17T
o_H
ost_
VLY
NQ
_SD
IO_V
IO18
D3_
3V_1
919
GN
D_2
020
WLA
N_V
LYN
Q_T
D0/
SD
IO_C
MD
21
WLA
N_V
LYN
Q_T
D1/
SD
IO_D
322
GN
D_2
323
WLA
N_V
LYN
Q_S
CR
UN
/SD
IO_D
024
GN
D_2
525
WLA
N_/
RE
SE
T26
GN
D_2
727
D3_
3V_2
828
1.8V
_BT
H_/
SH
UT
DW
N29
1.8V
_BT
H_/
INT
R30
D3_
3V_3
131
GN
D_3
232
GN
D_3
333
GN
D_3
434
GN
D_3
535
WLA
N_V
LYN
Q_R
D0/
SD
IO_D
236
GN
D_3
737
1.8V
_BT
H_E
LP_W
KU
P38
DB
G_G
PIO
_3V
39
D3_
3V_4
040
GN
D_4
141
GN
D_4
242
WLA
N_V
LYN
Q_R
D1/
SD
IO_D
143
GN
D_4
444
GN
D_4
545
GN
D_4
646
BT
_RF
_SD
47
GN
D_4
848
BT
_FR
EQ
49
GN
D_5
050
BT
_PR
I_D
AT
A51
GN
D_5
252
BT
_PA
_ON
_OR
_RX
53
GN
D_5
454
RE
SE
RV
ED
_55
55
GN
D_5
656
RE
SE
RV
ED
_57
57
GN
D_5
858
WLA
N_V
LYN
Q_T
D2
59
GN
D_6
060
WLA
N_V
LYN
Q_T
D3
61
GN
D_6
262
D3_
3V_6
363
GN
D_6
464
WLA
N_V
LYN
Q_R
D2
65
GN
D_6
666
WLA
N_V
LYN
Q_R
D3
67
GN
D_6
868
GN
D_6
969
D3_
3V_7
070
1.8V
_BT
H_P
CM
_CLK
71
GN
D_7
272
1.8V
_BT
H_P
CM
_FS
73
GN
D_7
474
1.8V
_BT
H_P
CM
_TX
D75
GN
D_7
676
1.8V
_BT
H_P
CM
_RX
D77
GN
D_7
878
GN
D_7
979
WLA
N_V
LYN
Q2_
TD
280
GN
D_8
181
WLA
N_V
LYN
Q2_
TD
382
GN
D_8
383
WLA
N_V
LYN
Q2_
RD
284
GN
D_8
585
WLA
N_V
LYN
Q2_
RD
386
GN
D_8
787
D3_
3V_8
888
D3_
3V_8
989
GN
D_9
090
GN
D_9
191
GN
D_9
292
WLA
N_V
LYN
Q2_
CLK
93
GN
D_9
494
GN
D_9
595
GN
D_9
696
5V_9
797
WLA
N_V
LYN
Q2_
TX
D0
98
GN
D_9
999
WLA
N_V
LYN
Q2_
TX
D1
100
GN
D_1
0110
1
GN
D_1
0210
2
5V_1
0310
3
1.8V
_BT
H_U
AR
T_T
XD
104
DB
G_E
E_W
P10
5
DB
G_I
2C_S
DA
106
DB
G_I
2C_S
CL
107
DB
G_I
2C_S
A2
108
1.8V
_BT
H_U
AR
T_R
XD
109
GN
D_1
1011
0
D1_
8V11
1
WLA
N_V
LYN
Q2_
RX
D0
112
1.8V
_BT
H_U
AR
T_R
TS
113
GN
D_1
1411
4
VIO
XIO
_3V
115
1.8V
_BT
H_U
AR
T_C
TS
116
WLA
N_R
S23
2_T
XD
117
WLA
N_R
S23
2_R
XD
118
GN
D_1
1911
9
WLA
N_U
AR
T_T
XD
120
WLA
N_V
LYN
Q2_
RX
D1
121
WLA
N_U
AR
T_R
XD
122
DB
G_R
S23
2_3V
123
WLA
N_V
LYN
Q2_
SC
RU
N12
4
HO
LE1
125
HO
LE2
126
GN
D_P
AD
112
7
GN
D_P
AD
212
8
R41
91K
C3
80
47
0pF
R3
94
NO
-PO
P
C3
93
47
0pF
C3
85
0.3
3u
F
C3
71
0.3
3u
F
Spectrum Digital, Inc
A-27
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
B_C
LK
X1_
AC
LK
X0
B_
CL
KR
1_
AC
LKR
0B
_FS
X1_
AF
SX
0
B_
FS
R1
_A
FS
R0
B_D
X1
_AX
R0[
0]B
_D
R1
_A
XR
0[1]
VC
C_
3V
3
VC
C_
3V
3
VC
C_
3V3
GN
D_A
ICG
ND
_AIC
GN
D_A
ICG
ND
_AIC
GN
D_A
IC
GN
D_A
IC
GN
D_A
IC
GN
D_A
IC
GN
D_A
IC
GN
D_A
ICG
ND
_AIC
GN
D_A
IC
GN
D_A
IC
GN
D_A
IC
GN
D_A
IC
GN
D_A
IC
VC
C_
3V
3
GN
D_A
IC
GN
D_A
IC
VC
C_
1V
8
VC
C_
3V
3
VC
C_
3V
3V
CC
_3V
3
SY
S_R
ES
ET
n3
,17,
19
,28
,30
,33
I2C
_D
AT
A5
,12
,13
,17
,28
,31
I2C
_C
LK
5,1
2,1
3,1
7,2
8,3
1
AU
DIO
_C
LK
11,
31
CLK
X1
5,3
1C
LK
R1
5,3
1F
SX
15
,31
DR
15
,31
ALT
_AIC
33_
CLK
DX
15
,31
DX
05,
17
,31
CLK
X0
5,1
7,3
1
SP
DIF
_O
UT
27
DR
05
,17
,31
FS
R1
5,3
1
McA
SP
_ON
n13
SP
DIF
_O
Nn
13
McB
SP
_ON
n13
SP
DIF
_O
Nn
13
McA
SP
_ON
n13
McB
SP
_ON
n13
Siz
e:
Da
te:
DW
G N
OR
evi
sio
n:
Sh
eet
of
Titl
e:
Pa
ge
Co
nte
nts
:
C
SP
EC
TR
UM
DIG
ITA
L I
NC
OR
PO
RA
TE
D
5091
02-0
001
We
dn
esd
ay,
De
cem
ber
06
, 2
00
626
34
B
TM
S3
20D
M64
37 E
valu
atio
n M
odul
e
AIC
33
Isolate analog and
digital GNDs at single
location in the ground
plane
DR0 <--> AFSR0
DX0 <--> AXR0[1]
CLKX0 <--> ACLKR0
CLKX1 <--> ACLKX0
FSR1 <--> AXR0[0]
DX1 <--> AFSX0
R3
56
33
C20
7
0.1
uF
R2
07N
O-P
OP
C2
39
220
pF
R1
990
R2
01
0K
R1
965
.6K
C2
250
.1uF
R2
16
10
+C
230
10
uF
C2
29
0.1
uF
L16
BLM
41P
750
SP
T
R1
945
.6K
C2
20
0.1
uF
C2
41
0.1
uF
R1
95
5.6
K
L23
BLM
21P
G2
21S
N1D
R2
023
30
C2
23
0.1
uF
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02-0
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y, D
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06
, 2
00
628
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TM
S32
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64
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valu
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A-30 DM6437 EVM Technical Reference
5 5
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OR
evi
sio
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Sh
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Pa
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Co
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nts
:
A
SP
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TR
UM
DIG
ITA
L IN
CO
RP
OR
AT
ED
5091
02-0
001
Wed
ne
sda
y, D
ece
mb
er
06
, 2
00
629
34
B
TM
S32
0DM
64
37 E
valu
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n M
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Vid
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ISOLATE GROUNDS
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AB
LE5
RS
ET
3
P1
749
181-
1
34 2
1
56
L46
1u
H
+C
29
41
0u
F
C3
04
10p
F
C3
08
10
pF
C29
30
.01
uF
Spectrum Digital, Inc
A-31
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
YI0
_(C
CD
0)_
GP
[36
]
YI4
_(C
CD
4)_
GP
[40]
YI1
_(C
CD
1)_
GP
[37
]Y
I2_
(CC
D2)
_G
P[3
8]
YI3
_(C
CD
3)_
GP
[39
]
YI7
_(C
CD
7)_
GP
[43]
C_
FIE
LD
_E
M_
A[2
1]_
GP
[34
]
CI4
_(C
CD
12)_
EM
_A[1
6]_
EM
_D
[3]_
GP
[48
]
CI6
_(C
CD
14)_
EM
_A[1
4]_
EM
_D
[1]_
GP
[50
]C
I5_
(CC
D13
)_E
M_A
[15
]_E
M_
D[2
]_G
P[4
9]
CI7
_(C
CD
15)_
EM
_A[1
3]_
EM
_D
[0]_
GP
[51
]C
I0_
(CC
D8
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M_
A[2
0]_
EM
_D
[07]
_GP
[44
]C
I1_
(CC
D9
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M_
A[1
9]_
EM
_D
[06]
_GP
[45
]C
I2_
(CC
D1
0)_
EM
_A
[18
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M_
D[0
5]_
GP
[46]
CI3
_(C
CD
11
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M_
A[1
7]_
EM
_D
[04
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P[4
7]
PC
LK
_G
P[5
4]
RE
SE
RV
ED
SY
S_
RE
SE
Tn
TV
P5
146_
EN
AB
LEn
C_
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NW
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5]
VD
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3]
HD
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P[5
2]
VC
LK
_G
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1]
HS
YN
C_
EM
_C
S5
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P[3
3]
VS
YN
C_
EM
_C
S4
n_
GP
[32
]
GP
[4]_
PW
M1
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T_
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AB
LE
n
CL
K_O
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4]
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SE
Tn
CI_
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A_E
NA
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En
ME
M_
EM
D7
-0_E
NA
BLE
n
EM
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11_G
P[9
0]
EM
_A
[12
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P[8
9]
EM
_A
[9]_
GP
[92]
EM
_A
[10
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P[9
1]
EM
_OE
n
EM
_A
[5]_
GP
[96]
EM
_A
[6]_
GP
[95]
EM
_A
[7]_
GP
[94]
EM
_A
[8]_
GP
[93]
EM
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n
LCD
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GP
[13]
G0
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[12]
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LE)_
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2)
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P[6
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1)
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[28
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[29
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5)_
GP
[41]
YI6
_(C
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GP
[42]
CO
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GP
[16]
CO
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[17]
VC
C_
5V
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C_
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3
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C_
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C_
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3
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C_
1V
8V
CC
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27
YI0
6,2
7
YI4
6,2
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YI6
6,2
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YI1
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YI3
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YI7
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I01
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15
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B.C
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15
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L_P
CLK
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SE
Tn
3,1
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9,2
6,2
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3
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P51
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NA
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5,6
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SE
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3,4
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EM
D7
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BLE
n15
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M_A
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16
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16
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101
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6,1
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16
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M_
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16
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7
EM
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17
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6,1
0,1
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7
EM
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6,1
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7
LC
D_O
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DC
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15W
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6,1
6
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06
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16
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6,1
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6,1
6,1
7
CO
UT
06
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CO
UT
16
,15
CO
UT
26
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CO
UT
36
,15
YO
UT
2_B
OO
TM
OD
E2
6,1
0Y
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T1
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OT
MO
DE
16
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UT
0_B
OO
TM
OD
E0
6,1
0
YO
UT
3_B
OO
TM
OD
E3
6,1
0
VP
BE
CLK
6
CO
UT
66
,15
CO
UT
56
,15
CO
UT
46
,15
CO
UT
76
,15
YO
UT
66
,10
YO
UT
4_F
AS
TB
OO
T6
,10
YO
UT
56
,10
YO
UT
76
CI_
EM
A_E
NA
BL
En
15
Siz
e:
Da
te:
DW
G N
OR
evi
sio
n:
Sh
eet
of
Titl
e:
Pa
ge
Co
nte
nts
:
A
SP
EC
TR
UM
DIG
ITA
L IN
CO
RP
OR
AT
ED
5091
02-0
001
Wed
ne
sda
y, D
ece
mb
er
06
, 2
00
630
34
B
TM
S32
0DM
64
37 E
valu
atio
n M
odul
e
VID
EO
DC
Co
nn
.
R2
65
NO
-PO
P
DC
_P
1
CO
NN
EC
TO
R 5
0 X
2
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
2121
2222
2323
2424
2525
2626
2727
2828
2929
3030
3131
3232
3333
3434
3535
3636
3737
3838
3939
4040
4141
4242
4343
4444
4545
4646
4747
4848
4949
5050
5151
5252
5353
5454
5555
5656
5757
5858
5959
6060
6161
6262
6363
6464
6565
6666
6767
6868
6969
7070
7171
7272
7373
7474
7575
7676
7777
7878
7979
8080
9090
8888
8686
8484
8282
8181
8383
8585
8787
8989
9292
9494
9696
9898
100
100
9191
9393
9595
9797
9999
Spectrum Digital, Inc
A-32 DM6437 EVM Technical Reference
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
HD
15_
TX
CL
K_G
P[7
3]
HD
14_
TX
D0
_G
P[7
2]
HD
12_
TX
D2
_G
P[7
0]
HD
11_
TX
D3
_GP
[69]
HA
Sn
_M
DIO
_G
P[8
3]
HC
Sn
_M
DC
_G
P[8
1]
HD
S2
n_
RX
D0
_GP
[78
]H
RD
Yn
_R
XD
2_
GP
[80
]H
DS
1n
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D1_
GP
[79
]H
INT
n_R
XD
3_G
P[8
2]
HC
NT
L0_
MR
XE
R_G
P[7
6]
AC
LK
X0
_CL
KX
1_G
P[1
06]
AM
UT
E0
_D
R1_
GP
[11
0]A
XR
0_
FS
R1
_G
P[1
06]
AF
SX
0_D
X1_
GP
[107
]A
HC
LK
X0_
CLK
R1_
GP
[108
]A
MU
TE
IN0
_FS
X1
_GP
[10
9]
AF
SR
0_
DR
0_
GP
[100
]A
HC
LK
R0
_C
LKR
0_G
P[1
01]
AU
DIO
_C
LK
AU
DIO
_CL
KA
XR
0[3
]_F
SR
0_G
P[1
02]
AX
R0[
1]_
DX
0_G
P[1
04]
AC
LK
R0_
CLK
X0_
GP
[99]
AX
R0[
2]_
FS
X0_
GP
[10
3]
UR
XD
0_
GP
[85]
UT
XD
0_G
P[8
6]U
CT
S0
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P[8
7]U
RT
S0
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WM
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P[8
8]
B.G
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B.G
P[0
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B.G
P[0
3]B
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[01]
HR
NW
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XC
LK
_G
P[7
7]H
HW
IL_
RX
DV
_G
P[7
4]
HD
10_
CR
S_
GP
[68
]
HD
09
_C
OL_
GP
[67]
HE
CC
_T
X_
TO
UT
1L_U
TX
D1_
GP
[55]
HE
CC
_R
X_
TIN
P1
L_U
RX
D1
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[56
]
CL
KS
1_
TIN
P0
L_G
P[9
8]
AIC
33_
EN
AB
LEn
CA
N_
EN
AB
LEn
RS
232
_EN
AB
LEn
VIC
_T
INP
0L_
EN
AB
LEn
EN
ET
_E
NA
BLE
n
CLK
S0
_TO
UT
0L_
GP
[97]
RE
SE
T_O
UT
n
I2C
_C
LK
I2C
_D
AT
A
US
ER
_I2
C_
IO.A
1P
0U
SE
R_
I2C
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R_
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C_
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6U
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R_
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P7
HD
13_
TX
D1
_GP
[71]
HC
NT
L1_
TX
EN
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P[7
5]
VC
C_
5V
VC
C_
3V
3
VC
C_
5V
VC
C_
3V
3
B.T
XC
LK
18
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B.T
XD
11
8,23
B.T
XD
01
8,2
3B
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D2
18
,23
B.T
XD
31
8,23
B.M
DIO
18
,23
B.M
DC
18,
23
B.R
XD
01
8,2
3B
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D2
18
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B.R
XD
31
8,23
B.R
XD
11
8,23
B.R
XE
R1
8,23
CL
KX
15
,26
DR
15
,26
FS
R1
5,2
6
DX
15
,26
CL
KR
15
,26
FS
X1
5,2
6
DR
05
,17
,26
CL
KR
05
AU
DIO
_C
LK
11,
26
FS
R0
5D
X0
5,1
7,2
6F
SX
05
,17
CLK
X0
5,1
7,2
6
UT
XD
05
,21
UR
XD
05
,21
UC
TS
05
UR
TS
05
B.G
P[0
0]23
B.G
P[0
2]23
B.G
P[0
3]
23
B.G
P[0
1]
23
B.T
XE
N1
8,23
B.R
XC
LK
18,
23B
.RX
DV
18,
23B
.CR
S1
8,23
B.C
OL
18
,23
TO
UT
1L5
,20
,21
TIN
P1L
5,2
0,2
1
TO
UT
0L
5T
INP
0L5
,11
AIC
33_
EN
AB
LE
n13
CA
N_
EN
AB
LE
n20
RS
232
_EN
AB
LEn
21
VIC
_T
INP
0L_
EN
AB
LEn
11
EN
ET
_E
NA
BL
En
18
RE
SE
T_
OU
Tn
3,2
2
I2C
_C
LK
5,1
2,1
3,1
7,2
6,2
8I2
C_D
AT
A5
,12
,13
,17
,26
,28
US
ER
_I2
C_
IO.A
1P
013
US
ER
_I2
C_
IO.A
1P
113
US
ER
_I2
C_
IO.A
1P
213
US
ER
_I2
C_
IO.A
1P
313
US
ER
_I2
C_
IO.A
0P
712
US
ER
_I2
C_
IO.A
0P
612
Siz
e:
Da
te:
DW
G N
OR
evi
sio
n:
Sh
eet
of
Titl
e:
Pa
ge
Co
nte
nts
:
A
SP
EC
TR
UM
DIG
ITA
L I
NC
OR
PO
RA
TE
D
5091
02-0
001
We
dn
esd
ay,
De
cem
be
r 0
6,
20
0631
34
B
TM
S32
0D
M6
437
Eva
luat
ion
Mo
dule
EM
AC
/MC
BS
P D
C C
onn
.
DC
_P
2
CO
NN
EC
TO
R 4
5 X
2 11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
2121
2222
2323
2424
2525
2626
2727
2828
2929
3030
3131
3232
3333
3434
3535
3636
3737
3838
3939
4040
4141
4242
4343
4444
4545
4646
4747
4848
4949
5050
5151
5252
5353
5454
5555
5656
5757
5858
5959
6060
6161
6262
6363
6464
6565
6666
6767
6868
6969
7070
7171
7272
7373
7474
7575
7676
7777
7878
7979
8080
9090
8888
8686
8484
8282
8181
8383
8585
8787
8989
R2
70
NO
-PO
P
Spectrum Digital, Inc
A-33
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
HD
06
_V
LY
NQ
_T
XD
1_G
P[6
4]H
D0
5_
VL
YN
Q_
TX
D0_
GP
[63]
VL
YN
Q_
CL
OC
K_
GP
[57
]H
D0
0_
VL
YN
Q_
SC
RU
N_
GP
[58
]
HD
01
_V
LY
NQ
_R
XD
0_
GP
[59
]H
D0
2_
VL
YN
Q_
RX
D1
_G
P[6
0]
HD
03
_V
LY
NQ
_R
XD
2_
GP
[61
]H
D0
4_
VL
YN
Q_
RX
D3
_G
P[6
2]
HD
07
_V
LY
NQ
_T
XD
2_G
P[6
5]H
D0
8_
VL
YN
Q_
TX
D3_
GP
[66]
VC
C_
3V
3
VC
C_5
VV
CC
_5
V
VC
C_
1V
8V
CC
_3
V3
VC
C_
3V
3
VL
YN
Q_
TX
D1
23
,25
VL
YN
Q_
SC
RU
N2
2,2
5
VL
YN
Q_
RX
D0
22
,25
VL
YN
Q_
RX
D1
22
,25
VL
YN
Q_
TX
D0
22
,25
VL
YN
Q_
CL
OC
K2
2,2
5
VL
YN
Q_
RX
D2
22
,25
VL
YN
Q_
RX
D3
22
,25
VL
YN
Q_
TX
D2
23
,25
VL
YN
Q_
TX
D3
23
,25
VL
YN
Q_
RE
SE
T1
2,2
5
Siz
e:
Da
te:
DW
G N
OR
evi
sio
n:
Sh
eet
of
Titl
e:
Pa
ge
Co
nte
nts
:
A
SP
EC
TR
UM
DIG
ITA
L IN
CO
RP
OR
AT
ED
5091
02-0
001
Wed
ne
sda
y, D
ece
mb
er
06
, 2
00
632
34
B
TM
S32
0DM
64
37 E
valu
atio
n M
odul
e
VL
YN
Q/E
MIF
DC
Co
nn
.
C1
77
0.1
uF
U1
5 SN
74
LV
C1G
06D
BV
RG
4
3
4
5
2 1
R2
67
NO
-PO
P
DC
_P
3
HE
AD
ER
10X
2
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20
R2
66
1K
Spectrum Digital, Inc
A-34 DM6437 EVM Technical Reference
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
DS
P_
CO
RE
_V
DD
VC
C_
5V
VC
C_
5V
AG
ND
DS
P_
CO
RE
_VD
D
VC
C_
3V
3V
CC
_3V
3
VC
C_
3V
3
VC
C_
3V
3
VC
C_
3V
3
VC
C_
1V
8V
CC
_3
V3
VC
C_
3V
3
VC
C_
3V3
SY
S_
RE
SE
Tn
3,1
7,1
9,2
6,2
8,3
0
CO
RE
_P
WR
_OK
34
CO
RE
_V
DD
_S
EL
EC
T13
1V
8_P
WR
_OK
34 3V
3_
PW
R_O
K34
EM
U_S
YS
_R
ES
ET
n
Siz
e:
Da
te:
DW
G N
OR
evi
sio
n:
Sh
eet
of
Titl
e:
Pa
ge
Co
nte
nts
:
B
SP
EC
TR
UM
DIG
ITA
L IN
CO
RP
OR
AT
ED
5091
02-0
001
Wed
ne
sda
y, D
ece
mb
er
06
, 2
00
633
34
B
TM
S32
0DM
64
37 E
valu
atio
n M
odul
e
RE
SE
T S
UP
ER
VIS
OR
3.3 sq in AGND,
min
thermal pad
Connect
at pin
1
GNDTest Points
ResetThrehold 0.84 Volts
ResetThrehold 0.84 Volts
ResetThrehold 0.84 Volts
nPOR
CORE_VDD_SELECT function:
0: 1.05V
1: 1.2V
The FET and resistor in series with it can be
removed if voltage scaling is not desired.
ResetThrehold 0.84 Volts
C3
31
NO
-PO
P
R2
75
71
.5K
1%
U5
6
TP
S3
808
G0
9DB
VR
G4
RE
SE
T1
GN
D2
MR
3
CT
4
SE
NS
E1
5V
DD
6
R28
31
0K 1
%
C3
28
0.1
uF
U5
8
TP
S3
808
G0
9DB
VR
G4
RE
SE
T1
GN
D2
MR
3
CT
4
SE
NS
E1
5V
DD
6
TP
25T
P-6
0
R3
44
NO
-PO
P
+C
32
3
10
0uF
4V
C3
15
0.0
39
uF
R2
890
SW
5
PU
SH
BU
TT
ON
SW
AA
AB
BB
L49
BLM
41P
750S
PT
C31
65
60p
F
TP
26
TP
-60
R2
76
1.6
5K
1%
C3
14
0.1
uF
U5
7
TP
S3
808
G0
9DB
VR
G4
RE
SE
T1
GN
D2
MR
3
CT
4
SE
NS
E1
5V
DD
6
R2
720
C3
27
NO
-PO
P
+C
32
5
10
0 u
F
TP
30T
P-6
0
R2
82
9.0
9K
1%
R2
79
10
K 0
.1%
R3
14
0
TP
28T
P-6
0
C3
17
33
00pF
C3
130
.01
uF
C3
68
1u
F
R29
01
0K 1
%
C3
12
NO
-PO
P
R2
85
20
K 1
%
C3
30
0.1
uF
R2
800
.025
L50
2.7
uH
C3
26
0.1
uF
JP
4
HE
AD
ER
2 N
O-P
OP
1 2
R2
74
56
.0K
1%
R28
810
K
D1
0
BA
S16
-7-F
13
R3
46
33
R27
71
07
1%
C3
19
NO
-PO
P
TP
23T
P-6
0
C3
24
100
0pF
C31
8
0.0
47u
F
R2
73
56.0
K 1
%
TP
27T
P-6
0R
287
10K
1%
TP
21T
P-3
0
C3
22
0.1
uF
R3
4510
K
+C
321
10
uF
LE
SR
TP
29T
P-6
0
R2
811K
R2
8410
K
R2
78
10K
R3
490
TP
22
TP
-60
S
D
G
Q4
BS
S12
3
C3
29
NO
-PO
P
C3
20
0.1
uF
U5
5
TP
S54
310P
WP
101
338-
0001
AG
ND
1
VS
EN
SE
2
CO
MP
3
PW
RG
D4
BO
OT
5
PH
16
PH
27
PH
38
PH
49
PH
510
PG
ND
111
PG
ND
212
PG
ND
313
VIN
114
VIN
215
VIN
316
VB
IAS
17S
S/E
NA
18S
YN
C19
RT
20P
OW
ER
PA
D21
Spectrum Digital, Inc
A-35
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
1V
8_P
WR
_O
K
1V
8_P
WR
_O
K
3V3
_PW
R_
OK
3V
3_P
WR
_OK
AG
ND
VC
C_
3V3
VC
C_
5V
VC
C_
5V
VC
C_
5V
AG
ND
VC
C_
1V
8
VC
C_
5V
CO
RE
_P
WR
_O
K33
CO
RE
_PW
R_
OK
33
3V3
_P
WR
_OK
33
1V
8_P
WR
_OK
33
Siz
e:
Da
te:
DW
G N
OR
evi
sio
n:
Sh
eet
of
Titl
e:
Pa
ge
Co
nte
nts
:
B
SP
EC
TR
UM
DIG
ITA
L IN
CO
RP
OR
AT
ED
5091
02-0
001
Wed
ne
sda
y, D
ece
mb
er
06
, 2
00
634
34
B
TM
S32
0DM
64
37 E
valu
atio
n M
odul
e
PO
WE
R
3.3 sq in AGND,
min
thermal pad
Connect
at pin
1
Sets
Voltage
3.3V @1.5Amp Max
2.5
MM
JA
CK
3.3 sq in AGND,
min
thermal pad
Connect
at pin
1
Sets
Voltage
SILKSCREEN:
5V IN
C34
8
0.1
uF
C3
3633
00p
F
R3
001
0.2
K 1
%
+C
35
9
100
uF
R2
913
.74
K 1
%
+C
357
100
uF
4V
TP
36T
P-3
0
C3
52
0.0
47
uF
C3
58
100
0p
FT
P37
TP
-60
1
C3
540
.1u
F
R3
022
K 1
%
C3
354
70
pF
R2
94
71
.5K
1%
C35
133
00p
F
R3
05
10K
1%
R2
99
220 R
43
8
NO
-PO
P
R3
01
71
.5K
1%
C3
478
200p
FC3
328
200p
FR
293
2K
1%
C3
44
1000
pF
+C
340
47u
F
TP
38T
P-6
0
R3
93
NO
-PO
P
R2
971
0K 1
%
C3
34
0.03
9u
F
DS
5
GR
EE
N
C3
56
0.1
uF
C3
33
0.1
uF
U6
0
TP
S54
310
PW
P1
013
38-0
001
AG
ND
1
VS
EN
SE
2
CO
MP
3
PW
RG
D4
BO
OT
5
PH
16
PH
27
PH
38
PH
49
PH
510
PG
ND
111
PG
ND
212
PG
ND
313
VIN
114
VIN
215
VIN
316
VB
IAS
17S
S/E
NA
18S
YN
C19
RT
20P
OW
ER
PA
D21
R2
95
10K
C3
504
70p
F
TP
32T
P-3
0R
296
10
7 1%
R4
39
0
C3
53
NO
-PO
P+
C3
55
10
uF L
ES
R
L51
BLM
41P
750
SP
T
+C
346
10
0 u
F
+C
34
3
100
uF
4V
TP
33T
P-6
0
+C
34
2
10u
F L
ES
R
C3
39
0.1
uF
R2
92
NO
-PO
P
C3
41
0.1
uF
L52
3.3
uH
R3
060
.025
R3
031
07
1%
+C
34
5
10
0 u
F 4
V
C3
37
0.0
47
uF
TP
31T
P-3
0
L53
BLM
41P
750
SP
T
C3
49
0.0
39u
F
TP
34
TP
-60
L54
2.7
uH
J16
RA
SM
712
SLE
EV
ES
HU
NT
CE
NT
ER
U5
9
TP
S5
4310
PW
P10
1338
-000
1
AG
ND
1
VS
EN
SE
2
CO
MP
3
PW
RG
D4
BO
OT
5
PH
16
PH
27
PH
38
PH
49
PH
510
PG
ND
111
PG
ND
212
PG
ND
313
VIN
114
VIN
215
VIN
316
VB
IAS
17S
S/E
NA
18S
YN
C19
RT
20P
OW
ER
PA
D21
C3
38
NO
-PO
PR
29
80
.025
R3
04
10K
Spectrum Digital, Inc
A-36 DM6437 EVM Technical Reference
B-1
Appendix B
Mechanical Information
This appendix contains the mechanical information about the DM6437EVM produced by Spectrum Digital.
Spectrum Digital, Inc
B-2 DM6437 EVM Technical Reference
TH
IS D
RA
WIN
G IS
NO
T T
O S
CA
LE
Printed in U.S.A., December 2006509105-0001 Rev C