Tin Whisker Phenomenon, Mitigation And Testing Overview V2

Tin WhiskersP tiPropertiesRisk FactorsMitigationMitigationIndustry PerspectiveJEDEC Test RequirementsJEDEC Test Requirements

- Patrick Neymany

OutlineTi Whi k F d t l•Tin Whiskers Fundamentals

•Physical & Electrical Properties•Growth and Accelerated Growth Factors•Growth and Accelerated Growth Factors•Risk Factors•Mitigationt gat o

- Conformal Coating Update

•The Role of Intermetallics•Industry Perspective

- Consumer, Telecom, Automotive- Supplier and Customer

•JEDEC Testing Requirements•Test Flow: Ni-Underplated devices with 4/less leads

Information is Patrick Neyman Confidential & ProprietaryDo Not Reproduce or Distribute - Patrick Neyman

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•Reference List

Tin Whiskers Basics

•Tin Whiskers are single-crystal Sn filaments that extrude from the Sn surface via grain boundary diffusion

•Grain boundary diffusion occurs due to compressive stresses at tin grain boundaries

•Tin whiskering is a stress relief mechanism

Tin Whisker mitigation techniques•Tin Whisker mitigation techniquesare stress relief mechanisms


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Tin Whisker Examples

Whisker with striations Whisker with ringsg

Smooth Whisker with a consistent cross section.


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Physical and Electrical Properties

•Diameter: ~1 – 5 microns

•Length: up to ~1 mm•Length: up to 1 mm

•Fusing Current: ~5 mA

•Linear Resistance: 0.5 Ohm/micron (f 2 i di t )(for 2 micron diameter)

•~700 G required to break off from surface G fbreak-off from surface note: Gold plating required for electrical contact

Oxide difficult to breach with whisker(7 G force required to breach oxide)


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Typical Time to WhiskeringiNEMI h d t i d h t i l ti t hi k i f i h idit• iNEMI has determined rough typical time to whiskering for various humidity & temperature conditions

• Matte Tin over Copper, 150 °C anneal – NO UNDERPLATE• No Corrosion on measured regions• No Corrosion on measured regions

Temperature Humidity Tin Thickness Time to Whisker

85 °C 85% RH 3 micron ~ 2000 hours85 C 85% RH 3 micron ~ 2000 hours10 micron ~ 2000 hours

60 °C 87% RH 3 micron ~ 2000 – 4500 hours10 micron ~ 4500 – 7000 hours

60 °C 60% RH 3 micron ~ 7000 – 10,000 hours10 micron ~ 7000 – 10,000 hours

30 °C 90% RH 3 micron ~ 11,000 hours45 °C 60% RH 10 micron ~ 10 000 hours


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45 C 60% RH 10 micron 10,000 hours


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Tin Whisker Risk Factors

•Mechanical Processing•Compressive stress at bending and singulation points

•Intermetallic Formation•Cu6Sn5 volume is greater than 6Cu+5Sn•Compressive stress forms at the Cu6Sn5 – Sn interface

•Surface Oxidation•SnO burrows into the Sn layer during oxidationSnO volume is greater than Sn + O•SnO volume is greater than Sn + O

•CTE Mismatch (Coefficient of Thermal Expansion)•Compressive stress at solder fillet / device interfaceCompressive stress at solder fillet / device interface.

•Plating Conditions•Organic Contamination (internal compressive stresses)


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Tin Whisker Mitigation TechniquesPlating Conditions•Plating Conditions

•!!! No other techniques work if this is not right !!!•Eliminate / reduce organics,...

M tt Ti ( f )•Matte Tin (if no Ni underplate: min 7 micron, 10 nominal. With Ni: thinner is better)•Larger grains result in larger free volume (void volume)•Free volume allows short-range stress relief

U d l t ith Ni k l•Underplate with Nickel (min 0.5 micron, 1.27 recommended)

•Ni protects Sn from Cu•Ni3Sn4 intermetallic forms tensile stress regions

•Relieves compressive stress from oxides or damage on thin (<<10 μm) Sn•Anneal @ 150 C for 1 hr within 24 hrs of plating

•Stress relaxation•Fuse in hot oil above Tmelt(Sn) within 24 hrs of plating (time varies)

•Sn flows to fill in voids and cool to non-stressed state•Alloy with Lead


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•Telecom and Automotive current (JUN07) method of choice

Conformal Coating NOT a mitigatorNo coatings yet found to mitigate whisker growth• No coatings yet found to mitigate whisker growth

• Conformal coatings CAN protect against intrusion by whiskers from neighboring components


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Tin Whiskers & Intermetallics•Intermetallic Formation•Cu6Sn5 takes up more volume than 6Cu+5Sn•Compressive stress forms at the Cu6Sn5 – Sn interface

Sn Deposit

Cu6Sn5

Sn DepositSn Deposit

Cu6Sn5Cu6Sn5

Cu SubstrateCu SubstrateCu Substrate


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Tin Whiskers & Intermetallics•Occasionally, a whisker extrudes

•The extrusion die is the path of least resistancepath of least resistance


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Tin Whisker Formation

Questions ???


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•Reference List

Telecom / Automotive (AEC Jun07)Sn Pb components preferred by most• Sn-Pb components preferred by most– Pb-free being forced by suppliers and customers

• Long-term reliability concern• Long-term reliability concern– Uncertain if Whisker Growth is Limited / Unlimited

• 3% Sn-Pb requirement being pushed by some3% Sn Pb requirement being pushed by some

• Whisker-Risk labeling on Pb-free parts under debate

• Majority going with JEDEC for testing requirements• Majority going with JEDEC for testing requirements– Telecom pushing for new Class 2A

• Periodic recertification may be droppedPeriodic recertification may be dropped

• Ambient conditions storage may be dropped

Sn Pb component price increasing significantlInformation is Patrick Neyman Confidential & ProprietaryDo Not Reproduce or Distribute - Patrick Neyman

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• Sn-Pb component price increasing significantly

Consumer Electronics (IPC, Dec06)

– Tin Whiskers viewed as small source of problems

– Largest Pb-Free concern is solder-joint reliability

– OEM manufacturers concerned as devices grow smaller

– Old plating techniques now known to be a problem

Cleanliness an issue for many (smaller?) shops– Cleanliness an issue for many (smaller?) shops

– Confusion in general about best methods


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Industry Perspective - SuppliersJ i t Fi diJoint Findings:

Philips, Infineon, STMicroelectronics, Freescale Semiconductor

• Reflow Mitigates Tin WhiskeringReflow Mitigates Tin Whiskering – matches RCP initial findings

• Plating improvement efforts ceased / very limitedJEDEC: any change to bath requires re testing– JEDEC: any change to bath requires re-testing

• JEDEC inspection procedures seen as impractical• Corrosion is found to be a significant cause of whiskering in practical use, but is a JEDEC exemption

• Preconditioning does not cause increased whiskering,but adds 66% workloadbut adds 66% workload

• Grandfathered parts fail JESD201 testing– Surface finishes with long field history of reliability exempt


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Industry Perspective - CustomersJ i t Fi diJoint Findings:

Philips, Infineon, STMicroelectronics, Freescale Semiconductor

• Very Few customers request Tin Whisker reportVery Few customers request Tin Whisker report– Mostly, no more questions after report submitted

• Some customers ADD demands to JESD201Some concern about JEDEC exception for terminations• Some concern about JEDEC exception for terminations covered in solder during assembly

• Customers are accepting the grandfather clause on long-p g g gestablished tin surface finish processes.

– from JESD201 Section 6 (Acceptance Criteria): “data on long established tin surface finish manufacturing processes withdata on long established tin surface finish manufacturing processes with reliable field histories can be substituted with agreement between supplier and user”.

– BUT, many of these components fail JESD201 testing


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•Reference List

JEDEC Testing Requirements

• Temp Cycle:– +85 C Tmax, -55/-40 C Tmin, 5-10 min soak, ~3 cyc/hr

Whi k t i ll f ft 500 l– Whiskers typically form after 500 cycles

• High Temp/Hum Conditions:60 C / 87% RH for 4000 hours– 60 C / 87% RH for 4000 hours

– Whiskers typically form after 1000-2000 hours

• Room Conditions:Room Conditions:– 30 C / 60% RH for 4000 hours– AEC and iNEMI driving to eliminate this condition from JEDEC

• Calibration Standard and Equipment Certification required


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Sample Requirements for 2-LeadsFi l t d d t L d R fl d• Final as-mounted product. Loose and Reflowed– For parts without top-bottom symmetry: 3 total pre-conditions

• Minimum 3 plating lots, at least one week apart, no more than ~1-2 months old at time of test – the older the samples, the more likely Whiskers will grow

• Minimum 2 samples per lot for pre-condition for each test• Minimum 9 samples total per test

– Due to minimum 18 measurable terminations– Measurable termination = able to measure top and 2 sidesMeasurable termination = able to measure top and 2 sides

• Minimum 75 mm2 total inspection area per test• Minimum 25 mm2 total inspection area each sample

– Including at least 2 edges with 3 mm total length• Minimum 96 total inspection areas

– Must increase number of samples if cannot achieve 96 areas


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– Each inspection area should be > 0.85 mm2 (not including solder fillet)

JEDEC Allowable Whisker Length

MilitaryAerospace

TelecomAutomotive

IndustrialElectronics

ConsumerElectronics


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JEDEC Testing Requirements

• Whisker length chosen by established lead spacing requirements. spacing

• Saturation debate (Telecom):– Original allowable length was 65 micron

R d d t 40 i i l ifi d ith– Reduced to 40 micron since classified with automotive in JEDEC

– Move to separate infrastructure from human safety – form Class 2A


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•Reference List

Test Flow Example

Tin Whisker Test Flow for Ni-Underplated Passive Components with Four or Less Terminals

Plating Lot A(test finished parts)

Plating Lot B(plated >1 week after lot A)

Plating Lot C(plated >1 week after lot B)

(plated <4? weeks after lot A)Lot

3-5 percondition for

each test

Precondition: Reflow

No Precondition:Glued in Normal

Configuration

No Precondition: Glued in “Dead

Bug” ConfigurationCondition

27-45 parts goto ::: each test :::

~300-500 parts total(80-140 if re-use)


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Test Flow Example, stress tests


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Test Flow Example, examination


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Reference List• Annotated Tin Whisker Bibliography and Anthology George T Galyon IEEE Trans• Annotated Tin Whisker Bibliography and Anthology, George T. Galyon, IEEE Trans.

Elec. Pack., 28 (1), 94-122 (January 2005)• Role of Intrinsic Stresses in the Phenomena of Tin Whiskers in Electrical Connectors,

Sudarshan Lal and Thomas D. Moyer, IEEE Trans. Elec. Pack., 28 (1), 63-74 (January 2005)

• An Integrated Theory of Whisker Formation: The Physical Metallurgy of Whisker Formation and the Role of Internal Stresses, George T. Galyon and L. Palmer, IEEE Trans. Elec. Pack., 28 (1), 17-30 (January 2005)( ) ( y )

• An Electrical Characterization of Tin Whisker, Robert Hilty, Ned Corman, MRS Spring Meeting, San Francisco (2007)

• Tin Whisker Reliability Assessment by Monte Carlo Simulation, Robert Hilty, Ned Corman IPC/JEDEC Lead Free Symposium San Jose (2005)Corman, IPC/JEDEC Lead Free Symposium, San Jose (2005)

• Accelerated Tin Whisker Test Committee Update Phase 5, Heidi L. Reynolds, ECTC Tin Whisker Workshop, Reno, NV, (May 29, 2007)

• Matte Sn Electroplating in Mass Production and Testing According to JESD201, P Ob d ff M Ditt P C H Si l P S ECTC Ti Whi k W k h ROberndorff, M Dittes, P Crema, H Siegel, P Su, ECTC Tin Whisker Workshop, Reno, NV, (May 29, 2007)

• Evaluation of Conformal Coatings as a Tin Whisker Mitigation Strategy, Part II, Tom Woodrow, , Reno, NV, (May 29, 2007)


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Reference List• JESD22A121: Measuring Whisker Growth on Tin and Tin Alloy Surface Finishes (May• JESD22A121: Measuring Whisker Growth on Tin and Tin Alloy Surface Finishes (May

2005)• JP002: Current Tin Whiskers Theory and Mitigation Practices Guideline (March 2006)• JESD201: Environmental Acceptance Requirements for Tin Whisker Susceptibility of

Tin and Tin Alloy Surface Finishes (March 2006)


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Tin Whisker Phenomenon, Mitigation And Testing Overview V2

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Transcript of Tin Whisker Phenomenon, Mitigation And Testing Overview V2