Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear...

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Timing II Last updated 3/14/19

Transcript of Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear...

Page 1: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

Timing II

Last updated 3/14/19

Page 2: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

2 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations

• CD54HC174F

• SN54LS174J

• SN74LVC2G80DCUR

Page 3: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

3 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations

HD 54 LS 10

SN 74 HCT 2G 04 N

Manufacturer Prefix

Specs/Temp Indicator

Technology Indicator

Gates Count

Device Number

Package Designation

AD; Analog Devices

AM; Advanced Micro Devices

AT; Atmel

bq; Benchmarq

CA; RCA (analog)

CD; RCA (digital)

CLC; Comlinear Corp.

CS; Crystal Semiconductor

CS; Cherry Semiconductor

CY; Cypress Semiconductor

DG; Siliconix

DS; Dallas Semiconductor

DM; National Semiconductor (digital)

EDI; Electronic Designs Inc, EDI

EL; Elantec

EP; Altera (Classic series)

EPC; Altera (EPROM)

EPF; Altera (Flex series)

EPM; Altera (MAX series)

GM; Goldstar

HA; Hitachi (analog)

HAT; Hitachi

HD; Hitachi (digital)

HEF; Philips

HI; Harris

HM; Harris Microwave

HM; Hitachi

HY; Hyundai

HYB; Siemens

IDT; Integrated Devices Technology, IDT

IRF; International Rectifier

IP; Integrated Power

IT; Micron

HI; Intersil [Harris]

LGS; Goldstar

LM; National

M; Mitsubishi

MACH; Vantis (MACH, PLD)

MAX; Maxim

MB; Fujitsu

MC; Motorola

MN; Micro Networks

MT; Micron Technology

NDS; National Semiconductor

NE; Signetics

NEC; NEC

OKI; Oki Data

MC; ON Semiconductor [Motorola]

PI; Pericom

PM; PMI "Analog Devices"

PWM; Siliconix

QL; Quick Logic

QSI; Quality Semiconductor

SA; Signetics

SD; SGS Thomson

SE; Signetics

SEC; Samsung Electronics

SG; Silcon General

SI; Siliconix

SN; Texas Instruments, TI (Standard commercial grade parts)

SNJ; Texas Instruments, TI (MIL/QML Qualified)

SPT; Signal Processing Technologies, SPT

SSD; Samsung Electronics

SU; Signetics

SY; Synergy Semiconductor

TA; Toshiba

TC; Toshiba

TD; Pro-Electronics

TL; Texas Instruments (analog, Linear)

TMS; Texas Instruments

X; Xicor

XC; Xilinx

XR; Exar Corp.

uA; Fairchild

UC; Unitrode Integrated Circuits

Z; Zilog

ZD; Zeltex

Page 4: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

4 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations

HD 54 LS 10

SN 74 HCT 2G 04 N

Manufacturer Prefix

Specs/Temp Indicator

Technology Indicator

Gates Count

Device Number

Package Designation

Technology Indicator

None - When no indicator is found, this implies it's the original TTL

Bipolar

S - Schottky logic.

LS - Low-power Schottky. Same as L series but with reduced power consumption and switching speed.

CMOS

C - CMOS

AC / ACT - Advanced CMOS (T version for TTL-compatible inputs)

HC / HCT - High-speed CMOS, similar to LS (T version for TTL-compatible inputs)

AHC / AHCT - Advanced high-speed CMOS (T version for TTL-compatible inputs)

LV / LVC' - Low-Voltage CMOS

BiCMOS

BCT - BiCMOS

ABT - Advanced BiCMOS

Specs/Temp Indicator:

75 - Interface device

74 - Commercial Grade

64 - Industrial

54 - Military/Airspace Grade

0°C - 85 °C

-40°C - 100 °C

-55°C - 125 °C

https://en.wikichip.org/wiki/transistor-transistor_logic
https://en.wikichip.org/wiki/CMOS
https://en.wikichip.org/wiki/CMOS
https://en.wikichip.org/wiki/BiCMOS
Page 5: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

5 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations

HD 54 LS 10

SN 74 HCT 2G 04 N

Manufacturer Prefix

Specs/Temp Indicator

Technology Indicator

Gates Count

Device Number

Package Designation

7400 quad 2-input NAND gate

7401quad 2-input NAND gate, open collector outputs

7402 quad 2-input NOR gate

7403quad 2-input NAND gate, open collector outputs

7404 hex inverter

7405 hex inverter, open collector outputs

7406hex inverter buffer/driver, 30 V open collector outputs

7407 hex buffer/driver, 30 V open collector outputs

7408 quad 2-input AND gate

7409 quad 2-input AND gate, open collector outputs

7410 triple 3-input NAND gate

7411 triple 3-input AND gate

7412triple 3-input NAND gate, open collector outputs

7468 dual 4-bit decade counters

7469 dual 4-bit binary counters

7473 dual J-K flip-flop, asynchronous clear

7474 dual D positive edge triggered flip-flop, asynchronous preset and clear

7475 4-bit bistable latch

7476 dual J-K flip-flop, asynchronous preset and clear

7477 4-bit bistable latch

74H78 dual positive pulse triggered J-K flip-flop, preset, common clock and common clear

74L78 dual positive pulse triggered J-K flip-flop, preset, common clock and common clear

74LS78 dual negative edge triggered J-K flip-flop, preset, common clock and common clear

7479 dual D flip-flop

https://en.wikipedia.org/wiki/NAND_gate
https://en.wikipedia.org/wiki/Open_collector
https://en.wikipedia.org/wiki/NOR_gate
https://en.wikipedia.org/wiki/Inverter_(logic_gate)
https://en.wikipedia.org/wiki/AND_gate
https://en.wikipedia.org/wiki/Latch_(electronic)
Page 6: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

6 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations

HD 54 LS 10

SN 74 HCT 2G 04 N

Manufacturer Prefix

Specs/Temp Indicator

Technology Indicator

Gates Count

Device Number

Package Designation

D - DIP

DB - SSOP

FK - LCCC

J - CDIP

N - Plastic DIP

NS - SOP

PS - SOP

T - Flat package

W - CFP

Many more …

Page 7: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

7 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations• Packages

src: Harris & Harris

Page 8: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

8 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations

• SN 74 LS 74 Data Sheet

TI com low power DFFSchottky

Page 9: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

9 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations

• SN 74 LS 74 Data Sheet

Page 10: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

10 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations• SN74S74 TI com Schottky DFF

Page 11: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

11 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations• SN7474

Page 12: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

12 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations• SN74LS74

Page 13: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

13 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations• Fanout

• Fanout: 6-12 depending on inputs being driven

D Q

>

D Q

>

Iout max 20mA

Iin max 1.6mA

Page 14: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

14 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations

• SN 74 HC 74 Data Sheet

Page 15: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

15 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations• SN74HC74

Page 16: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

16 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations• SN74HC74

Page 17: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

17 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations• SN74HC74

Page 18: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

18 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations• SN74HC74 – fanout

• Fanout = 5

Page 19: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

19 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations• Connections between types

TTL -> CMOS

Page 20: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

20 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations• Connections between types

CMOS -> TTL

Page 21: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

21 © tjCE 1911

Digital Circuit Timing

• Discrete Logic Families

src: Harris & Harris

Page 22: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

22 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations• Power Considerations (CMOS)• 2 major power components

• Static• Current used when not switching

• Pstatic = VCC * I static

• Dynamic• Current used when switching

• Idynamic = C * dv/dt ≈ C * VCC / T = C * VCC * F

• P = VCC * Idynamic = VCC * C * VCC * F = C * VCC2 * F

• Note – ½ time sourcing current, ½ time sinking current

• P = ½ C * VCC2 * F

Page 23: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

23 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations

Page 24: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

24 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations

Page 25: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

25 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations

Page 26: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

26 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations

Page 27: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

27 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations

Page 28: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

28 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations

Page 29: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

29 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations

Page 30: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,

30 © tjCE 1911

Digital Circuit Timing

• Discrete Implementations


Flip and Flop

Flip and Flop

Adders, multiplexers, latches, flip-flops · –Latches + clock = flip-flop –Examples: SR latch, D flip-flop, JK flip-flop, T flip-flop 21 . Title: CSCI 255: Introduction to Embedded

Adders, multiplexers, latches, flip-flops · –Latches + clock = flip-flop –Examples: SR latch, D flip-flop, JK flip-flop, T flip-flop 21 . Title: CSCI 255: Introduction to Embedded

CENTRAL UNIVERSITY OF JAMMUcujammu.ac.in/5084/5084_media/courses/IT/IT_PG_Syllabus.pdfCENTRAL UNIVERSITY OF JAMMU ... R-S Flip Flop,J.K Flip Flop, Master-slave Flip Flops, T-flip Flop,

CENTRAL UNIVERSITY OF JAMMUcujammu.ac.in/5084/5084_media/courses/IT/IT_PG_Syllabus.pdfCENTRAL UNIVERSITY OF JAMMU ... R-S Flip Flop,J.K Flip Flop, Master-slave Flip Flops, T-flip Flop,

Conversion of an SR-Flip Flop to a JK-Flip Flop

Conversion of an SR-Flip Flop to a JK-Flip Flop

Flip Flop Count

Flip Flop Count

flip flop multivibrator

flip flop multivibrator

Latches e Flip-Flops - Página Principaldcc.ufrj.br/~gabriel/circlog/FlipFlop.pdf · Circuito Detector de Transição. Flip-Flop JK. Flip-Flop JK. Flip-Flop JK Transição Negativa.

Latches e Flip-Flops - Página Principaldcc.ufrj.br/~gabriel/circlog/FlipFlop.pdf · Circuito Detector de Transição. Flip-Flop JK. Flip-Flop JK. Flip-Flop JK Transição Negativa.

95414579 flip-flop

95414579 flip-flop

M&G katalog - Integrisana kola...7476 2x Flip-Flop with Preset and Clear 16 7478 2x Flip-Flop with Preset and Clear 14 74107 2x Flip-Flop with Clear 14 RS-FLIPFLOPS 74279 4x NAND Flip-Flop

M&G katalog - Integrisana kola...7476 2x Flip-Flop with Preset and Clear 16 7478 2x Flip-Flop with Preset and Clear 14 74107 2x Flip-Flop with Clear 14 RS-FLIPFLOPS 74279 4x NAND Flip-Flop

Ch5 Flip Flop

Ch5 Flip Flop

Sequential Circuit Latch & Flip-flop. Contents Introduction Memory Element Latch SR latch D latch Flip-flop SR flip-flop D flip-flop JK flip-flop.

Sequential Circuit Latch & Flip-flop. Contents Introduction Memory Element Latch SR latch D latch Flip-flop SR flip-flop D flip-flop JK flip-flop.

ELE22MIC Lecture 19, 20, 21 Edge Detector Latch vs Flip Flop –S-R Latch, Transparent D-Latch –Clocked D-Latch –J-K Flip Flop, Toggle Flip Flop Flip Flop.

ELE22MIC Lecture 19, 20, 21 Edge Detector Latch vs Flip Flop –S-R Latch, Transparent D-Latch –Clocked D-Latch –J-K Flip Flop, Toggle Flip Flop Flip Flop.

Flip Flop Conversion

Flip Flop Conversion

CHANTHA THOEUN Flip-flop Circuits. Types of Flip-flops SR flip-flop (Set, Reset) T flip-flop (Toggle) D flip-flop (Delay) JK flip-flop.

CHANTHA THOEUN Flip-flop Circuits. Types of Flip-flops SR flip-flop (Set, Reset) T flip-flop (Toggle) D flip-flop (Delay) JK flip-flop.

Dual D-Type Positive Edge Triggered Flip-Flop With Clear and Preset

Dual D-Type Positive Edge Triggered Flip-Flop With Clear and Preset

Bab5 flip-flop

Bab5 flip-flop

Latches and Flip-Flops Discussion D7.1. Latches and Flip-Flops Latches –SR Latch –D Latch Flip-Flops –D Flip-Flop –JK Flip-Flop –T Flip-Flop.

Latches and Flip-Flops Discussion D7.1. Latches and Flip-Flops Latches –SR Latch –D Latch Flip-Flops –D Flip-Flop –JK Flip-Flop –T Flip-Flop.

Flip flop poem

Flip flop poem

1 Sequential Circuit Latch & Flip-flop. 2 Contents Introduction Memory Element Latch SR latch D latch Flip-flop SR flip-flop D flip-flop JK.

1 Sequential Circuit Latch & Flip-flop. 2 Contents Introduction Memory Element Latch SR latch D latch Flip-flop SR flip-flop D flip-flop JK.

Exercise 2: Dynamic Operation of a JK Flip-Flop - Lab … FLIP-FLOP Digital Logic Fundamentals Exercise 2: Dynamic Operation of a JK Flip-Flop ... CLOCK, OPEN COLLECTOR, and JK FLIP-FLOP

Exercise 2: Dynamic Operation of a JK Flip-Flop - Lab … FLIP-FLOP Digital Logic Fundamentals Exercise 2: Dynamic Operation of a JK Flip-Flop ... CLOCK, OPEN COLLECTOR, and JK FLIP-FLOP