The Track-Finding Processor for the Level-1 Trigger of the CMS Endcap Muon System D.Acosta,...
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Transcript of The Track-Finding Processor for the Level-1 Trigger of the CMS Endcap Muon System D.Acosta,...
The Track-Finding Processor for the Level-1 Trigger of the CMS
Endcap Muon System
D.Acosta, A.Madorsky, B.Scurlock, S.M.Wang
University of Florida
A.Atamanchuk, V.Golovtsov, B.Razmyslovich
St. Petersberg Nuclear Physics Institute
LEB99 Workshop, September 21, 1999
D. Acosta, University of Florida 2
Muon Track-Finding
• Perform 3D track-finding from trigger primitives
• Measure PT , , and
• Transmit highest PT candidates to Global Level-1
LEB99 Workshop, September 21, 1999
D. Acosta, University of Florida 3
Track-Finder Requirements
• High efficiency with low PT threshold
• Single muon trigger rate < few kHz at L=1034 cm-2s-1
– Should have large safety factor
• PT resolution 20%
– Require , information from 3 muon stations
• Multi-muon capability 3 muons per 60° azimuthal sector
– Best 4 muons overall sent to Global Level-1 Trigger
• Pipelined and deadtime-less– 40 MHz B.X. frequency
• Minimal latency – < 16 B.X. (400 ns)
• Programmable– FPGA and RAM implementation
LEB99 Workshop, September 21, 1999
D. Acosta, University of Florida 4
Trigger Regions in
Cathode Strip Chamber System
Drift-Tube systemOverlap 1.2 > > 0.9
• 4 muon stations in each endcap• Each station contains 6 layers of CSC chambers
• PT measured from fringe field of 4 T solenoid using 3D track segments in each station
LEB99 Workshop, September 21, 1999
D. Acosta, University of Florida 5
Trigger Regions in
ME1/3
MB2/2
MB2/1
Illustration of overlap region
Track-Finding performed in independent 60° sectors
LEB99 Workshop, September 21, 1999
D. Acosta, University of Florida 6
Why Two Muon Track-Finders?
• The Barrel Track-Finder:– intrinsically 2D
• road-finding in only (expect low rates)
• uniform magnetic field in central region
– large number of neighbor interconnections
• chambers are staggered, non-projective
• The Endcap Track-Finder:– intrinsically 3D
• road-finding in and to reduce backgrounds
• non-uniform magnetic field in endcap
– No interconnections between trigger sectors
• chambers are projective in • small bending in endcap
• Therefore, different needs in each region imply two different designs
• Must ensure that fake double triggers do not occur in region of overlap
LEB99 Workshop, September 21, 1999
D. Acosta, University of Florida 7
Level-1 Trigger Scheme
Strip FE cards
Wire FE cards
Motherboard
TMB
Port Card
PC
Sector Receiver Sector Processor
OPTICAL
SR SP
CSC Track-Finder
CSC Muon Sorter
Global Trigger
DTRPC
FE
FE
Global L1
2 / chamber 3 / port card 3 / sector
4
4
4 4
LCT
LCT
Strip LCT card
Wire LCT card
On chamber On periphery
In counting house36
LEB99 Workshop, September 21, 1999
D. Acosta, University of Florida 8
Track-Finder Architecture
• Track-Finder implemented as 12 Sector Processors
• Each Sector Processor: – Implemented on a 9U VME card
– Processes 15 CSC segments and 8 DT segments
– Identifies 3 muons per 60°
• CSC data received by 3 Sector Receiver cards– Each receives 6 track segments on optical links
– Reformats data to , b ,
– Applies alignment corrections
– Communicates to Sector Processors via custom point-to-point backplane
– Presently under development at UCLA
• DT data sent to transition board at back of crate
• Custom point-to-point backplane:– Delivers ~600 bits every 25 ns (3 GB/s)
– Operates at 280 MHz to reduce connections:
• National Channel Link 28:4 serialization
– Presently being prototyped in Florida
LEB99 Workshop, September 21, 1999
D. Acosta, University of Florida 9
Sector Processor Layout
P1
CCB
SR4 st.
SR1,3 st.
SR1,2 st.
SRBarrel
Ch
ann
el L
inks
2 B
unch
Cro
ssin
g A
nal
yzer
VMEInterface
ControlLogic
Ext
rap
olat
ion
Un
its
Glo
bal
Bu
ffer
(F
IFO
s)
FinalSelection
Unit
TA
U1
(ove
rlap
)
Pt-
assi
gnm
ent
Un
its
(FP
GA
s)
OutputData
Storage
Ch
ann
el L
inks
FPGADownload
Logic
Control Logic(Clock distribution, SRAM read/write
and other devices)
LE
DD
rive
rs
CustomBackplane
TA
U2
(en
dcap
)
Pt-
assi
gnm
ent
Un
its(
LU
Ts)
TransitionModule
LEB99 Workshop, September 21, 1999
D. Acosta, University of Florida 10
Sector Processor Logic
• Latch input and hold for possibly more than one B.X.– Allows for timing errors from trigger primitives
• Perform all possible station-to-station extrapolations in parallel– Simultaneously search roads in and
• Assemble 3- and 4-station tracks from 2-station extrapolations
• Cancel redundant short tracks if track is 3 or 4 stations in length
• Select the three best candidates
• Calculate PT , , and send to CSC muon sorter
LEB99 Workshop, September 21, 1999
D. Acosta, University of Florida 11
Two Bunch Crossing Mode
• Input data can be latched for 2 B.X. to accommodate timing errors from trigger primitives
• Sector Processor still reports trigger at correct B.X.
Title:(dblecnt.eps)Creator:Adobe Illustrator(R) 8.0Preview:This EPS picture was not savedwith a preview included in it.Comment:This EPS picture will print to aPostScript printer, but not toother types of printers.
LEB99 Workshop, September 21, 1999
D. Acosta, University of Florida 12
Extrapolation Unit
FF3
FF3
FF6
LUT64x2
LUT64x1
SB
LUT64x1
LUT64x7low
LUT64x7med
LUT64x7high
SB
FF5
ABS
FF5
FF5
FF5
FF1
FF6
FF10
FF10
FF1
FF2
FF7
FF1
FF10
FF7
FF7
FF7
FF1
LUT32x5
1min
LUT32x5
1max
LUT32x5
min
LUT32x5
max
FF5
FF5
NOTAND
FF1
FF1
Amb1
Amb2
1
2
1
2
1
2
Q1
Q2
LUT128x1
GlobalClock
SB
1
SB
1
SB
2
SB
2
LUT8x1
SBh
SBm
SBl
enable
LUT32x2
enable
6 -inputAND
3 -inputAND
FF2
ExtrapolationQuality
FF1
FF1
FF1
FF1
FF1
FF1
FF1
FF1
FF1
FF1
FF1
FF1
FF2
road finder
Course Pt assign
road finder
Z
1Bx 1Bx 1Bx
Xilinx Virtex FPGA XCV150
LEB99 Workshop, September 21, 1999
D. Acosta, University of Florida 13
Track Assembly Procedure
Title:(streams.eps)Creator:Adobe Illustrator(R) 8.0Preview:This EPS picture was not savedwith a preview included in it.Comment:This EPS picture will print to aPostScript printer, but not toother types of printers.
LEB99 Workshop, September 21, 1999
D. Acosta, University of Florida 14
Track Assembler Unit
SRAM256Kx16
IDT
LINK33
LINK32
LINK31
Fro
m E
xtra
pol
atio
n U
nits
12
3
3
12
3
3
12
3
3
ME33 – ME4
ME33 – ME2
ME33 – ME1
ME32 – ME4
ME32 – ME2
ME32 – ME1
ME31 – ME4
ME31 – ME2
ME31 – ME1
To
Fin
al S
elec
tion
Uni
t
9
6
9
6
9
6
6 bit Ranking &9 bit hit i.d. :
LINK23
LINK22
LINK21
12
3
3
12
3
3
12
3
3
ME23 – ME4
ME23 – ME3
ME23 – ME1
ME22 – ME4
ME22 – ME3
ME22 – ME1
ME21 – ME4
ME21 – ME3
ME21 – ME1
9
6
9
6
6
9
LINK23
LINK22
LINK21
4
6
4
6
4
6
ME23 – ME1
ME23 – MB2
ME23 – MB1
ME22 – ME1
ME22 – MB2
ME22 – MB1
ME21 – ME1
ME21 – MB2
ME21 – MB1
9
6
9
6
6
9
8
8
8
Extrapolation output small enough to address SRAM for quick decision
LEB99 Workshop, September 21, 1999
D. Acosta, University of Florida 15
The Final Selection Unit A Sorter with Cancellation Logic
“Final Selection Unit”FPGA XCV50 (XILINX)
Fro
m T
rack
Ass
emb
ler
Un
itSt
ream
1 –
ME
2 ke
y st
atio
nSt
ream
2 –
ME
2 ke
y st
atio
nSt
ream
3 –
ME
3 ke
y st
atio
n
Ext
rapo
lati
ons
Qua
lity
Com
para
tors
(36
Uni
ts)
Hit
Num
ber
Com
para
tors
(36
Uni
ts) FinalDecision Unit
9
9
9
9
9
9
6
6
6
6
6
6
36
36
13
13
13
Hit
Num
ber
Part
Ext
rapo
latio
n Q
ualit
y Pa
rt
17 bits:1st stub number – 5 bits;2nd stub number – 5 bits;3rd stub number – 5 bits;2-stn or 3-stn mode – 1 bit;overlap or endcap track – 1 bit.
4 4 4
Track 1
Track 3
Track 2
Track 6
Track 5
Track 4
Track 1
Track 3
Track 2
Track 6
Track 5
Track 4
9
9
9
ConverterEnable
ConverterEnable
ConverterEnable
4
4
4
9
9
9
Stre
am 2
Station ME2
Station MB1Station MB2Station ME1
3
446
Fro
m 2
Bx
An
alyz
erB
unch
cro
ssin
g ID
1
1
1
To
Ass
ignm
ent
Uni
t (F
PG
As)
4 bits:1st stub Bx ID – 1 bit;2nd stub Bx ID – 1 bit;3rd stub Bx ID – 1 bit;4th stub Bx ID – 1 bit.
MUX
Sel1 Sel2 Sel3
MODE
MUX
Select
MUX
Select
MUX
Select
AND
AND
AND
1
1
1
1
1
1
1
1
1
1
1
1
Converter
Converter
Converter
17
17
17 To
Ass
ignm
ent
Uni
t (F
PG
As)
To prohibitDouble Count
To select3 best tracks
out of 9
Track 7
Track 8
Track 9
56
6
6
9
9
9
9
9
9
Track 7
Track 8
Track 9
Stre
am 3
Stre
am 1
Stre
am 2
Stre
am 3
Stre
am 1
Station ME3 3Station ME4 3
0 – no 1 – a Match bit unset (only for 3-stn)2 – 1-2-33 – 1-2-44 – 1-3-45 – 2-3-46 – 1-27 – 1-38 – 2-39 – 2-410 – 3-4
11 – MB1-MB2-ME212 – MB1-ME1-ME213 – MB2-ME1-ME214 – MB1-ME215 – MB2-ME2
VHDL code written
LEB99 Workshop, September 21, 1999
D. Acosta, University of Florida 16
Assignment Unit
• Determines , , PT of the selected 3 best muons
• PT assignment uses , measurements from 2 or 3 stations PT/PT ~ 30% with only 2 stations
PT/PT ~ 20% with 3 stations improves Level-1 rate reduction
• Implemented with FPGA preprocessing followed by large SRAM look-up table
2Mb16 SRAM
FPGA
LEB99 Workshop, September 21, 1999
D. Acosta, University of Florida 17
Summary of CSC Track-Finder
• Conceptual design complete• 12 Sector Processors cover CSC and CSC/DT
overlap– 1.0 < < 2.4 and = 60° on one board
• Track-finding algorithms are three-dimensional– Improves background suppression
• PT assignment includes , measurements from 3 stations PT/PT ~ 20% (30% with only 2 stations)
– Significantly improves rate reduction at Level-1
• Inputs can be latched for 2 B.X.– Tolerates timing errors from trigger primitives
• Latency expected to be only 14 B.X.• Fully re-programmable• Xilinx Virtex FPGAs and SRAM used• Board layout and backplane design started