The future of Amalogue Test - NMI DFT event

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Confidential © ams AG 2015 Looking to the Future for DFT and Analogue Test National Microelectronic Institute Peter Sarson CEng MIET CMgr MCMI Full Service Foundry 16 th April 2015

Transcript of The future of Amalogue Test - NMI DFT event

Page 1: The future of Amalogue Test - NMI DFT event

Confidential © ams AG 2015

Looking to the Future

for DFT and Analogue Test

National Microelectronic Institute

Peter Sarson CEng MIET CMgr MCMI

Full Service Foundry

16th April 2015

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Automotive TestExisting Challenges

Historically Low Volume, High Reliability

More extensive and exhaustive testing

• Very long test times

• Limited resources needed extensively around the device

Potentially compromising loadboard design

• Long time to market

Expensive RMA process – 2 man years at ams AG

• Extensive failures analysis

• 8D reports

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Consumer TestExisting Challenges

High Volume

Bare bones testing, system tests

• Short test times

• Complicated multi-site boards, high parallelism

Long down times due to setup issues during production

• Fast time to market

Non-existent RMA flow

• Generally only receive RMA during cost negotiations

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Automotive test Future Challenges

A move to higher supply voltages, more complex test boards

• Fewer resources available, and lower accuracy

• Requires more resource sharing

Higher volume

An even greater focus on product quality and reliability

• As devices get larger and more complex, more defects missed by test

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ConsumerFuture Challenges

Our current high-volume consumer customers requesting more

automotive-style product qualifications

More precision

• Less chance for parallelism, which increases cost

More RMA received – More than 2 man years?

Even higher volume

• Need more parallelism

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Automotive and Consumer Future Challenges

• Automotive and consumer requirements will merge

and a single standard will be adopted for all semiconductor segments

• Larger ASICS, smaller geometries, more defects per sq. mm

More focus on defect-based testing,

since spec testing simply doesn’t find all defects.

• We will need more design tools to calculate analogue test coverage

to show where test coverage is missing

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Automotive and Consumer Future Challenges

• We need to focus more on automated analogue DFT to allow muxing

signals on-chip, to single points on loadboards

To aid test board reliability, device debug, automated test generation

Access to nodes we simple don’t have access to today

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Measurement System Analysis V4 spec change

• Automotive industry has seen a requirement to change the MSA spec

due to very tight requirements becoming unrealistic

Means? No need for such accuracies and test repeatability to pass

requirements use Cp(observed) rather than Cp

Possibly built-in test measurement accuracy can be relaxed

• Applicable to Consumer parts for high volumes, not just Automotive!

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New Release Criteria

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IEEE 1687 Standard

• A new approach to scan access based on IEEE 1149.1 and 1500

Allows faster, simpler access to IP blocks (“instruments”) via scan

• Intended to also allow test access to the IP blocks in the field

• Tools currently available from some EDA vendors

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Analogue Defect Simulation

• No commercially available tools

• Published papers proposed many different techniques over last 30

years, with no really usable result

• With larger ASICS and more defects in the analogue circuitry,

it becomes much more critical to finding reliability-related defects

• Analogue Defect Simulation shows where coverage is lacking

and hence where more test access is needed

• “An analysis of random sampling for analog fault simulation,”

Stephen Sunter, Mentor Graphics, ETS 2014 STEM Workshop

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Ad hoc working group

• A group of motivated people from industry working together to find

common ground in mixed-signal DFT and test generation

• Work on-going to develop standard way to describe Analogue Test Bus

and ADC/DAC serial access using 1687 syntax, to allow automation

• Focused on Defect-Oriented Test (DOT), rather than spec testing

This simplifies the problem for an Analogue BIST approach

• “A Mixed-Signal Test Bus and Analog BIST with 'Unlimited' Time and

Voltage Resolution,” Stephen Sunter, Mentor Graphics, ETS 2011

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Thank you

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