Testing of Synchronous Sequential Circuits

By

Dr. Amin Danial Asham

References

An Introduction to Logic Circuit Testing

Transfer Tree•It is often necessary to take the circuit into a predetermined state, after the homing sequence has been applied. This is done with the help of a transfer sequence, which is the shortest input sequence that takes a machine from state Si to state Sj .

•Example: for the following machine: we want to drive the it from state B to state C.

•Shortest path is the input sequence 00

Designing checking Experiments•Basically, the purpose of a checking experiment is to verify that the state table of a sequential circuit accurately describes its behavior. If during the execution of the experiment the circuit produces a response that is different from the correctly operating circuit, the circuit is definitely faulty.

•Such experiments can be used only to determine whether or not something is wrong with a circuit; it is not possible to conclude from these experiments what is wrong with the circuit.

•A checking experiment can be designed for:1. A strongly connected sequential circuit2. There is it at least one distinguishing sequence.

Designing checking Experiments• The checking experiment can be divided into three phases:

1. Initialization phase. During the initialization phase, the circuit under test is taken from an unknown initial state to a fixed state by the following method:

a. Apply a homing sequence to the circuit and identify the current state of the circuit.

b. If the current state is not the desired state, apply a transfer sequence to move the circuit from the current state to the desired state.

2. State identification phase: During this phase, an input sequence is applied so as to cause the circuit to visit each of its states and display its response to the distinguishing sequence.

3. Transition verification phase. During this phase, the circuit is made to go through every state transition; each state transition is checked by using the distinguishing sequence.

• Although these three phases are distinct, in practice, the subsequences for state identification and transition verification are combined whenever possible in order to shorten the length of the experiment. The length is the total number of input symbols applied to the circuit during the execution of an experiment; it is a measure of efficiency of the experiment.

Designing checking Experiments (continue)

Example•Consider FSM

Successor Tree

(ABCD)

0

(BC)1(AB)0

1

(AD)1(AC)0

(B)1(A)0(AB)0

0 1

(D)1(A)0(D)1(C)0

Distinguishing

(BC)1(B)1(B)0

(A)1(C)0(AC)0

0 1

Therefore, sequence 01 is HS and DS

Example (cont.)1. Initialization phase:

Response TableInit. State Response to 0 1 Final State Output

Sequence

A B , 1 D ,1 D 1 1

B A , 0 C , 0 C 0 0

C B , 0 D , 1 D 0 1

D C , 1 A , 0 A 1 0

Example (cont.)2. Identification Phase:

Time

Input

State

Output

1 2 3 4 5 6 7 8 9 10 11

0 1 0 1 0 0 1 0 1 0 1

A D A B C D A

1 1 1 0 1 0 0 0 1 1 0

Example (cont.)3. Transition Verification Phase:

Input

State

Output

0 01 0 01 1 01 1 01 0 01 1 1 01 1 0 1 01 0 0 01 1

A B C B C A D A D C D A C D A B D A B A D A

1 00 0 00 0 11 1 11 1 01 1 0 01 1 1 1 10 1 0 11 1

All Possible Transitions

Thanks