Teralane Semiconductor - Display Future · Dummy5, Dummy6 115 39 Bumped Pad Size Dummy7, Dummy8 39...

TLS8103 Datasheet – Teralane Semiconductor, Inc.

TTLLSS88110033

132 RGB Segment x 132 Common Driver & Controller

For 65536 Colors STN LCD

Version 2.3 Jul., 2007

Notice: Specifications and information contained in this Datasheet are subject to change without notice. No part of this Datasheet may be copied or transmitted in any form or by any means, electronic or non-electronic media, for any purpose, without the written permission of Teralane Semiconductor Inc. Precautions for light: Light has the effect of causing the electrons of semiconductor to move and may change the characteristics of semiconductor devices. For this reason, it is necessary to take account of effective protection measures for the packages (such as COB, COG, TCP and COF, etc) causing chip to be exposed to a light environment in order to isolate the projection of light on any part of the chip, including top, bottom and the area around the chip. Follow the precautions below when using this product: 1) During the design stage, it is necessary to notice and confirm the light sensitivity and preventive measures for using IC on substrate (PCB, Glass or Film) or product. 2) Test and inspect the product under an environment free of light source penetration. 3) Confirm that all surfaces around the IC will not be exposed to light source.

Teralane Semiconductor Product Data Sheet

TLS8103 Datasheet

Teralane Semiconductor, Inc Confidential Version 2.3 Aug.,2007 2 / 94

Contents

INTRODUCTION............................................................................................................................................................6

FEATURES......................................................................................................................................................................6

PAD ARRANGEMENT...................................................................................................................................................9

PAD CENTER COORDINATES ................................................................................................................................... 11

PIN DESCRIPTION.......................................................................................................................................................41

ITO REQUIREMENTS........................................................................................................................................................51

BLOCK DIAGRAM.......................................................................................................................................................54

FUNCTION DESCRIPTIONS .......................................................................................................................................56

COMMAND TABLE ...................................................................................................................................................105

COMMAND DESCRIPTION ...................................................................................................................................... 115

INITIALIZATION SEQUENCE ..................................................................................................................................173

VOP CALIBRATION ..................................................................................................................................................177

AC CHARACTERISTICS ...........................................................................................................................................180

DC CHARACTERISTICS ...........................................................................................................................................190

ABSOLUTE MAXIMUM RATING.............................................................................................................................192

APPLICATION NOTES ..............................................................................................................................................194

APPLICATION INFORMATION FOR LCD PANEL (REFERENCE EXAMPLE) ........................................................................194 APPLICATION INFORMATION FOR PIN CONNECTION TO MPU (REFERENCE EXAMPLE)..................................................197

REVISION HISTORY .................................................................................................................................................205

TLS8103 Datasheet


INTRODUCTION

TLS8103 is a low power single-chip CMOS Color STN LCD driver with integrated controller. It consists of 396 Segment and 132 Common driver circuits, which can drivers 132RGB x 132, 128RGB x 128 CSTN LCD panels.

TLS8103 integrates 132 x 132 x 16 bits Graphic Display Data RAM, On-Chip Oscillator, DC-DC Converter, and LCD driving voltage generation circuit to provide a low-cost solution. For being connected with microprocessors, TLS8103 supports four kinds of MCU interfaces: 8-bit 6800-series or 8080-series Parallel interface, 3-wires /4-wires Serial Peripheral Interface. TLS8103 adopts APT (Hi-Fas) and built-in capacitors architecture to achieve high-performance display by minimum power consumption and external components.

FEATURES

Display Resolution: 132RGB x 132

On-chip Display Data SRAM: 132 x 132 x 16 = 278,784 bits

Interface Color Modes:

256 colors RGB = (332) mode

4096 colors RGB = (444) mode

Full colors 65K RGB = (565) mode

Truncated 262K colors (RGB) = (666) mode

Truncated 16M colors (RGB) = (888) mode

8 Colors Mode for Display IDLE Power Saving

Microprocessor Interface:

8-bit 6800 Parallel interface

8-bit 8080 Parallel interface

3-wires Serial Interface

4-wires Serial Interface

Special Display Modes:

Area Scrolling

Partial windows moving

3 set (RGB) of CLUT for 256 colors and 4096 colors map to 65K colors

3 set (RGB) of 128-steps Palettes for panel gamma correction

On-chip Low Power Analog Circuit:

Oscillator with internal resistors and capacitors

DC-DC Converter (x4, x5, x6, x7, x8) with internal booster capacitors

Extremely few external components: 4 capacitors

+/-64 steps electronic contrast control circuits

LCD driving voltage generation circuits

Programmable temperature compensation of VLCD and frame frequency

+/-128 Steps MTP for LCD driving voltage calibration

TLS8103 Datasheet


Block Polarity Inversion for low cross talk

Power Supply Voltage:

VCC = 2.5 ~ 3.3V (power supply for internal VDD regulator, whatever internal regulator close or open)

VDD = 1.65 ~ 1.95V (external power supply for logic, when internal regulator close; internal regulator generate the power supply for logic, when internal regulator open)

VDDIO = 1.65 ~ 3.3V (power for digital IO) VCI = 2.5 ~ 3.3V (power for analog) VLCD = max 18V (LCD driving voltage)

Package Type: Application for COG

TLS8103 Datasheet


PAD ARRANGEMENT

Figure 1 TLS8103 Pad arrangement diagram

Table 1 TLS8103 Pad bump size and alignment key coordinates

Size(um) Item Pad No. X(um) Y(um)

Die Size 11400 760 Die Thickness 400 (+/-25um)

COM0~131, SEG0~395 26 PAD0-116 70

Pad Pitch

Dummy1~Dummy8 52 COM49~COM0 13.5 115 PAD0~PAD116 50 52 COM131~COM82 13.5 115 Dummy1, Dummy2 39 115 Dummy3, Dummy4 115 39 COM81~COM66 115 13.5 SEG99~SEG0 13.5 115 SEG197~SEG100 13.5 115 SEG295~SEG198 13.5 115 SEG395~SEG296 13.5 115 COM65~COM50 115 13.5 Dummy5, Dummy6 115 39

Bumped

Pad Size

Dummy7, Dummy8 39 115 Bump Height 15 (+/- 3um)

Coordinate X Y

Alignment A 5007.43 173.80 Alignment B -5355.00 -115.70

Alignment Key

Alignment C 5355.00 -115.70

TLS8103 Datasheet


PAD CENTER COORDINATES

Table 2 TLS8103 Pad center coordinates

NUM PADNAME X Y LOCATION

1 dummy_pad7 -5621.000 -297.000 BOTTOM

2 dummy_pad8 -5569.000 -297.000 BOTTOM

3 COM_PAD -5530.000 -297.000 BOTTOM

4 COM_PAD -5504.000 -297.000 BOTTOM

5 COM_PAD -5478.000 -297.000 BOTTOM

6 COM_PAD -5452.000 -297.000 BOTTOM

7 COM_PAD -5426.000 -297.000 BOTTOM

8 COM_PAD -5400.000 -297.000 BOTTOM

9 COM_PAD -5374.000 -297.000 BOTTOM

10 COM_PAD -5348.000 -297.000 BOTTOM

11 COM_PAD -5322.000 -297.000 BOTTOM

12 COM_PAD -5296.000 -297.000 BOTTOM

13 COM_PAD -5270.000 -297.000 BOTTOM

14 COM_PAD -5244.000 -297.000 BOTTOM

15 COM_PAD -5218.000 -297.000 BOTTOM

16 COM_PAD -5192.000 -297.000 BOTTOM

17 COM_PAD -5166.000 -297.000 BOTTOM

18 COM_PAD -5140.000 -297.000 BOTTOM

19 COM_PAD -5114.000 -297.000 BOTTOM

20 COM_PAD -5088.000 -297.000 BOTTOM

21 COM_PAD -5062.000 -297.000 BOTTOM

22 COM_PAD -5036.000 -297.000 BOTTOM

23 COM_PAD -5010.000 -297.000 BOTTOM

24 COM_PAD -4984.000 -297.000 BOTTOM

25 COM_PAD -4958.000 -297.000 BOTTOM

26 COM_PAD -4932.000 -297.000 BOTTOM

27 COM_PAD -4906.000 -297.000 BOTTOM

28 COM_PAD -4880.000 -297.000 BOTTOM

29 COM_PAD -4854.000 -297.000 BOTTOM

30 COM_PAD -4828.000 -297.000 BOTTOM

31 COM_PAD -4802.000 -297.000 BOTTOM

32 COM_PAD -4776.000 -297.000 BOTTOM

33 COM_PAD -4750.000 -297.000 BOTTOM

34 COM_PAD -4724.000 -297.000 BOTTOM

35 COM_PAD -4698.000 -297.000 BOTTOM

36 COM_PAD -4672.000 -297.000 BOTTOM

37 COM_PAD -4646.000 -297.000 BOTTOM

38 COM_PAD -4620.000 -297.000 BOTTOM

TLS8103 Datasheet


39 COM_PAD -4594.000 -297.000 BOTTOM

40 COM_PAD -4568.000 -297.000 BOTTOM

41 COM_PAD -4542.000 -297.000 BOTTOM

42 COM_PAD -4516.000 -297.000 BOTTOM

43 COM_PAD -4490.000 -297.000 BOTTOM

44 COM_PAD -4464.000 -297.000 BOTTOM

45 COM_PAD -4438.000 -297.000 BOTTOM

46 COM_PAD -4412.000 -297.000 BOTTOM

47 COM_PAD -4386.000 -297.000 BOTTOM

48 COM_PAD -4360.000 -297.000 BOTTOM

49 COM_PAD -4334.000 -297.000 BOTTOM

50 COM_PAD -4308.000 -297.000 BOTTOM

51 COM_PAD -4282.000 -297.000 BOTTOM

52 COM_PAD -4256.000 -297.000 BOTTOM

53 GITOL -4045.835 -327.800 BOTTOM

54 V0 -3975.835 -327.800 BOTTOM

55 V0 -3905.835 -327.800 BOTTOM

56 V0 -3835.835 -327.800 BOTTOM

57 V0 -3765.835 -327.800 BOTTOM

58 V0 -3695.835 -327.800 BOTTOM

59 V0 -3625.835 -327.800 BOTTOM

60 XV0 -3555.835 -327.800 BOTTOM

61 XV0 -3485.835 -327.800 BOTTOM

62 XV0 -3415.835 -327.800 BOTTOM

63 XV0 -3345.835 -327.800 BOTTOM

64 XV0 -3275.835 -327.800 BOTTOM

65 XV0 -3205.835 -327.800 BOTTOM

66 LCDVSS -3135.835 -327.800 BOTTOM

67 LCDVSS -3065.835 -327.800 BOTTOM

68 LCDVSS -2995.835 -327.800 BOTTOM

69 LCDVSS -2925.835 -327.800 BOTTOM

70 LCDVSS -2855.835 -327.800 BOTTOM

71 LCDVSS -2785.835 -327.800 BOTTOM

72 LCDVSS -2715.835 -327.800 BOTTOM

73 LCDVSS -2645.835 -327.800 BOTTOM

74 VSS -2575.835 -327.800 BOTTOM

75 VSS -2505.835 -327.800 BOTTOM

76 VSS -2435.835 -327.800 BOTTOM

77 VSS -2365.835 -327.800 BOTTOM

78 VSS -2295.835 -327.800 BOTTOM

79 VSS -2225.835 -327.800 BOTTOM

80 VSS -2155.835 -327.800 BOTTOM

81 VSS -2085.835 -327.800 BOTTOM

82 GND -2015.835 -327.800 BOTTOM

TLS8103 Datasheet


83 GND -1945.835 -327.800 BOTTOM

84 GND -1875.835 -327.800 BOTTOM

85 GND -1805.835 -327.800 BOTTOM

86 GND -1735.835 -327.800 BOTTOM

87 GND -1665.835 -327.800 BOTTOM

88 GND -1595.835 -327.800 BOTTOM

89 GND -1525.835 -327.800 BOTTOM

90 VDDIO -1455.835 -327.800 BOTTOM

91 VDDIO -1385.835 -327.800 BOTTOM

92 VDDIO -1315.835 -327.800 BOTTOM

93 VDDIO -1245.835 -327.800 BOTTOM

94 VDDIO -1175.835 -327.800 BOTTOM

95 VDDIO -1105.835 -327.800 BOTTOM

96 VDDIO -1035.835 -327.800 BOTTOM

97 VDDIO -965.835 -327.800 BOTTOM

98 VPP -895.835 -327.800 BOTTOM

99 VPP -825.835 -327.800 BOTTOM

100 VPP -755.835 -327.800 BOTTOM

101 CL -685.835 -327.800 BOTTOM

102 CLS -615.835 -327.800 BOTTOM

103 VDDIO -545.835 -327.800 BOTTOM

104 D_C -475.835 -327.800 BOTTOM

105 RW_WR -405.835 -327.800 BOTTOM

106 D -335.835 -327.800 BOTTOM

107 D -265.835 -327.800 BOTTOM

108 D -195.835 -327.800 BOTTOM

109 D -125.835 -327.800 BOTTOM

110 D -55.835 -327.800 BOTTOM

111 D 14.165 -327.800 BOTTOM

112 D 84.165 -327.800 BOTTOM

113 D 154.165 -327.800 BOTTOM

114 GND 224.165 -327.800 BOTTOM

115 VDDIO 294.165 -327.800 BOTTOM

116 E_RD 364.165 -327.800 BOTTOM

117 RST 434.165 -327.800 BOTTOM

118 CSEL 504.165 -327.800 BOTTOM

119 PS 574.165 -327.800 BOTTOM

120 PS 644.165 -327.800 BOTTOM

121 PS 714.165 -327.800 BOTTOM

122 GND 784.165 -327.800 BOTTOM

123 VDDIO 854.165 -327.800 BOTTOM

124 CS 924.165 -327.800 BOTTOM

125 TE 994.165 -327.800 BOTTOM

126 T1 1064.165 -327.800 BOTTOM

TLS8103 Datasheet


127 T2 1134.165 -327.800 BOTTOM

128 T3 1204.165 -327.800 BOTTOM

129 T4 1274.165 -327.800 BOTTOM

130 T5 1344.165 -327.800 BOTTOM

131 T6 1414.165 -327.800 BOTTOM

132 T7 1484.165 -327.800 BOTTOM

133 VDD 1554.165 -327.800 BOTTOM

134 VDD 1624.165 -327.800 BOTTOM

135 VDD 1694.165 -327.800 BOTTOM

136 VDD 1764.165 -327.800 BOTTOM

137 VDD 1834.165 -327.800 BOTTOM

138 VDD 1904.165 -327.800 BOTTOM

139 VDD 1974.165 -327.800 BOTTOM

140 VDD 2044.165 -327.800 BOTTOM

141 REG_OUT 2114.165 -327.800 BOTTOM

142 REG_OUT 2184.165 -327.800 BOTTOM

143 VCI 2254.165 -327.800 BOTTOM

144 VCI 2324.165 -327.800 BOTTOM

145 VCI 2394.165 -327.800 BOTTOM

146 VCI 2464.165 -327.800 BOTTOM

147 VCI 2534.165 -327.800 BOTTOM

148 VCI 2604.165 -327.800 BOTTOM

149 VCI 2674.165 -327.800 BOTTOM

150 VCI 2744.165 -327.800 BOTTOM

151 T8 2814.165 -327.800 BOTTOM

152 VCC 2884.165 -327.800 BOTTOM

153 VCC 2954.165 -327.800 BOTTOM

154 VCC 3024.165 -327.800 BOTTOM

155 VCC 3094.165 -327.800 BOTTOM

156 VCC 3164.165 -327.800 BOTTOM

157 VCC 3234.165 -327.800 BOTTOM

158 VDD_EN 3304.165 -327.800 BOTTOM

159 VM 3374.165 -327.800 BOTTOM

160 VM 3444.165 -327.800 BOTTOM

161 VM 3514.165 -327.800 BOTTOM

162 VM 3584.165 -327.800 BOTTOM

163 VG 3654.165 -327.800 BOTTOM

164 VG 3724.165 -327.800 BOTTOM

165 VG 3794.165 -327.800 BOTTOM

166 VG 3864.165 -327.800 BOTTOM

167 VG 3934.165 -327.800 BOTTOM

168 VG 4004.165 -327.800 BOTTOM

169 GITOR 4074.165 -327.800 BOTTOM

170 COM_PAD 4256.000 -297.000 BOTTOM

TLS8103 Datasheet


171 COM_PAD 4282.000 -297.000 BOTTOM

172 COM_PAD 4308.000 -297.000 BOTTOM

173 COM_PAD 4334.000 -297.000 BOTTOM

174 COM_PAD 4360.000 -297.000 BOTTOM

175 COM_PAD 4386.000 -297.000 BOTTOM

176 COM_PAD 4412.000 -297.000 BOTTOM

177 COM_PAD 4438.000 -297.000 BOTTOM

178 COM_PAD 4464.000 -297.000 BOTTOM

179 COM_PAD 4490.000 -297.000 BOTTOM

180 COM_PAD 4516.000 -297.000 BOTTOM

181 COM_PAD 4542.000 -297.000 BOTTOM

182 COM_PAD 4568.000 -297.000 BOTTOM

183 COM_PAD 4594.000 -297.000 BOTTOM

184 COM_PAD 4620.000 -297.000 BOTTOM

185 COM_PAD 4646.000 -297.000 BOTTOM

186 COM_PAD 4672.000 -297.000 BOTTOM

187 COM_PAD 4698.000 -297.000 BOTTOM

188 COM_PAD 4724.000 -297.000 BOTTOM

189 COM_PAD 4750.000 -297.000 BOTTOM

190 COM_PAD 4776.000 -297.000 BOTTOM

191 COM_PAD 4802.000 -297.000 BOTTOM

192 COM_PAD 4828.000 -297.000 BOTTOM

193 COM_PAD 4854.000 -297.000 BOTTOM

194 COM_PAD 4880.000 -297.000 BOTTOM

195 COM_PAD 4906.000 -297.000 BOTTOM

196 COM_PAD 4932.000 -297.000 BOTTOM

197 COM_PAD 4958.000 -297.000 BOTTOM

198 COM_PAD 4984.000 -297.000 BOTTOM

199 COM_PAD 5010.000 -297.000 BOTTOM

200 COM_PAD 5036.000 -297.000 BOTTOM

201 COM_PAD 5062.000 -297.000 BOTTOM

202 COM_PAD 5088.000 -297.000 BOTTOM

203 COM_PAD 5114.000 -297.000 BOTTOM

204 COM_PAD 5140.000 -297.000 BOTTOM

205 COM_PAD 5166.000 -297.000 BOTTOM

206 COM_PAD 5192.000 -297.000 BOTTOM

207 COM_PAD 5218.000 -297.000 BOTTOM

208 COM_PAD 5244.000 -297.000 BOTTOM

209 COM_PAD 5270.000 -297.000 BOTTOM

210 COM_PAD 5296.000 -297.000 BOTTOM

211 COM_PAD 5322.000 -297.000 BOTTOM

212 COM_PAD 5348.000 -297.000 BOTTOM

213 COM_PAD 5374.000 -297.000 BOTTOM

214 COM_PAD 5400.000 -297.000 BOTTOM

TLS8103 Datasheet


215 COM_PAD 5426.000 -297.000 BOTTOM

216 COM_PAD 5452.000 -297.000 BOTTOM

217 COM_PAD 5478.000 -297.000 BOTTOM

218 COM_PAD 5504.000 -297.000 BOTTOM

219 COM_PAD 5530.000 -297.000 BOTTOM

220 dummy_pad1 5569.000 -297.000 BOTTOM

221 dummy_pad2 5621.000 -297.000 BOTTOM

222 dummy_pad3 5616.000 -147.600 RIGHT

223 dummy_pad4 5616.000 -95.600 RIGHT

224 COM_PAD 5616.000 -56.600 RIGHT

225 COM_PAD 5616.000 -30.600 RIGHT

226 COM_PAD 5616.000 -4.600 RIGHT

227 COM_PAD 5616.000 21.400 RIGHT

228 COM_PAD 5616.000 47.400 RIGHT

229 COM_PAD 5616.000 73.400 RIGHT

230 COM_PAD 5616.000 99.400 RIGHT

231 COM_PAD 5616.000 125.400 RIGHT

232 COM_PAD 5616.000 151.400 RIGHT

233 COM_PAD 5616.000 177.400 RIGHT

234 COM_PAD 5616.000 203.400 RIGHT

235 COM_PAD 5616.000 229.400 RIGHT

236 COM_PAD 5616.000 255.400 RIGHT

237 COM_PAD 5616.000 281.400 RIGHT

238 COM_PAD 5616.000 307.400 RIGHT

239 COM_PAD 5616.000 333.400 RIGHT

240 SEG_PAD 5291.000 296.800 TOP

241 SEG_PAD 5265.000 296.800 TOP

242 SEG_PAD 5239.000 296.800 TOP

243 SEG_PAD 5213.000 296.800 TOP

244 SEG_PAD 5187.000 296.800 TOP

245 SEG_PAD 5161.000 296.800 TOP

246 SEG_PAD 5135.000 296.800 TOP

247 SEG_PAD 5109.000 296.800 TOP

248 SEG_PAD 5083.000 296.800 TOP

249 SEG_PAD 5057.000 296.800 TOP

250 SEG_PAD 5031.000 296.800 TOP

251 SEG_PAD 5005.000 296.800 TOP

252 SEG_PAD 4979.000 296.800 TOP

253 SEG_PAD 4953.000 296.800 TOP

254 SEG_PAD 4927.000 296.800 TOP

255 SEG_PAD 4901.000 296.800 TOP

256 SEG_PAD 4875.000 296.800 TOP

257 SEG_PAD 4849.000 296.800 TOP

258 SEG_PAD 4823.000 296.800 TOP

TLS8103 Datasheet


259 SEG_PAD 4797.000 296.800 TOP

260 SEG_PAD 4771.000 296.800 TOP

261 SEG_PAD 4745.000 296.800 TOP

262 SEG_PAD 4719.000 296.800 TOP

263 SEG_PAD 4693.000 296.800 TOP

264 SEG_PAD 4667.000 296.800 TOP

265 SEG_PAD 4641.000 296.800 TOP

266 SEG_PAD 4615.000 296.800 TOP

267 SEG_PAD 4589.000 296.800 TOP

268 SEG_PAD 4563.000 296.800 TOP

269 SEG_PAD 4537.000 296.800 TOP

270 SEG_PAD 4511.000 296.800 TOP

271 SEG_PAD 4485.000 296.800 TOP

272 SEG_PAD 4459.000 296.800 TOP

273 SEG_PAD 4433.000 296.800 TOP

274 SEG_PAD 4407.000 296.800 TOP

275 SEG_PAD 4381.000 296.800 TOP

276 SEG_PAD 4355.000 296.800 TOP

277 SEG_PAD 4329.000 296.800 TOP

278 SEG_PAD 4303.000 296.800 TOP

279 SEG_PAD 4277.000 296.800 TOP

280 SEG_PAD 4251.000 296.800 TOP

281 SEG_PAD 4225.000 296.800 TOP

282 SEG_PAD 4199.000 296.800 TOP

283 SEG_PAD 4173.000 296.800 TOP

284 SEG_PAD 4147.000 296.800 TOP

285 SEG_PAD 4121.000 296.800 TOP

286 SEG_PAD 4095.000 296.800 TOP

287 SEG_PAD 4069.000 296.800 TOP

288 SEG_PAD 4043.000 296.800 TOP

289 SEG_PAD 4017.000 296.800 TOP

290 SEG_PAD 3991.000 296.800 TOP

291 SEG_PAD 3965.000 296.800 TOP

292 SEG_PAD 3939.000 296.800 TOP

293 SEG_PAD 3913.000 296.800 TOP

294 SEG_PAD 3887.000 296.800 TOP

295 SEG_PAD 3861.000 296.800 TOP

296 SEG_PAD 3835.000 296.800 TOP

297 SEG_PAD 3809.000 296.800 TOP

298 SEG_PAD 3783.000 296.800 TOP

299 SEG_PAD 3757.000 296.800 TOP

300 SEG_PAD 3731.000 296.800 TOP

301 SEG_PAD 3705.000 296.800 TOP

302 SEG_PAD 3679.000 296.800 TOP

TLS8103 Datasheet


303 SEG_PAD 3653.000 296.800 TOP

304 SEG_PAD 3627.000 296.800 TOP

305 SEG_PAD 3601.000 296.800 TOP

306 SEG_PAD 3575.000 296.800 TOP

307 SEG_PAD 3549.000 296.800 TOP

308 SEG_PAD 3523.000 296.800 TOP

309 SEG_PAD 3497.000 296.800 TOP

310 SEG_PAD 3471.000 296.800 TOP

311 SEG_PAD 3445.000 296.800 TOP

312 SEG_PAD 3419.000 296.800 TOP

313 SEG_PAD 3393.000 296.800 TOP

314 SEG_PAD 3367.000 296.800 TOP

315 SEG_PAD 3341.000 296.800 TOP

316 SEG_PAD 3315.000 296.800 TOP

317 SEG_PAD 3289.000 296.800 TOP

318 SEG_PAD 3263.000 296.800 TOP

319 SEG_PAD 3237.000 296.800 TOP

320 SEG_PAD 3211.000 296.800 TOP

321 SEG_PAD 3185.000 296.800 TOP

322 SEG_PAD 3159.000 296.800 TOP

323 SEG_PAD 3133.000 296.800 TOP

324 SEG_PAD 3107.000 296.800 TOP

325 SEG_PAD 3081.000 296.800 TOP

326 SEG_PAD 3055.000 296.800 TOP

327 SEG_PAD 3029.000 296.800 TOP

328 SEG_PAD 3003.000 296.800 TOP

329 SEG_PAD 2977.000 296.800 TOP

330 SEG_PAD 2951.000 296.800 TOP

331 SEG_PAD 2925.000 296.800 TOP

332 SEG_PAD 2899.000 296.800 TOP

333 SEG_PAD 2873.000 296.800 TOP

334 SEG_PAD 2847.000 296.800 TOP

335 SEG_PAD 2821.000 296.800 TOP

336 SEG_PAD 2795.000 296.800 TOP

337 SEG_PAD 2769.000 296.800 TOP

338 SEG_PAD 2743.000 296.800 TOP

339 SEG_PAD 2717.000 296.800 TOP

340 SEG_PAD 2587.000 296.800 TOP

341 SEG_PAD 2561.000 296.800 TOP

342 SEG_PAD 2535.000 296.800 TOP

343 SEG_PAD 2509.000 296.800 TOP

344 SEG_PAD 2483.000 296.800 TOP

345 SEG_PAD 2457.000 296.800 TOP

346 SEG_PAD 2431.000 296.800 TOP

TLS8103 Datasheet


347 SEG_PAD 2405.000 296.800 TOP

348 SEG_PAD 2379.000 296.800 TOP

349 SEG_PAD 2353.000 296.800 TOP

350 SEG_PAD 2327.000 296.800 TOP

351 SEG_PAD 2301.000 296.800 TOP

352 SEG_PAD 2275.000 296.800 TOP

353 SEG_PAD 2249.000 296.800 TOP

354 SEG_PAD 2223.000 296.800 TOP

355 SEG_PAD 2197.000 296.800 TOP

356 SEG_PAD 2171.000 296.800 TOP

357 SEG_PAD 2145.000 296.800 TOP

358 SEG_PAD 2119.000 296.800 TOP

359 SEG_PAD 2093.000 296.800 TOP

360 SEG_PAD 2067.000 296.800 TOP

361 SEG_PAD 2041.000 296.800 TOP

362 SEG_PAD 2015.000 296.800 TOP

363 SEG_PAD 1989.000 296.800 TOP

364 SEG_PAD 1963.000 296.800 TOP

365 SEG_PAD 1937.000 296.800 TOP

366 SEG_PAD 1911.000 296.800 TOP

367 SEG_PAD 1885.000 296.800 TOP

368 SEG_PAD 1859.000 296.800 TOP

369 SEG_PAD 1833.000 296.800 TOP

370 SEG_PAD 1807.000 296.800 TOP

371 SEG_PAD 1781.000 296.800 TOP

372 SEG_PAD 1755.000 296.800 TOP

373 SEG_PAD 1729.000 296.800 TOP

374 SEG_PAD 1703.000 296.800 TOP

375 SEG_PAD 1677.000 296.800 TOP

376 SEG_PAD 1651.000 296.800 TOP

377 SEG_PAD 1625.000 296.800 TOP

378 SEG_PAD 1599.000 296.800 TOP

379 SEG_PAD 1573.000 296.800 TOP

380 SEG_PAD 1547.000 296.800 TOP

381 SEG_PAD 1521.000 296.800 TOP

382 SEG_PAD 1495.000 296.800 TOP

383 SEG_PAD 1469.000 296.800 TOP

384 SEG_PAD 1443.000 296.800 TOP

385 SEG_PAD 1417.000 296.800 TOP

386 SEG_PAD 1391.000 296.800 TOP

387 SEG_PAD 1365.000 296.800 TOP

388 SEG_PAD 1339.000 296.800 TOP

389 SEG_PAD 1313.000 296.800 TOP

390 SEG_PAD 1287.000 296.800 TOP

TLS8103 Datasheet


391 SEG_PAD 1261.000 296.800 TOP

392 SEG_PAD 1235.000 296.800 TOP

393 SEG_PAD 1209.000 296.800 TOP

394 SEG_PAD 1183.000 296.800 TOP

395 SEG_PAD 1157.000 296.800 TOP

396 SEG_PAD 1131.000 296.800 TOP

397 SEG_PAD 1105.000 296.800 TOP

398 SEG_PAD 1079.000 296.800 TOP

399 SEG_PAD 1053.000 296.800 TOP

400 SEG_PAD 1027.000 296.800 TOP

401 SEG_PAD 1001.000 296.800 TOP

402 SEG_PAD 975.000 296.800 TOP

403 SEG_PAD 949.000 296.800 TOP

404 SEG_PAD 923.000 296.800 TOP

405 SEG_PAD 897.000 296.800 TOP

406 SEG_PAD 871.000 296.800 TOP

407 SEG_PAD 845.000 296.800 TOP

408 SEG_PAD 819.000 296.800 TOP

409 SEG_PAD 793.000 296.800 TOP

410 SEG_PAD 767.000 296.800 TOP

411 SEG_PAD 741.000 296.800 TOP

412 SEG_PAD 715.000 296.800 TOP

413 SEG_PAD 689.000 296.800 TOP

414 SEG_PAD 663.000 296.800 TOP

415 SEG_PAD 637.000 296.800 TOP

416 SEG_PAD 611.000 296.800 TOP

417 SEG_PAD 585.000 296.800 TOP

418 SEG_PAD 559.000 296.800 TOP

419 SEG_PAD 533.000 296.800 TOP

420 SEG_PAD 507.000 296.800 TOP

421 SEG_PAD 481.000 296.800 TOP

422 SEG_PAD 455.000 296.800 TOP

423 SEG_PAD 429.000 296.800 TOP

424 SEG_PAD 403.000 296.800 TOP

425 SEG_PAD 377.000 296.800 TOP

426 SEG_PAD 351.000 296.800 TOP

427 SEG_PAD 325.000 296.800 TOP

428 SEG_PAD 299.000 296.800 TOP

429 SEG_PAD 273.000 296.800 TOP

430 SEG_PAD 247.000 296.800 TOP

431 SEG_PAD 221.000 296.800 TOP

432 SEG_PAD 195.000 296.800 TOP

433 SEG_PAD 169.000 296.800 TOP

434 SEG_PAD 143.000 296.800 TOP

TLS8103 Datasheet


435 SEG_PAD 117.000 296.800 TOP

436 SEG_PAD 91.000 296.800 TOP

437 SEG_PAD 65.000 296.800 TOP

438 SEG_PAD -65.000 296.800 TOP

439 SEG_PAD -91.000 296.800 TOP

440 SEG_PAD -117.000 296.800 TOP

441 SEG_PAD -143.000 296.800 TOP

442 SEG_PAD -169.000 296.800 TOP

443 SEG_PAD -195.000 296.800 TOP

444 SEG_PAD -221.000 296.800 TOP

445 SEG_PAD -247.000 296.800 TOP

446 SEG_PAD -273.000 296.800 TOP

447 SEG_PAD -299.000 296.800 TOP

448 SEG_PAD -325.000 296.800 TOP

449 SEG_PAD -351.000 296.800 TOP

450 SEG_PAD -377.000 296.800 TOP

451 SEG_PAD -403.000 296.800 TOP

452 SEG_PAD -429.000 296.800 TOP

453 SEG_PAD -455.000 296.800 TOP

454 SEG_PAD -481.000 296.800 TOP

455 SEG_PAD -507.000 296.800 TOP

456 SEG_PAD -533.000 296.800 TOP

457 SEG_PAD -559.000 296.800 TOP

458 SEG_PAD -585.000 296.800 TOP

459 SEG_PAD -611.000 296.800 TOP

460 SEG_PAD -637.000 296.800 TOP

461 SEG_PAD -663.000 296.800 TOP

462 SEG_PAD -689.000 296.800 TOP

463 SEG_PAD -715.000 296.800 TOP

464 SEG_PAD -741.000 296.800 TOP

465 SEG_PAD -767.000 296.800 TOP

466 SEG_PAD -793.000 296.800 TOP

467 SEG_PAD -819.000 296.800 TOP

468 SEG_PAD -845.000 296.800 TOP

469 SEG_PAD -871.000 296.800 TOP

470 SEG_PAD -897.000 296.800 TOP

471 SEG_PAD -923.000 296.800 TOP

472 SEG_PAD -949.000 296.800 TOP

473 SEG_PAD -975.000 296.800 TOP

474 SEG_PAD -1001.000 296.800 TOP

475 SEG_PAD -1027.000 296.800 TOP

476 SEG_PAD -1053.000 296.800 TOP

477 SEG_PAD -1079.000 296.800 TOP

478 SEG_PAD -1105.000 296.800 TOP

TLS8103 Datasheet


479 SEG_PAD -1131.000 296.800 TOP

480 SEG_PAD -1157.000 296.800 TOP

481 SEG_PAD -1183.000 296.800 TOP

482 SEG_PAD -1209.000 296.800 TOP

483 SEG_PAD -1235.000 296.800 TOP

484 SEG_PAD -1261.000 296.800 TOP

485 SEG_PAD -1287.000 296.800 TOP

486 SEG_PAD -1313.000 296.800 TOP

487 SEG_PAD -1339.000 296.800 TOP

488 SEG_PAD -1365.000 296.800 TOP

489 SEG_PAD -1391.000 296.800 TOP

490 SEG_PAD -1417.000 296.800 TOP

491 SEG_PAD -1443.000 296.800 TOP

492 SEG_PAD -1469.000 296.800 TOP

493 SEG_PAD -1495.000 296.800 TOP

494 SEG_PAD -1521.000 296.800 TOP

495 SEG_PAD -1547.000 296.800 TOP

496 SEG_PAD -1573.000 296.800 TOP

497 SEG_PAD -1599.000 296.800 TOP

498 SEG_PAD -1625.000 296.800 TOP

499 SEG_PAD -1651.000 296.800 TOP

500 SEG_PAD -1677.000 296.800 TOP

501 SEG_PAD -1703.000 296.800 TOP

502 SEG_PAD -1729.000 296.800 TOP

503 SEG_PAD -1755.000 296.800 TOP

504 SEG_PAD -1781.000 296.800 TOP

505 SEG_PAD -1807.000 296.800 TOP

506 SEG_PAD -1833.000 296.800 TOP

507 SEG_PAD -1859.000 296.800 TOP

508 SEG_PAD -1885.000 296.800 TOP

509 SEG_PAD -1911.000 296.800 TOP

510 SEG_PAD -1937.000 296.800 TOP

511 SEG_PAD -1963.000 296.800 TOP

512 SEG_PAD -1989.000 296.800 TOP

513 SEG_PAD -2015.000 296.800 TOP

514 SEG_PAD -2041.000 296.800 TOP

515 SEG_PAD -2067.000 296.800 TOP

516 SEG_PAD -2093.000 296.800 TOP

517 SEG_PAD -2119.000 296.800 TOP

518 SEG_PAD -2145.000 296.800 TOP

519 SEG_PAD -2171.000 296.800 TOP

520 SEG_PAD -2197.000 296.800 TOP

521 SEG_PAD -2223.000 296.800 TOP

522 SEG_PAD -2249.000 296.800 TOP

TLS8103 Datasheet


523 SEG_PAD -2275.000 296.800 TOP

524 SEG_PAD -2301.000 296.800 TOP

525 SEG_PAD -2327.000 296.800 TOP

526 SEG_PAD -2353.000 296.800 TOP

527 SEG_PAD -2379.000 296.800 TOP

528 SEG_PAD -2405.000 296.800 TOP

529 SEG_PAD -2431.000 296.800 TOP

530 SEG_PAD -2457.000 296.800 TOP

531 SEG_PAD -2483.000 296.800 TOP

532 SEG_PAD -2509.000 296.800 TOP

533 SEG_PAD -2535.000 296.800 TOP

534 SEG_PAD -2561.000 296.800 TOP

535 SEG_PAD -2587.000 296.800 TOP

536 SEG_PAD -2717.000 296.800 TOP

537 SEG_PAD -2743.000 296.800 TOP

538 SEG_PAD -2769.000 296.800 TOP

539 SEG_PAD -2795.000 296.800 TOP

540 SEG_PAD -2821.000 296.800 TOP

541 SEG_PAD -2847.000 296.800 TOP

542 SEG_PAD -2873.000 296.800 TOP

543 SEG_PAD -2899.000 296.800 TOP

544 SEG_PAD -2925.000 296.800 TOP

545 SEG_PAD -2951.000 296.800 TOP

546 SEG_PAD -2977.000 296.800 TOP

547 SEG_PAD -3003.000 296.800 TOP

548 SEG_PAD -3029.000 296.800 TOP

549 SEG_PAD -3055.000 296.800 TOP

550 SEG_PAD -3081.000 296.800 TOP

551 SEG_PAD -3107.000 296.800 TOP

552 SEG_PAD -3133.000 296.800 TOP

553 SEG_PAD -3159.000 296.800 TOP

554 SEG_PAD -3185.000 296.800 TOP

555 SEG_PAD -3211.000 296.800 TOP

556 SEG_PAD -3237.000 296.800 TOP

557 SEG_PAD -3263.000 296.800 TOP

558 SEG_PAD -3289.000 296.800 TOP

559 SEG_PAD -3315.000 296.800 TOP

560 SEG_PAD -3341.000 296.800 TOP

561 SEG_PAD -3367.000 296.800 TOP

562 SEG_PAD -3393.000 296.800 TOP

563 SEG_PAD -3419.000 296.800 TOP

564 SEG_PAD -3445.000 296.800 TOP

565 SEG_PAD -3471.000 296.800 TOP

566 SEG_PAD -3497.000 296.800 TOP

TLS8103 Datasheet


567 SEG_PAD -3523.000 296.800 TOP

568 SEG_PAD -3549.000 296.800 TOP

569 SEG_PAD -3575.000 296.800 TOP

570 SEG_PAD -3601.000 296.800 TOP

571 SEG_PAD -3627.000 296.800 TOP

572 SEG_PAD -3653.000 296.800 TOP

573 SEG_PAD -3679.000 296.800 TOP

574 SEG_PAD -3705.000 296.800 TOP

575 SEG_PAD -3731.000 296.800 TOP

576 SEG_PAD -3757.000 296.800 TOP

577 SEG_PAD -3783.000 296.800 TOP

578 SEG_PAD -3809.000 296.800 TOP

579 SEG_PAD -3835.000 296.800 TOP

580 SEG_PAD -3861.000 296.800 TOP

581 SEG_PAD -3887.000 296.800 TOP

582 SEG_PAD -3913.000 296.800 TOP

583 SEG_PAD -3939.000 296.800 TOP

584 SEG_PAD -3965.000 296.800 TOP

585 SEG_PAD -3991.000 296.800 TOP

586 SEG_PAD -4017.000 296.800 TOP

587 SEG_PAD -4043.000 296.800 TOP

588 SEG_PAD -4069.000 296.800 TOP

589 SEG_PAD -4095.000 296.800 TOP

590 SEG_PAD -4121.000 296.800 TOP

591 SEG_PAD -4147.000 296.800 TOP

592 SEG_PAD -4173.000 296.800 TOP

593 SEG_PAD -4199.000 296.800 TOP

594 SEG_PAD -4225.000 296.800 TOP

595 SEG_PAD -4251.000 296.800 TOP

596 SEG_PAD -4277.000 296.800 TOP

597 SEG_PAD -4303.000 296.800 TOP

598 SEG_PAD -4329.000 296.800 TOP

599 SEG_PAD -4355.000 296.800 TOP

600 SEG_PAD -4381.000 296.800 TOP

601 SEG_PAD -4407.000 296.800 TOP

602 SEG_PAD -4433.000 296.800 TOP

603 SEG_PAD -4459.000 296.800 TOP

604 SEG_PAD -4485.000 296.800 TOP

605 SEG_PAD -4511.000 296.800 TOP

606 SEG_PAD -4537.000 296.800 TOP

607 SEG_PAD -4563.000 296.800 TOP

608 SEG_PAD -4589.000 296.800 TOP

609 SEG_PAD -4615.000 296.800 TOP

610 SEG_PAD -4641.000 296.800 TOP

TLS8103 Datasheet


611 SEG_PAD -4667.000 296.800 TOP

612 SEG_PAD -4693.000 296.800 TOP

613 SEG_PAD -4719.000 296.800 TOP

614 SEG_PAD -4745.000 296.800 TOP

615 SEG_PAD -4771.000 296.800 TOP

616 SEG_PAD -4797.000 296.800 TOP

617 SEG_PAD -4823.000 296.800 TOP

618 SEG_PAD -4849.000 296.800 TOP

619 SEG_PAD -4875.000 296.800 TOP

620 SEG_PAD -4901.000 296.800 TOP

621 SEG_PAD -4927.000 296.800 TOP

622 SEG_PAD -4953.000 296.800 TOP

623 SEG_PAD -4979.000 296.800 TOP

624 SEG_PAD -5005.000 296.800 TOP

625 SEG_PAD -5031.000 296.800 TOP

626 SEG_PAD -5057.000 296.800 TOP

627 SEG_PAD -5083.000 296.800 TOP

628 SEG_PAD -5109.000 296.800 TOP

629 SEG_PAD -5135.000 296.800 TOP

630 SEG_PAD -5161.000 296.800 TOP

631 SEG_PAD -5187.000 296.800 TOP

632 SEG_PAD -5213.000 296.800 TOP

633 SEG_PAD -5239.000 296.800 TOP

634 SEG_PAD -5265.000 296.800 TOP

635 SEG_PAD -5291.000 296.800 TOP

636 COM_PAD -5616.000 333.400 LEFT

637 COM_PAD -5616.000 307.400 LEFT

638 COM_PAD -5616.000 281.400 LEFT

639 COM_PAD -5616.000 255.400 LEFT

640 COM_PAD -5616.000 229.400 LEFT

641 COM_PAD -5616.000 203.400 LEFT

642 COM_PAD -5616.000 177.400 LEFT

643 COM_PAD -5616.000 151.400 LEFT

644 COM_PAD -5616.000 125.400 LEFT

645 COM_PAD -5616.000 99.400 LEFT

646 COM_PAD -5616.000 73.400 LEFT

647 COM_PAD -5616.000 47.400 LEFT

648 COM_PAD -5616.000 21.400 LEFT

649 COM_PAD -5616.000 -4.600 LEFT

650 COM_PAD -5616.000 -30.600 LEFT

651 COM_PAD -5616.000 -56.600 LEFT

652 dummy_pad5 -5616.000 -95.600 LEFT

653 dummy_pad6 -5616.000 -147.600 LEFT

TLS8103 Datasheet


PIN DESCRIPTION

Table3 TLS8103 PIN function description table

Name I/O Description No. of PinsPower Supply Pins

VCC Power Supply

Power supply for internal logic power regulator. When use internal logic power regulator, VCC can be connected to 2.5V~3.3V; When use external logic power supply, VCC must be connected with a voltage supply > VDD. For a typical connection, when use internal logic power regulator, VCC can be connected together with VCI, and REG_OUT, VDD, are connected together; when use external logic power supply, VCC can be connected together with VCI.

VDDIO Power Supply Power supply for digital I/O circuits. VDD

TLS8103 Datasheet


When the internal power circuit is active, the three voltage are generated as V0-Vm = Vm-XV0, and Vm = (1/N) x V0. N is the LCD bias.

Please connect a capacitor between V0 and XV0 for their driving stability, and connect a capacitor between Vm and system ground for Vm driving stability.

Vg Power Supply

Power supply for LCD SEG driving circuit. When the internal power circuit is active, the Vg voltage are generated as Vg = 2 * Vm.

Please connect a capacitor between Vg and system ground for Vg driving stability.

VPP Power Supply

MTP programming voltage supply. Left this pin open when normal function.

MPU Interface I/O Pins

D/C (SCK)

I

This pin is used to indicate that whether the data bus is data or command when parallel interface. D/C = “H”: D7 – D0 are data. D/C = “L”: D7 – D0 are command.

It is also used as Serial Clock (SCK) when serial interface.

1

/RES I This is the reset pin. When this pin is set to “L”, the system registers are set to the initialized status. Refer to the descriptions of Reset Circuits.

1

/CS I These are the chip select pins. The chip is set to active when /CS= “L”. 1

E (/RD) I

This pin is the enable indicator (6800 interface mode) or the read operation indicator (8080 interface mode).

For 6800 series interface applications: This is the E pin. Setting E = “H” indicates a write/read operation.

For 8080 series interface applications: This is the /RD pin. Setting /RD = “L” indicates the read operation and the data bus can be read by MPU.

When using serial interface, this pin should be fixed to “H” or “L”.

1

TLS8103 Datasheet


R/W (/WR) I

This pin is the read/write indicator (6800 interface mode) or write operation indicator (8080 interface mode).

For 6800 series interface applications:

This is the R/W pin. Setting R/W = “H” indicates a read operation (MPU can read data from the data bus) while setting R/W = “L” indicates the write.

For 8080 series interface applications: This is the /WR pin. Setting /WR = “L” indicates the write operation.

When use serial interface, this pin should be fixed to “H” or “L”.

1

D7, D6, D5, D4, D3, D2, D1, D0

I/O

When parallel interface, D7-D0 are the data bus for write and read operation; when serial interface, D0 and D1 are used as Serial Data bus and D/C Control Signals.

1. In serial interface, D0 is used as SDA, the serial data bus signal.

2. In 4-lines serial interface, D1 is used as command/data indicator signal (D/C).

3. In serial interface, the unused pins of D7-D0 are in state of high impedance, should be connected with “H” or “L” or be floating.

8

Configuration Pins

PS2, PS1, PS0

I

PS2 PS1 PS0 State L H L 3 wire-SPI MPU Interface

L H H 4 wire-SPI MPU Interface

H L L 6800-series 8 bits parallel MPU interface

H H L 8080-series 8 bits parallel MPU interface

These pins should be fixed to proper “H” or “L”.

3

CL I

External clock source for test purpose. When CLS = H, TLS8103 use internal clock oscillator, leave CL pin floating; when CLS = L, TLS8103 use external clock, connect CL to external clock source.

Please be noted that CL only for test purpose, for normal LCM design, please connect CLS = H and leave CL floating or connect CL with “L”.

1

CLS I/O

When CLS = H, TLS8103 use internal clock oscillator, leave CL pin floating; when CLS = L, TLS8103 use external clock, connect CL to external clock source.

1

TLS8103 Datasheet


CSEL I

CSEL = L, COM0~65 is in one side, COM66~131 is in the opposite side. And it can be set to ‘L’ only.

1

TE I Frame sync output for tear affection. Please leave it open when don’t use this function 1

LCD Driver Pins

SEG0 – SEG395 O

LCD segment driver outputs. This display data and the M signal control the output voltage of segment driver.

Segment driver output voltage Display data

M (internal) Normal display Reverse display

H H Vg VSS H L VSS Vg L H VSS Vg L L Vg VSS Sleep-in mode VSS VSS

396

COM0 – COM131 O

LCD column driver outputs This internal scanning data and M signal control the output voltage of common driver.

Common driver output voltage Display data

M (internal) Normal display Reverse display

H H XV0 H L V0 L H Vm L L Vm

Power save mode VSS

132

Test Pins

T1- T8 I/O Test pins, should be left open. 8

GITOL/ GITOR I/O

GITOL should be connected with GITOR by ITO which run a ring on LCM glass. The TLS8103 can use these two pins and the ITO ring to improve ESD capability. Please leave these two pins open when don’t use this function.

2

TLS8103 Datasheet


ITO requirements

Table4 TLS8103 ITO series resistor requirements

Name Type Maximum Series Resistors (Ω) VCC Power supply 50 VDDIO Power supply 30 REG_OUT Power supply 50 VDD Power supply 20 VCI Power supply 30 GND Power supply 30 VSS Power supply 30 LCDVSS Power supply 20 VPP Power supply 50 V0 Capacitor connection 100 XV0 Capacitor connection 100 Vg Capacitor connection 100 Vm Capacitor connection 100 PS2, PS1, PS0, CLS, CSEL

Input 1000

/RES Input 200 D/C(SCK) Input 200 /CS Input 200 E(/RD) Input 200 R/W(/WR) Input 200 D7~D0 Inout 200 TE Output 200 CL Input 200

TLS8103 Datasheet


BLOCK DIAGRAM

Figure 2 TLS8103 block Diagram

TLS8103 Datasheet


FUNCTION DESCRIPTIONS

MICROPROCESSOR INTERFACE Chip Select Input

CS pin is chip selection. The TLS8103 is active when CS=L. In serial interface mode, the internal shift

register and the counter are reset when CS=H. Selecting Parallel / Serial Interface

TLS8103 has four types of interfaces with an MPU, which are two serial and two parallel interfaces. These parallel or serial interfaces are determined by PS pin as shown in Table 5.

Table5 Parallel/Serial interface mode selection

PS2 PS1 PS0 State L H L 3 wire-SPI MPU Interface

L H H 4 wire-SPI MPU Interface

H L L 6800-series 8 bits parallel MPU interface

H H L 8080-series 8 bits parallel MPU interface

8-bit Parallel Interface

The TLS8103 identifies the type of the data bus signals according to the combination of D/C, E and R/W signals, as shown in Table 6.

Table6 Parallel data transfer mode selection

common 6800-series 8080-series D/C R/W E WR RD Description

H H ↑ H ↓ Display data read out H H ↑ H ↓ Register status read L L ↓ ↑ H Instruction write H L ↓ ↑ H Display data write

8- and 9-bit Serial Interface

The 8-bit serial interface uses four pins CS, SDA, SCK, and D/C to write in commands and data. Meanwhile, the 9-bit serial interface uses three pins CS, SDA and SCK for the same purpose.

Data read is not available in the serial interface. Data must write to IC with 8 bits for each time. The relation between gray-scale data and data bus in the serial input is the same as that in the 8-bit parallel interface mode at every gradation.

TLS8103 Datasheet


(1) 8-bit serial interface (4-line) When entering data (parameters): D/C= HIGH at the rising edge of the 8th SCK.

When entering command: D/C= LOW at the rising edge of the 8th SCK

When entering reading command:

Figure3 4 lines 8 bits serial interface

TLS8103 Datasheet


(2) 9-bit serial interface (3-line) When entering data (parameters): SDA= HIGH at the rising edge of the 1st SCK

When entering command: SDA= LOW at the rising edge of the 1st SCK

When entering reading command:

Figure4 3 lines 9 bits serial interface

If CS is set to HIGH while the 8 bits from D7 to D0 are entered, the data concerned is invalidated. Before entering succeeding sets of data, you must correctly input the data concerned again.

In order to avoid data transfer error due to incoming noise, it is recommended to set CS at HIGH on byte basis to initialize the serial-to-parallel conversion counter and the register.

TLS8103 Datasheet


8-bit and 9-bit Serial Interface Data Color Coding 8-bit serial interface (4-line) (1) R 3-bit, G 3-bit, B 2-bit, 256 colors There is 1 pixel (1 pixel = 3 sub-pixels ) per byte.

Figure5 8 bits serial interface 256 colors data format

(2) R 4-bit, G 4-bit, B 4-bit, 4,096 colors — Type A There are 2 pixel ( 1 pixel = 3 sub-pixels ) per 3 byte.

Figure6 8 bits serial interface 4096 colors data format TYPE A

TLS8103 Datasheet


(3) R 4-bit, G 4-bit, B 4-bit, 4,096 colors — Type B There is 1 pixel (1 pixel = 3 sub-pixels ) per 2 bytes.

Figure7 8 bits serial interface 4096 colors data format TYPE B

(4) R 5-bit, G 6-bit, B 5-bit, 65,536 colors There is 1 pixel (1 pixel = 3 sub-pixels ) per 2 byte.

Figure8 8 bits serial interface 65K colors data format

TLS8103 Datasheet


(5) R 6-bit, G 6-bit, B 6-bit, 262K colors There is 1 pixel (1 pixel = 3 sub-pixels ) per 3 byte.


(6) R 8-bit, G 8-bit, B 8-bit, 16M colors There is 1 pixel (1 pixel = 3 sub-pixels ) per 3 byte.

Figure10 8 bits serial interface 16M colors data format

TLS8103 Datasheet


9-bit serial interface (3-line) (1) R 3-bit, G 3-bit, B 2-bit, 256 colors There is 1 pixel (1 pixel = 3 sub-pixels ) per byte.

Figure11 9 bits serial interface 256 colors data format

(2) R 4-bit, G 4-bit, B 4-bit, 4,096 colors – Type A There are 2 pixel (1 pixel = 3 sub-pixels ) per 3 byte.

Figure12 9 bits serial interface 4096 colors data format TYPE A

TLS8103 Datasheet


(3) R 4-bit, G 4-bit, B 4-bit, 4,096 colors – Type B There is 1 pixel (1 pixel = 3 sub-pixels ) per 2 bytes.

Figure13 9 bits serial interface 4096 colors data format TYPE B

(4) R 5-bit, G 6-bit, B 5-bit, 65,536 colors There is 1 pixel (1 pixel = 3 sub-pixels ) per 2 byte.


TLS8103 Datasheet


(5) R 6-bit, G 6-bit, B 6-bit, 262K colors There is 1 pixel (1 pixel = 3 sub-pixels ) per 3 byte.


(6) R 8-bit, G 8-bit, B 8-bit, 16M colors There is 1 pixel (1 pixel = 3 sub-pixels ) per 3 byte.

Figure16 9 bits serial interface 16M colors data format

TLS8103 Datasheet


ACCESS TO DDRAM AND INTERNAL REGISTERS TLS8103 realizes high-speed data transfer because the access from MPU is a sort of pipeline processing done via the bus holder attached to the internal, requiring the cycle time alone without needing the wait time. For example, when MPU writes data to the DDRAM, the data is once held by the bus holder and then written to the DDRAM before the succeeding write cycle is started. When MPU reads data from the DDRAM, the first read cycle is dummy and the bus holder holds the data read in the dummy cycle, and then it read from the bus holder to the system bus in the succeeding read cycle.

Figure17 Parallel interface pipeline data access DISPLAY DATA RAM (DDRAM) DDRAM It is 132 X 132 X 16 bits capacity RAM prepared for storing dot data. Refer to the following memory map for the RAM configuration. You can change position of R and B with MADCTR command.

TLS8103 Datasheet


Address Control The address counter sets the addresses of the display data RAM for writing. Data is written into the pixel RAM matrix of TLS8103. The data for one pixel or two pixels is collected (RGB 565 bit), according to the data formats. As soon as this pixel-data information is complete, the “Write access” is activated on the RAM. The locations of RAM are addressed by the address pointers. The address ranges are X=0 to X=131 (83h) and Y=0 to Y=131 (83h). Addresses outside these ranges are not allowed. Before writing to the RAM, a window must be defined into which will be written. The window is programmable via the command registers. XS, YS designating the start address and XE, YE designating the end address. For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h) and XE=131 (83h), YE=131 (83h). In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps around to YS and X increments to address the next column. In horizontal addressing mode (MV=0), the X-address increments after each byte, after the last X-address (X=XE), X wraps around to XS and Y increments to address the next row. After the every last address (X=XE and Y=YE), the address pointers wrap around to address (X=XS and Y=YS). For flexibility in handling a wide variety of display architectures, the commands “CASET, RASET” and “MADCTR”, define flags MX and MY, which allows mirroring of the X-address and Y-address. All combinations of flags are allowed. For each image condition, the controls for the column and row counters apply as below:

TLS8103 Datasheet


TLS8103 Datasheet


I/O Buffer Circuit It is the bi-directional buffer used when MPU reads or writes the DDRAM. Since MPU’s read or write of DDRAM is performed independently from data output to the display data latch circuit, asynchronous access to the DDRAM when the LCD is turned on does not cause troubles such as flicking of the display images. Scroll Address Circuit The circuit associates lines on DDRAM with COM output. TLS8103 processes signals for the liquid crystal display on 1-line basis. Thus, when specifying a specific area in the area scroll display or partial display, you must designate it in line. Display data Latch Circuit This circuit is used to temporarily hold display data to be output from the DDRAM to the SEG decoder circuit. Since display normal/inverse and display on/off commands are used to control data in the latch circuit alone, they do not modify data in the DDRAM. Normal Display On or Partial Mode On, Vertical Scroll Off In this mode, contents of the frame memory within an area where column address is 00h to 83h and row address is 00h to 83h is displayed. To display a dot on leftmost top corner, store the dot data at (column address, row address) = (0,0). Example1) Normal Display On

Example2) Partial Display On: PSL[6:0] = 04h, PEL[6:0] = 80h

TLS8103 Datasheet


Vertical Scroll/Rolling Scroll Rolling Scroll

There is just one types of vertical scrolling, which are determined by the commands “Vertical Scrolling Definition” (33h) and “Vertical Scrolling Start Address” (37h).

When Vertical Scrolling Definition Parameters (TFA+VSA+BFA) =132. In this case, ‘rolling’ scrolling is applied as shown below. All the memory contents will be used. Example)

Panel size=132 x 132, TFA =3, VSA=127, BFA=2, SSA=4: Rolling Scroll

TLS8103 Datasheet


Vertical Scroll Example There are 2 types of vertical scrolling, which are determined by the commands “ Vertical Scrolling Definition” (33h) and Vertical Scrolling Start Address” (37h). Case 1: TFA + VSA + BFA

TLS8103 Datasheet


Case3: TFA + VSA + BFA =132 (Scrolling with 2line buffer) Example) TFA=20, VSA=82, BFA=30 and VSCSAD=60.

Tearing Effect Output Line The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled by the Tearing Effect Line Off & On commands. The signal can be used by the MPU to synchronize Frame Memory Writing when displaying video images. Tearing Effect Line Modes Mode 1, the Tearing Effect Output signal consists of V-Sync (Tvhd) information only before Super-frame’s start (only during every 4th frame and every 4th field). tvdh = The LCD display is updating the end (4th frame) of the previous Super-frame from the Frame memory tvdl = The LCD display is updated 1st, 2nd and 3rd frames (It is possible that the begin of the 4th frame is also included for this timing) from the Frame Memory. Mode 2, the Tearing Effect Output signal consists of only H-Sync (1 frame) information, there is one high pulse and 1 low pulse during every frame. thdh = The LCD display is updated the end of the frame field from the Frame Memory. thdl = The LCD display is updated the begin of the frame field from the Frame Memory.

TLS8103 Datasheet


Note: During Sleep In Mode, the Tearing Effect Output Pin is active Low. Tearing Effect Line Timing The Tearing Effect signal is described below:

Figure18 Tear affection timing diagram

AC characteristics of Tearing Effect Signal Idle Mode Off (Frame Rate = 100Hz)

Symbol Parameter Min Max unit description

VDLt Vertical Timing Low Duration 37.5 ms

VDHt Vertical Timing High Duration 2.5 ms Mode1

HDLt Horizontal Timing Low Duration 7.5 ms

HDHt Horizontal Timing High Duration 2.5 ms Mode2

NOTE: The timings in Table 5.2.5 apply when MADCTL B4=0 and B4=1 . The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.

TLS8103 Datasheet


Oscillation circuit This is on-chip oscillator without external resistor. When the internal oscillator is used, CLS must connect to VDD; when the external oscillator is used, CL could be input pin. This oscillator signal is used in the voltage converter and display timing generation circuit. Display Timing Generator Circuit This circuit generates some signals to be used for displaying LCD. The display clock CL (internal), which is generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock and the display data latch circuit latches the 132-bits display data in synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (M), which enables the LCD driver to make an AC drive waveform, and also generates an internal common timing signal and start signal to the common driver. The frame signal or the line signal changes the M by setting internal instruction. Power Levels 6 level modes are defined they are in order of Maximum Power consumption to Minimum Power Consumption: 1. Normal Mode On (full display), Idle Mode Off, Sleep Out: In this mode, the display is able to show maximum 65K colors. 2. Partial Mode On, Idle Mode Off, Sleep Out: In this mode part of the display is used with maximum 65K colors. 3. Normal Mode On (full display), Idle Mode On, Sleep Out: In this mode, the full display area is used but with 8 colors. 4. Partial Mode On, Idle Mode On, Sleep Out: In this mode, part of the display is used but with 8 colors. 5. Sleep In Mode: In this mode, the DC-DC converter, internal oscillator and panel driver circuit are stopped. Only the MCU interface and memory works with Digital VDD power supply. Contents of the memory are safe. 6. Power Off Mode: In this mode, both Analog and Digital power supplies are removed. Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only when both Power supplies are removed.

TLS8103 Datasheet


POWER FLOW CHART FOR DIFFERENT POWER MODES

Figure19 TLS8103 Power modes

Note 1: There is not any abnormal visual effect when there is changing from one power mode to another power

mode. 2: There is not any limitation, which is not specified by this spec, when there is changing from one power

mode to another power mode. Liquid Crystal Driver Power Circuit The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are controlled by power control instruction. For details, refers to "Instruction Description". Figure3 shows the referenced combinations in using Power Supply circuits.

TLS8103 Datasheet


Figure20 TLS8103 LCD Power circuits Voltage Regulator Circuits There is a built-in voltage regulator circuits in TLS8103 for generating V0. After internal voltage is regulated by voltage regulator circuit, V0 is generated. Detail explanation of V0 set is listed below: SET V0 (Temperatue = 24°C)

V0=a+{Vop[8:0] + (EV[6:0]-3Fh)}*b (V) Example: Vop[8:0]=011010010 EV[6:0]=0111111 V0=3.6 + { 210 + (63-63) } *0.04 =12 (V)

● a is a fixed constant value ( a=3.6V ). ● b is a fixed constant value ( b=0.04V ). ● Vop [8:0] is the programmed VOP value. The programming range for Vop[8:0] is 0 to 410 (19Ahex). ● The range of contrast is 128 steps for MTP to fine tune VOP.

The Vop [8:0] value must be in the V0 programming range as given in Figure 4. Evaluating V0 equation, values outside the programming range indicated in many result. Resulting Vop[8:0] values higher than 410 will be mapped to Vop[8:0] = 410. At room temperature (24°C), we suggests V0 range equals 3.6V to 18V.

TLS8103 Datasheet


Figure21 TLS8103 LCD Voltage Regulator setting

As the programming range for the internally generated V0 voltage is above the limited V0 (20V), users has to

ensure while selecting the temperature compensation that under all conditions and including all tolerances that the V0 voltage remains below 18V. SET V0 with temperature compensation (Temperature ≠ 24℃)

There are 16-line slope in each temperature steps and customer can select one line slope of temperature compensation coefficiency for each temperature step. Each temperature step is 8°C. Please see Figure 5 as below.

Figure22 TLS8103 LCD temperature compensation curve setting

TLS8103 Datasheet


In command TEMPSEL, each MTx, where x=0, 1, 2,…, E, F, has a value between 0 and 15. MTx= 0 results

in 0V increment on V0, MTx = 1 results in Mx=5mV increment, …, MTx = 15 results in Mx=15x5mV=75mV increment. Note that each MTx individually corresponds to a temperature interval; The relations between Mx and V0 quantity due to temperature V0(T) are described in the equations shown as follows:

Temperature range Equation V0(V) at temperature=T℃

-40℃ ≦ T ＜ -32℃ V0(T) = V0(T24)+ (-32-T)．M0 +( M1 + M2 + M3 + M4 + M5 + M6 + M7)．8 -32℃ ≦ T ＜ -24℃ V0(T) = V0(T24)+ (-24-T)．M1 +( M2 + M3 + M4 + M5 + M6 + M7)．8 -24℃ ≦ T ＜ -16℃ V0(T) = V0(T24)+ (-16-T)．M2 +( M3 + M4 + M5 + M6 + M7)．8 -16℃ ≦ T ＜ -8℃ V0(T) = V0(T24)+ (-8-T)．M3 +( M4 + M5 + M6 + M7)．8 -8℃ ≦ T ＜ 0℃ V0(T) = V0(T24)+ (0-T)．M4 +( M5 + M6 + M7)．8 0℃ ≦ T ＜ 8℃ V0(T) = V0(T24)+ (8-T)．M5 +( M6 + M7)．8

8℃ ≦ T ＜ 16℃ V0(T) = V0(T24)+ (16-T)．M6 + M7．8 16℃ ≦ T ＜ 24℃ V0(T) = V0(T24)+ (24-T)．M7 24℃ ≦ T ＜ 32℃ V0(T) = V0(T24)－(T-24)．M8 32℃ ≦ T ＜ 40℃ V0(T) = V0(T24)－(T-32)．M9－M8．8 40℃ ≦ T ＜ 48℃ V0(T) = V0(T24)－(T-40)．M10－(M9 + M8 )．8 48℃ ≦ T ＜ 56℃ V0(T) = V0(T24)－(T-48)．M11－(M10 + M9 + M8 )．8 56℃ ≦ T ＜ 64℃ V0(T) = V0(T24)－(T-56)．M12－(M11 + M10 + M9 + M8 )．8 64℃ ≦ T ＜ 72℃ V0(T) = V0(T24)－(T-64)．M13－(M12 + M11 + M10 + M9 + M8 )．8 72℃ ≦ T ＜ 80℃ V0(T) = V0(T24)－(T-72)．M14－(M13 + M12 + M11 + M10 + M9 + M8 )．8 80℃ ≦ T ＜ 88℃ V0(T) = V0(T24)－(T-80)．M15－( M14 + M13 + M12 + M11 + M10 + M9 + M8 )．8

Figure23 TLS8103 LCD temperature compensation curve setting

V0 fine tuning

TLS8103 has 2 commands for fine tuning V0. These commands are VopOfsetInc and VopOfsetDec. When

writing VopOfsetInc into IC for each time, V0 would increase 40mV; when writing VopOfsetDec into IC for each time, V0 would decrease 40mV.

TLS8103 Datasheet


Example: Vop[8:0]=011010010 EV[6:0]=0111111 VopOfsetInc x2 → V0=3.6 + { 210 + (63-63) } *0.04 + 0.04*2 =12.08 (V)

Voltage Follower Circuits

There is a build-in voltage follower circuits in TLS8103 for generating Vg and Vm. These voltages are decided by bias ratio selection circuitry which is set by users with software to control 1/5 to 1/12 bias ratios to match the optimum display performance of LCD panel. Bias driving rule is listed below:

LCD bias Vg Vm 1/N bias (2/N)*V0 (1/N)*V0

N=5~12

MTP Setting Flow

TLS8103 provides the Write and Read function to write the electronic control value and built-in resistance ratio into built-in MTP, and then read them from it. Using the Write and Read functions, you can store these values appropriate to each LCD panel. This function is very convenient for user in setting from some different panel’s voltage. But using this function must attention the setting procedure. Please see the following diagram.

Note1: This setting flow is used for LCM assembler. Note2: MTP shouldn’t be written without preceding loading correctly from MTP in order to avoid

some errors during IC operation. Note3: When writing value to MTP, the voltage of VPP must be more than 7.5V; the current of

Ivpp must be more than 4 mA. Note4: If the MTP is exposed to a high temperature for hours, data in the memory cell may

probably be lost before the data retention guarantee period. To retain data in the memory cell, keep the memory cell below 90℃. The data retention guarantee period is specified including the retention period.

Frquency Temperature Gradient Compensation Coefficient

TLS8103 will auto-switch frame rate on different temperature such as Figure 6. TA,TB and TC are frame rate

switching temperatures which can be defined by customer with command TMPRNG. FA, FB, FC and FD are switched frame rate which also can be defined by customer with command FRMSEL . The frame rate range is from 37.5Hz to 170Hz.

When the temperature is in increasing state, frame rate changes to the higher step at TA/TB/TC+TH(℃). When the temperature is in decreasing state, frame rate changes to the lower step at TA/TB/TC. For example:

TLS8103 Datasheet


TC=10℃ and TH=5℃, FC switches to FD at 15 ℃ but FD switches to FC at 10℃. Please take Figure 6 for reference.

Figure24 TLS8103 LCD auto-adjustment with 4 temperature ranges

TLS8103 Datasheet


COMMAND TABLE

Hex command D/C

RD WR D7 D6 D5 D4 D3 D2 D1 D0 Function Ref

(00H) NOP 0 1 0 0 0 0 0 0 0 0 0 No operation 1 (01H) SWRESET 0 1 0 0 0 0 0 0 0 0 1 Software reset 2 (04H) RDDID 0 1 0 0 0 0 0 0 1 0 0 Read display ID

1 0 1 - - - - - - - - Dummy read 1 0 1 ID

17 ID16

ID15

ID14

ID13

ID12

ID11

ID10

ID1 read (D23-D16)

1 0 1 ID 27

ID26

ID25

ID24

ID23

ID22

ID21

ID20

ID2 read (D15-D8)

1 0 1 ID37

ID36

ID35

ID34

ID33

ID32

ID31

ID30

ID3 read (D7-D0)

3

(09H) RDDST 0 1 0 0 0 0 0 1 0 0 1 Read display status 1 0 1 - - - - - - - - Dummy read 1 0 1 ST

31 ST30

ST29

ST28

ST27

ST26

ST25

ST24

(D31-D24)

1 0 1 ST23

ST22

ST21

ST20

ST19

ST18

ST17

ST16

(D23-D16)

1 0 1 ST15

ST14

ST13

ST12

ST11

ST10

ST9

ST8

(D15-D8)

1 0 1 ST7

ST6

ST5

ST4

ST3

ST2

ST1

ST0

(D7-D0)

4

(0AH) RDDPM 0 1 0 0 0 0 0 1 0 1 0 Read display power mode

1 0 1 - - - - - - - - Dummy read 1 0 1 D7 D6 D5 D4 D3 D2 0 0

5

(0BH) RDDMADCTR 0 1 0 0 0 0 0 1 0 1 1 Read display MADCTR1 0 1 - - - - - - - - Dummy read 1 0 1 D7 D6 D5 D4 D3 0 0 0

6

(0CH) RDDCOLMOD 0 1 0 0 0 0 0 1 1 0 0 Read display pixel format

1 0 1 - - - - - - - - Dummy read 1 0 1 0 0 0 0 0 D2 D1 D0

7

(0DH) RDDIM 0 1 0 0 0 0 0 1 1 0 1 Read display image mode

1 0 1 - - - - - - - - Dummy read 1 0 1 D7 0 D5 D4 D3 0 0 0

8

(0EH) RDDSM 0 1 0 0 0 0 0 1 1 1 0 Read display signal mode

1 0 1 - - - - - - - - Dummy read 1 0 1 D7 D6 0 0 0 0 0 0

9

(10H) SLPIN 0 1 0 0 0 0 1 0 0 0 0 Sleep in 10 (11H) SLPOUT 0 1 0 0 0 0 1 0 0 0 1 Sleep out 11 (12H) PTLON 0 1 0 0 0 0 1 0 0 1 0 Partial mode on 12 (13H) NORON 0 1 0 0 0 0 1 0 0 1 1 Partial off 13 (20H) INVOFF 0 1 0 0 0 1 0 0 0 0 0 Display inversion off 14 (21H) INVON 0 1 0 0 0 1 0 0 0 0 1 Display inversion on 15 (22H) APOFF 0 1 0 0 0 1 0 0 0 1 0 All pixel off 16 (23H) APON 0 1 0 0 0 1 0 0 0 1 1 All pixel on 17 (25H) WRCNTR 0 1 0 0 0 1 0 0 1 0 1 Write contrast 1 1 0 0 EV

6 EV5

EV4

EV3

EV2

EV1

EV0

EV=0 to 127 18

(28H) DISPOFF 0 1 0 0 0 1 0 1 0 0 0 Display off 19 (29H) DISPON 0 1 0 0 0 1 0 1 0 0 1 Display on 20 (2AH) CASET 0 1 0 0 0 1 0 1 0 1 0 Column address set

1 1 0 0 XS6

XS5

XS4

XS3

XS2

XS1

XS0

Column start address (0 to 131)

1 1 0 0 XE6

XE5

XE4

XE3

XE2

XE1

XE0

Column end address (0 to 131)

21

(2BH) RASET 0 1 0 0 0 1 0 1 0 1 1 Row address set 22

TLS8103 Datasheet


1 1 0 0 YS6

YS5

YS4

YS3

YS2

YS1

YS0

Row start address (0 to 131)

1 1 0 0 YE6

YE5

YE4

YE3

YE2

YE1

YE0

Row end address (0 to 131)

(2CH) RAMWR 0 1 0 0 0 1 0 1 1 0 0 Memory write operation 1 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Write data to RAM

23

(2DH) RGBSET 0 1 0 0 0 1 0 1 1 0 1 Color set for 256 or 4k color display

1 1 0 - - - R 004

R 003

R 002

R 001

R 000

Red tone (1st entry)

1 1 0 - - - ︰︰︰︰︰︰ 1 1 0 - - - R

154R

153R

152R

151R

150Red tone (16th entry)

1 1 0 - - G 005

G 004

G 003

G 002

G 001

G 000

Green tone (1st entry)

1 1 0 - - ︰︰︰︰︰︰︰ 1 1 0 - - G

155G

154G

153G

152G

151GR 150

Green tone (16th entry)

1 1 0 - - - B 004

B 003

B 002

B 001

B 000

Blue tone (1st entry)

1 1 0 - - - ︰︰︰︰︰︰

1 1 0 - - - B 154

B 153

B 152

B 151

B 150

Blue tone (16th entry)

24

(2EH) RAMRD 0 1 0 0 0 1 0 1 1 1 0 Memory read 1 0 1 - - - - - - - - Dummy read 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 Read data from RAM

25

(30H) PTLAR 0 1 0 0 0 1 1 0 0 0 0 Partial start/end address set

1 1 0 PS7

PS6

PS5

PS4

PS3

PS2

PS1

PS0

Partial start address (0 to 131)

1 1 0 PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

Partial end address (0 to 131)

26

(33H) SCRLAR 0 1 0 0 0 1 1 0 0 1 1 Scroll area set 1 1 0 TF

A7TFA6

TFA5

TFA4

TFA3

TFA2

TFA1

TFA0

TFA= 0~132

1 1 0 VSA7

VSA6

VSA5

VSA4

VSA3

VSA2

VSA1

VSA0

VSA= 0~132

1 1 0 BFA7

BFA6

BFA5

BFA4

BFA3

BFA2

BFA1

BFA0

BFA= 0~132

27

(34H) TEOFF 0 1 0 0 0 1 1 0 1 0 0 Tearing effect line off 28 (35H) TEON 0 1 0 0 0 1 1 0 1 0 1 Tearing effect mode set 1 1 0 - - - - - - - M “0”: mode 1;

“1”: mode 2

29

(36H) MADCTR 0 1 0 0 0 1 1 0 1 1 0 Memory data access control

1 1 0 MY MX MV - RGB

- - -

30

(37H) VSCSAD 0 1 0 0 0 1 1 0 1 1 1 Scroll start address of SRAM

1 1 0 SSA7

SSA6

SSA5

SSA4

SSA3

SSA2

SSA1

SSA0

SSA= 0~131

31

(38H) IDMOFF 0 1 0 0 0 1 1 1 0 0 0 Idle mode off 32 (39H) IDMON 0 1 0 0 0 1 1 1 0 0 1 Idle mode on 33 (3AH) COLMOD 0 1 0 0 0 1 1 1 0 1 0 Interface pixel format 1 1 0 - - - - - P2 P1 P0 Interface format

34

(DAH) RDID1 0 1 0 1 1 0 1 1 0 1 0 Read ID1 1 0 1 - - - - - - - - Dummy read 1 0 1 ID

17 ID16

ID15

ID14

ID13

ID12

ID11

ID10

(D7~D0)

35

(DBH) RDID2 0 1 0 1 1 0 1 1 0 1 1 Read ID2 1 0 1 - - - - - - - - Dummy read 1 0 1 ID

27 ID26

ID25

ID24

ID23

ID22

ID21

ID20

(D7~D0)

36

(DCH) RDOD3 0 1 0 1 1 0 1 1 1 0 0 Read ID3 1 0 1 - - - - - - - - Dummy read 1 0 1 ID

37 ID36

ID35

ID34

ID33

ID32

ID31

ID30

(D7~D0)

37

TLS8103 Datasheet


(B0H) DUTYSET 0 1 0 1 0 1 1 0 0 0 0 Display duty setting

1 1 0 DU7

DU6

DU5

DU4

DU3

DU2

DU1

DU0

38

(B1H) FIRSTCOM 0 1 0 1 0 1 1 0 0 0 1 First com. page address 1 1 0 F7 F6 F5 F4 F3 F2 F1 F0

39

(B3H) OSCDIV 0 1 0 1 0 1 1 0 0 1 1 FOSC divider 1 1 0 - - - - - - CL

D1CLD0

40

(B5H) NLINVSET 0 1 0 1 0 1 1 0 1 0 1 N-line control 1 1 0 M N6 N5 N4 N3 N2 N1 N0

41

(B7H) COMSCANDIR 0 1 0 1 0 1 1 0 1 1 1 Com/Seg scan direction 1 1 0 S

MY

SMX

SINV

- SBGR

- CSD1

CSD0

42

(B8H) RMWIN 0 1 0 1 0 1 1 1 0 0 0 Read modify in 43 (B9H) RMWOUT 0 1 0 1 0 1 1 1 0 0 1 Read modify out 44 (C0H) VOPSET 0 1 0 1 1 0 0 0 0 0 0 Vop setting

1 1 0 VOP7

VOP6

VOP5

VOP4

VOP3

VOP2

VOP1

VOP0

1 1 0 - - - - - - - VOP8

45

(C1H) VOPOFSETINC 0 1 0 1 1 0 0 0 0 0 1 +40mv/step 46 (C2H) VOPOFSETDEC 0 1 0 1 1 0 0 0 0 1 0 -40mv/step 47 (C3H) BIASSEL 0 1 0 1 1 0 0 0 0 1 1 Bias selection

1 1 0 - - - - - BIAS2

BIAS1

BIAS0

48

(C4H) BSTBMPXSEL 0 1 0 1 1 0 0 0 1 0 0 Booster setting 1 1 0 - - - - - BS

T2BST1

BST0

49

(C5H) BSTEFFSEL 0 1 0 1 1 0 0 0 1 0 1 Booster efficiency selection

1 1 0 - - - - - - BFT1

BFT0

50

(C7H) VOPOFFSET 0 1 0 1 1 0 0 0 1 1 1 Vop offset fuse bit adjust

1 1 0 VO S7

VOS6

VOS5

VOS4

VOS3

VOS2

VOS1

VOS0

51

(D7H) MTPERS 0 1 0 1 1 0 1 0 1 1 1 MTP erase control 52 1 1 0 - - ER

S 0 0 0 0 0

(E0H) MTPPROG 0 1 0 1 1 1 0 0 0 0 0 MTP program control 53 (E1H) MTPPROGE 0 1 0 1 1 1 0 0 0 0 1 MTP program end 54 (E2H) MTPPROGS 0 1 0 1 1 1 0 0 0 1 0 MTP program start 55 (E4H) MTPPROGA 0 1 0 1 1 1 0 0 0 1 0 MTP program address

1 1 0 - - - - - - 0 0 Always “00” 56

(F0H) FRMSEL 0 1 0 1 1 1 1 0 0 0 0 Frame Freq. in Temp. range A, B, C and D

1 1 0 - - - FA4

FA3

FA2

FA1

-

1 1 0 - - - FB4

FB3

FB2

FB1

-

1 1 0 - - - FC4

FC3

FC2

FC1

-

1 1 0 - - - FD4

FD3

FD2

FD1

-

57

(F2H) TMPRNG 0 1 0 1 1 1 1 0 0 1 0 Delimitation point of Temp. ranges of A, B, C

1 1 0 - TA6

TA5

TA4

TA3

TA2

TA1

TA0

1 1 0 - TB6

TB5

TB4

TB3

TB2

TB1

TB0

1 1 0 - TC6

TC5

TC4

TC3

TC2

TC1

TC0

58

(F3H) TMPHYS 0 1 0 1 1 1 1 0 0 1 1 Hysteretic value set 1 1 0 TH

3 TH2

TH1

TH0

59

TLS8103 Datasheet


(F4H) TMPCOE 0 1 0 1 1 1 1 1 1 1 0 Temp. compensation curve coefficients

1 1 0 MT13

MT12

MT11

MT10

MT03

MT02

MT01

MT00

1 1 0 MT33

MT32

MT31

MT30

MT23

MT22

MT21

MT20

1 1 0 MT53

MT52

MT51

MT50

MT43

MT42

MT41

MT40

1 1 0 MT73

MT72

MT71

MT70

MT63

MT62

MT61

MT60

1 1 0 MT93

MT92

MT91

MT90

MT83

MT82

MT81

MT80

1 1 0 MT113

MT112

MT111

MT110

MT103

MT102

MT101

MT100

1 1 0 MT133

MT132

MT131

MT130

MT123

MT122

MT121

MT120

1 1 0 MT153

MT152

MT151

MT150

MT143

MT142

MT141

MT140

60

(FBH) CLUTR 0 1 0 1 1 1 1 1 0 1 1 CLUT for panel red color gamma correction

1 1 0 - R 006

R 005

R 004

R 003

R 002

R 001

R 000

Red tone (1st entry)

1 1 0 - ︰︰︰︰︰︰︰︰

1 1 0 - R 316

R 315

R 314

R 313

R 312

R 311

R 310

Red tone (32th entry)

61

(FCH) CLUTG 0 1 0 1 1 1 1 1 0 1 1 CLUT for panel green color gamma correction

1 1 0 - G 006

G 005

G 004

G 003

G 002

G 001

G 000

Green tone (1st entry)

1 1 0 - ︰︰︰︰︰︰︰︰

1 1 0 - G 636

G 635

G 634

G 633

G 632

G 631

G 630

Green tone (64th entry)

62

(FDH) CLUTB 0 1 0 1 1 1 1 1 0 1 1 CLUT for panel blue color gamma correction

1 1 0 - B 006

B 005

B 004

B 003

B 002

B 001

B 000

Blue tone (1st entry)

1 1 0 - ︰︰︰︰︰︰︰︰

1 1 0 - B 316

B 315

B 314

B 313

B 312

B 311

B 310

Blue tone (32th entry)

63

TLS8103 Datasheet


COMMAND DESCRIPTION

1. NOP (00H)

Command D/C RD WR D7 D6 D5 D4 D3 D2 D1 D0 Hex NOP 0 1 0 0 0 0 0 0 0 0 0 00H parameter No parameter description This command is an empty command. It does not have effect on the display module.

However it can be used to terminate RAM data write or read as described in RAMWR (Memory Write) or RAMRD (Memory Read) and parameter write command.

restriction - Status Default value Power on sequence N/A S/W reset N/A

default

H/W reset N/A 2. SWRESET : Software Reset (01H)

Command D/C RD WR D7 D6 D5 D4 D3 D2 D1 D0 Hex SWRESET 0 1 0 0 0 0 0 0 0 0 1 01H parameter No parameter description When the Software Reset command is written, it causes a software reset. It resets the

commands and parameter to their S/W Reset default values and all segment & common output are set to Vm (display off: blank display). Note: the Frame Memory contents are not affected by this command.

restriction It will be necessary to wait 5msec before sending new command following software reset. The display module loads all display suppliers’ factory default values to the registers during 5msec. If Software Reset is applied during Sleep out mode, it will be necessary to wait 120msec before sending Sleep Out command. status Default value Power on sequence N/A S/W reset N/A

default

H/W reset N/A 3. RDDID : Read Display ID (04H)

Command D/C RD WR D7 D6 D5 D4 D3 D2 D1 D0 Hex RDDID 0 1 0 0 0 0 0 0 1 0 0 04H Dummy read 1 0 1 - - - - - - - - 2nd parameter 1 0 1 ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 3rd parameter 1 0 1 1 ID26 ID25 ID24 ID23 ID22 ID21 ID20 4th parameter 1 0 1 ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30

description This read byte returns 24-bit display identification information. The 1st parameter is dummy data; The 2nd parameter (ID17-ID10): LCD module’s manufacturer ID; The 3rd parameter (ID26-ID20): LCD module/driver version ID; The 4th parameter (ID37-ID30): LCD module/driver ID.

restriction - Default value status

ID1 ID2 ID3 Power on sequence 55H 80H 00H S/W reset 55H 80H 00H

default

H/W reset 55H 80H 00H NOTE: “-“ don’t care

TLS8103 Datasheet


4. RDDST : Read Display Status (09H)

Command D/C RD WR D7 D6 D5 D4 D3 D2 D1 D0 Hex RDDST 0 1 0 0 0 0 0 1 0 0 1 09H Dummy read 1 0 1 - - - - - - - - 2nd parameter 1 0 1 ST31 ST30 ST29 ST28 ST27 ST26 ST25 ST24 3rd parameter 1 0 1 ST23 ST22 ST21 ST20 ST19 ST18 ST17 ST16 4th parameter 1 0 1 ST15 ST14 ST13 ST12 ST11 ST10 ST9 ST8 5th parameter 1 0 1 ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0

description This command indicates the current status of the display as described in the table below:

Bit Description Value ST31 Booster Voltage Status “1”=Booster on, “0”=Booster Off ST30 Row Address Order “1”=Decrement, “0”=Increment ST29 Column Address Order “1”=Decrement, “0”=Increment ST28 Row/Column Order (MV) “1”=Row/Column exchange (MV=1)

“0”=Normal (MV=0) ST27 Scan Address Order “1”=Decrement, “0”=Increment ST26 RGB/BGR Order “1”=BGR, “0”=RGB ST25 Not Used “0” ST24 Not Used “0” ST23 Not Used “0” ST22ST21ST20

Interface Color Pixel Format Definition

“010” = 8-bit/pixel “011” = 12-bit/pixel type A “101” = 16-bit/pixel “110” = 12-bit/pixel type B

ST19 Idle Mode On/Off “1” = On, “0’ = Off ST18 Partial Mode On/Off “1” = On, “0’ = Off ST17 Sleep In/Out “1” = In, “0” = Out ST16 Display Normal Mode On/Off “1”=Partial Display, “0”=Normal displayST15 Vertical Scrolling Status “1” = Scroll On, ‘0” = Scroll Off ST14 Not Used “0” ST13 Inversion Status “1” = On, “0” = Off ST12 All Pixel On “1” = Mode On, “0” = Mode Off ST11 All Pixel Off “1” = Mode On, “0” = Mode Off ST10 Display On/Off “1” = On, “0” = Off ST9 Tearing Effect Line On/Off “1” = On, “0” = Off ST8 Not Used “0” ST7 Not Used “0” ST6 Not Used “0” ST5 Tearing Effect Line Mode “0” = Mode 1, “1” = Mode 2 ST4 Not Used “0” ST3 Not Used “0” ST2 Not Used “0” ST1 Not Used “0” ST0 Not Used “0”

restriction - status Default value Power on sequence 0000_0000_0

Teralane Semiconductor - Display Future · Dummy5, Dummy6 115 39 Bumped Pad Size Dummy7, Dummy8 39...

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