2007­06­04 Michael Traxler, GSI 1

TDC Readout Board, TRBv2TDC Readout Board, TRBv2

OutlineOutline

• Motivation / Aim• TRB V2

– projects with TRBv2 platform

• Problems, problems, problems.... and the solution :-)• Summary

2007­06­04 Michael Traxler, GSI 2

Motivation / AimMotivation / Aim

• Main Problem:– The limitation of the LVL1/LVL2 rate

• Measures:– Increase LVL1/LVL2-rate capability– Improve on the LVL2 trigger-algorithm (W. Kuehn)

Objective: 20 kHz primary data rate to ensure measuring rare decays in heavy systemsRisk: Not ready till mid. 2008 (6 months comm.)

2007­06­04 Michael Traxler, GSI 3

““new” DAQ Architecturenew” DAQ Architecture

Frondend Readout,e.g. RPC-TRBFrondend Readout,

e.g. RPC-TRBFrondend Readout,e.g. RPC-TRB

Fut,e.g. MDC-TRBFrondeout,

e.g. MDC-TRBFrondend Readout,e.g. MDC-TRB

.....

Eventbuilders

EthernetswitchEthernet Switches

Ethernet: data / slow ctrl.

Compute-Node +Trigger-Link-Hub

Compute-Node +Trigger-Link-Hub .....

Optical GB-Link

Central Trigger SystemMatching Unit

CTU

Trigger and IPU-data

EventbuildersEventbuilders(5-10)

2007­06­04 Michael Traxler, GSI 4

TRBv2TRBv2

• successor of TRBv1, which is used in the experiment

• larger FPGA• faster CPU (x3)• Tiger-Sharc DSP• 2 GBit/s optical link

for trigger and data• Add-on connector• TRBv1 functionality

given

2007-06-04 Michael Traxler, GSI 5

LVDSTTL TTL

Virtex4(LX40)

Etrax-FS

SDRAM128MB

2GBit/s optical link

DSP (TS201)

HPTDC HPTDC HPTDC HPTDC

Optional

SDRAM128MB

Add-on connector 100MBit/s Ethernet

2007­06­04 Michael Traxler, GSI 6

TRB V2, why? consequences?TRB V2, why? consequences?

Advantages to use TRB V2 as DAQ-FEE-systemAdvantages to use TRB V2 as DAQ-FEE-system• Use one common platform for all subsystems!

– Concentrate manpower on one main project• data transport issues are solved only once => more stable• easier to debug, distributed knowledge, less maintenance,

lower cost

• Interesting also for other experiments: CBM, Panda, PET-readout

Nothing is for free, general solution needs...Nothing is for free, general solution needs...– more time until deployment (more complex)– new trigger / IPU-bus over optical links (IP-core)– many people involved, more communication, better

documentation needed, ... => advantage

2007­06­04 Michael Traxler, GSI 7

TRBv2 connectivity: Add-on BoardsTRBv2 connectivity: Add-on Boards

• 15 GBit/s connector + many multipurpose I/Os• Add-on-boards provide the connectivity to the other

detectors / new applications / other experiments

TRB V2 can be our common DAQ-FEE-platformTRB V2 can be our common DAQ-FEE-platform– RPC, Forward Wall, Beam-detectors, TOF, PETRPC, Forward Wall, Beam-detectors, TOF, PET

• With HPTDCWith HPTDC

– MDC, RICH, ShowerMDC, RICH, Shower• Without HPTDCWithout HPTDC

– around 100 boards will be usedaround 100 boards will be used

2007­06­04 Michael Traxler, GSI 8

Status / Manpower / RiskStatus / Manpower / RiskTRBv2TRBv2

Status:Status:• TRBv2 ready to be used for RPC, Forward-Wall,

Beam-Detectors, TOF => TRBv1 functionality=> low risk!low risk!Manpower:Manpower:• Current main developers:

– TRBv2: Marek Pałka, Radek Trębacz– TRB Net: Ingo Fröhlich, Jan Michel

• Involved: Marcin Kajetanowicz , Krzysztof Korcyl + others

2007­06­04 Michael Traxler, GSI 9

TRB HUB, StatusTRB HUB, Status

Purpose:Purpose:• distribute LVL1/2 triggers, IPU-Link, slow-control• TRBv2 add-on: Lattice-SC FPGA with 16 optical

links– 16 SERDES integrated into FPGA

Status:Status:• Schematics finished, Layout finished, PCB ordered

2007­06­04 Michael Traxler, GSI 10

TRB-Net, StatusTRB-Net, Status

• TRB-Net has left stage of simulation

• stable communication running

• HUB functionality is still missing

2007­06­04 Michael Traxler, GSI 11

TOF-detector-FEE, StatusTOF-detector-FEE, Status

• PM-signal, time and amplitude data has to be taken• FEE with Q2W (ToT) logic needed for TRB

– get rid of CAMAC etc.– the rest is identical to RPC

• Evgueni Usenko (INR Moscow, Fedor Guber's group)– Analogue expert, one of the designers of the NINO ASIC

• Concept:– TRB-add-on with PM-amplifier and Q2W logic for 128

channels, based on NINO

2007­06­04 Michael Traxler, GSI 12

MDC Setup: current and new (with TRB)MDC Setup: current and new (with TRB)

2007­06­04 Michael Traxler, GSI 13

Status / ManpowerStatus / ManpowerTRB-MDC-Add-onTRB-MDC-Add-on

• Readout of MDC-Motherboards

• VHDL code written and simulated

• Token-chain working in hardware

• Manpower: Attilio Tarantola

• Readout: same as for HPTDC

2007­06­04 Michael Traxler, GSI 14

2007­06­04 Michael Traxler, GSI 15

DAQ-Upgrade, if a working LVL2 trigger DAQ-Upgrade, if a working LVL2 trigger algorithm can not be foundalgorithm can not be found

• If we will not have a LVL2 trigger for Au+Au we can expect (worst case):– 150 MBytes/s sustained rate (300 MBytes/s peak)

• This is very inconvenient:– 86 TBytes / week– expensive (8k€ for tapes/week)– Compression can save 30% (tested)

• DAQ and IT-department are able to do this• Comparison:

– Phenix is writing since 2004 350MBytes/s sustained to tape (600MBytes/s with compression).

2007­06­04 Michael Traxler, GSI 16

TRBv2 from the point of ElectronicsTRBv2 from the point of Electronics

„New“ technologies (high risk)• LatticeSC FPGA: price, SERDES feature• ispClock

– 5 programmable clocks, different standards, rise time• Power-Sequencer

– 14 outputs, 10 analog inputs, sequencer, I2C, JTAG• EtraxFS processor, Axis

– CPU + 3 CoProcessors– Fast, flexible and complicated

• several month of manpower– easy to run: standard Linux, development environment– Flash: new, not supported, patch solved the problem

2007­06­04 Michael Traxler, GSI 17

Problems, TRBv2Problems, TRBv2

Layout is a major effort• 8 different voltages• 13 power „planes“ (different DC/DC converters and LDOs)• Power filtering, carefully designed pi-filters• impedance matched differential pairs and length matched

differential pairs (500MHz)– layout system doesn't support this, Specctra does!

• Plugged-Vias, needed for capacitors (low inductance)• 4000 „components“, 5200 vias, 8000 connections, 12 layers• 2 month for Peter Skott• 150-750€/PCB (10) depending on manufacturer• 6 month delay due to Q-Print

2007­06­04 Michael Traxler, GSI 18

Problems, TRBv2Problems, TRBv2

• 2GBit/s links did work in the beginning just with short cables• Eye-pattern open! No sign of problems!• Tektronix: around 2 MHz „wander“ of time-period from ispClock

2007­06­04 Michael Traxler, GSI 19

SummarySummary

• Large and demanding project!• Many people involved• progress: looks promising• few parts with high risk

– fallbacks are possible

• „Future-DAQ“ is happening now at HADES and really motivates the involved people

2007­06­04 Michael Traxler, GSI 20

TRBv2 -> DAQ upgradeTRBv2 -> DAQ upgrade

Thank you for your attention!