******************************************************* ******* EXPERIMENT 6-Full Adder ********* *******************************************************

* SPICE export by: SEDIT 13.00 * Export time: Sat Nov 07 18:04:11 2015 * Design: fulladder * Cell: Cell0 * View: view0 * Export as: top-level cell * Export mode: hierarchical * Exclude .model: yes * Exclude .end: no * Expand paths: yes * Wrap lines: 80 characters * Root path: C:\Users\Siddharth\Documents\new\fulladder * Exclude global pins: no * Control property name: SPICE ********* Simulation Settings - General section ********* ********* Simulation Settings - Parameters and SPICE Options ********* *-------- Devices: SPICE.ORDER > 0 -------- MNMOS_1 N_8 N_6 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_2 N_9 B Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_3 N_5 N_7 N_9 N_9 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_4 N_5 A N_8 N_8 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_5 N_7 A Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_6 N_6 B Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_7 N_17 N_5 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_8 N_3 A N_2 N_2 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_9 N_2 B Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_10 N_4 N_3 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_11 N_12 N_17 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_12 N_13 C1 N_12 N_12 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_13 SUM N_14 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_14 N_15 C1 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_15 N_16 N_17 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_16 N_14 N_17 N_18 N_18 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_17 N_14 N_16 N_19 N_19 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_18 N_19 C1 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_19 N_21 N_13 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_20 N_18 N_15 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_21 N_23 N_21 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_22 N_23 N_4 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_23 COut N_23 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_10 N_4 N_3 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_11 N_14 N_16 N_20 N_20 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_12 N_13 N_17 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_13 N_13 C1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_14 SUM N_14 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_15 N_15 C1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_16 N_16 N_17 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MPMOS_17 N_20 N_17 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_18 N_20 N_15 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_19 N_14 C1 N_20 N_20 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_20 N_21 N_13 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_21 N_22 N_4 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_22 N_23 N_21 N_22 N_22 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_23 COut N_23 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_1 N_5 N_7 N_10 N_10 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_2 N_5 B N_10 N_10 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_3 N_10 N_6 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_4 N_10 A Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_5 N_7 A Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_6 N_6 B Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_7 N_17 N_5 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_8 N_3 A Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_9 N_3 B Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u ********* Simulation Settings - Analysis section ********* ********* Simulation Settings - Additional SPICE commands ********* .tran 1n 100n .dc lin source v1 0 5 .1 .lib "C:\Users\Siddharth\Documents\Tanner EDA\Tanner Tools v13.0\Libraries\Models\Generic_025.lib" TT v1 A Gnd BIT ({01010101}) v2 B Gnd BIT ({00110011}) v3 C1 Gnd BIT ({00001111}) v4 Vdd Gnd 5 .print tran v(SUM) v(COut) v(C1) v(B) v(A) .op .end

******************************************************************* ******* EXPERIMENT 7- FULL ADDER ********* ******************************************************************* * SPICE export by: SEDIT 13.00 * Export time: Tue Nov 10 01:13:43 2015 * Design: fa * Cell: Cell0 * View: view0 * Export as: top-level cell * Export mode: hierarchical * Exclude .model: yes * Exclude .end: no * Expand paths: yes * Wrap lines: 80 characters * Root path: C:\Users\Siddharth\Documents\new\fa * Exclude global pins: no * Control property name: SPICE ********* Simulation Settings - General section ********* ********* Simulation Settings - Parameters and SPICE Options ********* *-------- Devices: SPICE.ORDER > 0 -------- MNMOS_3 N_1 B Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_4 N_3 A N_8 N_8 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_5 N_8 B Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_6 N_11 N_3 N_7 N_7 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_7 N_11 A N_14 N_14 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_8 N_7 A Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_9 N_7 B Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_10 N_7 C Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_11 N_14 B N_15 N_15 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_12 N_15 C Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_13 CO N_3 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_14 SUM N_11 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_1 N_3 C N_1 N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_2 N_1 A Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_10 N_11 A N_10 N_10 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_11 N_10 B N_13 N_13 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_12 N_13 C Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_13 SUM N_11 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_14 CO N_3 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_1 N_12 A Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_2 N_3 C N_12 N_12 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_3 N_12 B Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_4 N_5 B Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_5 N_3 A N_5 N_5 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_6 N_31 A Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_7 N_31 B Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_8 N_31 C Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_9 N_11 N_3 N_31 N_31 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

********* Simulation Settings - Analysis section ********* ********* Simulation Settings - Additional SPICE commands ********* .tran 1n 100n .dc lin source v1 0 5 .1 .lib "C:\Users\Siddharth\Documents\Tanner EDA\Tanner Tools v13.0\Libraries\Models\Generic_025.lib" TT v1 A Gnd BIT ({01010101}) v2 B Gnd BIT ({00110011}) v3 C Gnd BIT ({00001111}) v4 Vdd Gnd 5 .print tran v(SUM) v(CO) v(C) v(B) v(A) .op .end ***WAVEFORM***

**************************************************************** ******* EXPERIMENT NO 8- XNOR ********* **************************************************************** * SPICE export by: SEDIT 13.00 * Export time: Fri Nov 20 17:34:35 2015 * Design: xnor * Cell: Cell0 * View: view0 * Export as: top-level cell * Export mode: hierarchical * Exclude .model: yes * Exclude .end: no * Expand paths: yes * Wrap lines: 80 characters * Root path: C:\Users\Siddharth\Documents\new\xnor * Exclude global pins: no * Control property name: SPICE ********* Simulation Settings - General section ********* ********* Simulation Settings - Parameters and SPICE Options ********* *-------- Devices: SPICE.ORDER > 0 -------- MNMOS_1 N_1 N_3 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_2 N_2 In2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_3 Out N_7 N_2 N_2 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_4 Out In1 N_1 N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_5 N_7 In1 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_6 N_3 In2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_1 Out N_7 N_10 N_10 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_2 Out In2 N_10 N_10 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_3 N_10 N_3 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_4 N_10 In1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_5 N_7 In1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_6 N_3 In2 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u ********* Simulation Settings - Analysis section ********* ********* Simulation Settings - Additional SPICE commands ********* .tran 10n 100n .dc lin source v1 0 5 .1 sweep lin source v2 0 5 .1 .lib "C:\Users\Siddharth\Documents\Tanner EDA\Tanner Tools v13.0\Libraries\Models\Generic_025.lib" TT v1 In1 Gnd BIT ({00100100}) v2 In2 Gnd BIT ({10010110}) v3 Vdd Gnd 5 .print tran v(Out) v(In2) v(In1) .op .end

******************************************************************* ******* EXPERIMENT NO 9 - D LATCH ********* ******************************************************************* * SPICE export by: SEDIT 13.00 * Export time: Wed Oct 28 14:39:07 2015 * Design: dlatch * Cell: Cell0 * View: view0 * Export as: top-level cell * Export mode: hierarchical * Exclude .model: yes * Exclude .end: no * Expand paths: yes * Wrap lines: 80 characters * Root path: C:\Users\Siddharth\Documents\new\dlatch * Exclude global pins: no * Control property name: SPICE ********* Simulation Settings - General section ********* ********* Simulation Settings - Parameters and SPICE Options ********* *-------- Devices: SPICE.ORDER > 0 -------- MNMOS_1 N_2 In2 Gnd N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_2 N_4 In N_2 N_3 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_3 N_6 In Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_4 Out N_4 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_5 N_4 N_6 N_13 N_12 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_6 N_13 Out Gnd N_14 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_1 N_4 N_6 N_7 N_5 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_2 N_7 In2 Vdd N_8 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_3 N_6 In Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_4 Out N_4 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_5 N_10 Out Vdd N_9 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_6 N_4 In N_10 N_11 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u ********* Simulation Settings - Analysis section ********* ********* Simulation Settings - Additional SPICE commands ********* .tran 10n 100n .dc lin source v1 0 5 .1 sweep lin source v2 0 5 .1 .lib "C:\Users\Siddharth\Documents\Tanner EDA\Tanner Tools v13.0\Libraries\Models\Generic_025.lib" TT v1 In Gnd BIT ({01101101}) v2 In2 Gnd BIT ({00101101}) v3 Vdd Gnd 5 .print tran v(Out) v(In2) v(In) .op .end

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************************************************************************** EXPERIMENT NO 1- INVERTER ***************************************************************************** SPICE export by: SEDIT 13.00* Export time: Fri Sep 04 13:56:38 2015* Design: inverter* Cell: Cell0* View: view1* Export as: top-level cell* Export mode: hierarchical* Exclude .model: yes* Exclude .end: no* Expand paths: yes* Wrap lines: 80 characters* Root path: C:\Users\Siddharth\Documents\new\inverter* Exclude global pins: no* Control property name: SPICE********* Simulation Settings - General section ****************** Simulation Settings - Parameters and SPICE Options **********-------- Devices: SPICE.ORDER > 0 --------MNMOS_1 Out In Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_1 Out In Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u ********* Simulation Settings - Analysis section ****************** Simulation Settings - Additional SPICE commands *********.tran 10n 100n.dc lin source v1 0 5 .1.lib "C:\Users\Siddharth\Documents\Tanner EDA\Tanner Tools v13.0\Libraries\Models\Generic_025.lib" TTv1 In Gnd BIT ({01101001})v2 Vdd Gnd 5.print dc v(Out).print tran v(In) v(Out).op.end

******************************************************************* ******* EXPERIMENT NO 2- NAND ********* ******************************************************************* * SPICE export by: SEDIT 13.00 * Export time: Mon Oct 05 23:22:04 2015 * Design: and2 * Cell: Cell0 * View: view0 * Export as: top-level cell * Export mode: hierarchical * Exclude .model: yes * Exclude .end: no * Expand paths: yes * Wrap lines: 80 characters * Root path: C:\Users\Siddharth\Documents\new\and2 * Exclude global pins: no * Control property name: SPICE ********* Simulation Settings - General section ********* ********* Simulation Settings - Parameters and SPICE Options ********* *-------- Devices: SPICE.ORDER > 0 -------- MNMOS_1 N_1 In2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_2 Out In1 N_1 N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_1 Out In2 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_2 Out In1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u ********* Simulation Settings - Analysis section ********* ********* Simulation Settings - Additional SPICE commands ********* .tran 10n 100n .dc lin source v1 0 5 .1 .lib "C:\Users\Siddharth\Documents\Tanner EDA\Tanner Tools v13.0\Libraries\Models\Generic_025.lib" TT .dc lin source v1 0 5 .1 sweep lin source v2 0 5 .1 v1 In1 Gnd BIT ({1010110010}) v2 In2 Gnd BIT ({1110001010}) v3 Vdd Gnd 5 .print dc v(Out) .print tran v(Out) v(In1) v(In2) .op .end

******************************************************************* ******* EXPERIMENT NO 3- NOR ********* ******************************************************************* * SPICE export by: SEDIT 13.00 * Export time: Tue Oct 06 22:30:48 2015 * Design: nor2 * Cell: Cell0 * View: view0 * Export as: top-level cell * Export mode: hierarchical * Exclude .model: yes * Exclude .end: no * Expand paths: yes * Wrap lines: 80 characters * Root path: C:\Users\Siddharth\Documents\new\nor2 * Exclude global pins: no * Control property name: SPICE ********* Simulation Settings - General section ********* ********* Simulation Settings - Parameters and SPICE Options ********* *-------- Devices: SPICE.ORDER > 0 -------- MNMOS_1 Out In1 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_2 Out In2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_1 Out In2 N_1 N_1 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_2 N_1 In1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u ********* Simulation Settings - Analysis section ********* ********* Simulation Settings - Additional SPICE commands ********* .tran 10n 100n .dc lin source v1 0 5 .1 sweep lin source v2 0 5 .1 .lib "C:\Users\Siddharth\Documents\Tanner EDA\Tanner Tools v13.0\Libraries\Models\Generic_025.lib" TT v1 In1 Gnd BIT ({00110110}) v2 In2 Gnd BIT ({00010110}) v3 Vdd Gnd 5 .print dc v(Out) .print tran v(Out) v(In2) v(In1) .op .end

******************************************************************* ******* EXPERIMENT NO 4- HALFADDER ********* ******************************************************************* * SPICE export by: SEDIT 13.00 * Export time: Wed Oct 07 13:55:24 2015 * Design: halfadder * Wrap lines: 80 characters * Root path: C:\Users\Siddharth\Documents\new\halfadder * Exclude global pins: no * Control property name: SPICE ********* Simulation Settings - General section ********* ********* Simulation Settings - Parameters and SPICE Options ********* *-------- Devices: SPICE.ORDER > 0 -------- MNMOS_3 N_4 N_2 N_6 N_6 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_4 N_4 In1 N_5 N_5 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_5 N_2 In1 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_6 N_1 In2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_7 Out1 N_4 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_8 N_7 In1 N_8 N_8 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_9 N_8 In2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_10 Out2 N_7 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_1 N_5 N_1 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_2 N_6 In2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_10 Out2 N_7 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_1 N_4 N_2 N_3 N_3 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_2 N_4 In2 N_3 N_3 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_3 N_3 N_1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_4 N_3 In1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_5 N_2 In1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_6 N_1 In2 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_7 Out1 N_4 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_8 N_7 In1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_9 N_7 In2 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u ********* Simulation Settings - Analysis section ********* ********* Simulation Settings - Additional SPICE commands ********* .tran 10n 100n .dc lin source v1 0 5 .1 .lib "C:\Users\Siddharth\Documents\Tanner EDA\Tanner Tools v13.0\Libraries\Models\Generic_025.lib" TT .dc lin source v1 0 5 .1 sweep lin source v2 0 5 .1 v1 In1 Gnd BIT ({1010110010}) v2 In2 Gnd BIT ({1110001010}) v3 Vdd Gnd 5 .print dc v(Out1) v(Out2) .print tran v(Out1) v(Out2) v(In1) v(In2) .op .end

**************************************************************** ******* EXPERIMENT NO 5- Half Subtractor ********* **************************************************************** * SPICE export by: SEDIT 13.00 * Export time: Fri Nov 20 18:49:24 2015 * Design: hs * Cell: Cell0 * View: view0 * Export as: top-level cell * Export mode: hierarchical * Exclude .model: yes * Exclude .end: no * Expand paths: yes * Wrap lines: 80 characters * Root path: C:\Users\Siddharth\Documents\new\hs * Exclude global pins: no * Control property name: SPICE ********* Simulation Settings - General section ********* ********* Simulation Settings - Parameters and SPICE Options ********* *-------- Devices: SPICE.ORDER > 0 -------- MNMOS_3 N_4 N_3 N_7 N_7 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_4 N_4 In1 N_6 N_6 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_5 N_3 In1 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_6 N_5 In2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_7 Out1 N_4 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_8 N_2 N_3 N_1 N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_9 N_1 In2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_10 Out2 N_2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_1 N_6 N_5 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_2 N_7 In2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_10 Out2 N_2 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_1 N_4 N_3 N_8 N_8 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_2 N_4 In2 N_8 N_8 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_3 N_8 N_5 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_4 N_8 In1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_5 N_3 In1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_6 N_5 In2 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_7 Out1 N_4 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_8 N_2 N_3 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_9 N_2 In2 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u ********* Simulation Settings - Analysis section ********* ********* Simulation Settings - Additional SPICE commands ********* .tran 10n 100n .dc lin source v1 0 5 .1 .lib "C:\Users\Siddharth\Documents\Tanner EDA\Tanner Tools v13.0\Libraries\Models\Generic_025.lib" TT .dc lin source v1 0 5 .1 sweep lin source v2 0 5 .1 v1 In1 Gnd BIT ({1010110010})

v2 In2 Gnd BIT({1110001010}) v3 Vdd Gnd 5 .print dc v(Out1) v(Out2) .print tran v(Out1) v(Out2) v(In1) v(In2) .op .end WAVEFORM