Tanner Workbook (1)

8/18/2019 Tanner Workbook (1)

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TANNER TOOLS

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INDEX

S.No. TITLE Page No.

1. Integrated Circuit Layout 3

2. Integrated Circuit Design 4

3. Tanner IC Work Flow 9

4. S-EDIT 11

5. T-SPICE 23

6. W-EDIT 25

7. L-EDIT 28

8. LVS (Layout Vs Schematic) 43

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Integrated Circuit Layout

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousandsof transistor -based circuits into a single chip. VLSI began in the 1970s when complex semiconductor andcommunication technologies were being developed. The microprocessor is a VLSI device. The term is nolonger as common as it once was, as chips have increased in complexity into the hundreds of millions oftransistors.

Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the representation ofan integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, orsemiconductor layers that make up the components of the integrated circuit.When using a standard process - where the interaction of the many chemical, thermal, and photographic

variables are known and carefully controlled - the behavior of the final integrated circuit depends largely onthe positions and interconnections of the geometric shapes. A layout engineer's job is to place and connectall the components that make up a chip so that they meet all criteria. Typical goals are performance, size,and manufacturability.

The layout must pass a series of checks in a process known as verification. The two most common checks inthe verification process are Design Rule Checking (DRC), and Layout Versus Schematic (LVS). When allverification is complete the data is translated into an industry standard format, typically GDSII, and sent to asemiconductor foundry. The process of sending this data to the foundry is called tapeout due to the fact thedata used to be shipped out on a magnetic tape. The foundry converts the data into another format and usesit to generate the photomasks used in a photolithographic process of semiconductor device fabrication.

In the earlier, simpler, days of IC design, layout was done by hand using opaque tapes and films, much likethe early days of PCB design. Modern IC Layout is done with the aid of IC layout editor software, or evenautomatically using EDA tools, including place and route tools or schematic driven layout tools. Themanual operation of choosing and positioning the geometric shapes is informally known as "polygon pushing".

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Integrated circuit design

Integrated circuit design, or IC design, is a subset of electrical engineering, encompassing the particular

logic and circuit design techniques required to design integrated circuits, or ICs. ICs consist of miniaturizedelectronic components built into an electrical network on a monolithic semiconductor substrate by photolithography.

IC design can be divided into the broad categories of digital and analog IC design. Digital IC design is usedto produce components such as microprocessors, FPGAs, memories (RAM, ROM, and flash) and digitalASICs. Digital design focuses on logical correctness, maximizing circuit density, and placing circuits sothat clock and timing signals are routed efficiently. Analog IC design also has specializations in power ICdesign and RF IC design. Analog IC design is used in the design of op-amps, linear regulators, phase lockedloops, oscillators and active filters. Analog design is more concerned with the physics of the semiconductordevices such as gain, matching, power dissipation, and resistance. Fidelity of analog signal amplificationand filtering is usually critical and as a result, analog ICs use larger area active devices than digital designsand are usually less dense in circuitry.

Modern ICs are enormously complicated. A large chip, as of 2006, may well have more transistors thanthere are people on Earth. The rules for what can and cannot be manufactured are also extremely complex.An IC process as of 2006 may well have more than 600 rules. Furthermore, since the manufacturing processitself is not completely predictable, designers must account for its statistical nature. The complexity ofmodern IC design, as well as market pressure to produce designs rapidly, has led to the extensive use ofautomated design tools in the IC design process. In short, the design of an IC using EDA software is thedesign, test, and verification of the instructions that the IC is to carry out.

Fundamentals

Integrated circuit design involves the creation of electronic components, such as transistors, resistors,capacitors and the metallic interconnect of these components onto a piece of semiconductor, typicallysilicon. A method to isolate the individual components formed in the substrate is necessary since thesubstrate silicon is conductive and often forms an active region of the individual components. The twocommon methods are p-n junction isolation and dielectric isolation. Attention must be given to powerdissipation of transistors and interconnect resistances and current density of the interconnect, contacts andvias since ICs contain very tiny devices compared to discrete components, where such concerns are less ofan issue. Electromigration in metallic interconnect and ESD damage to the tiny components are also ofconcern. Finally, the physical layout of certain circuit subblocks is typically critical, in order to achieve the

desired speed of operation, to segregate noisy portions of an IC from quiet portions, to balance the effects ofheat generation across the IC, or to facilitate the placement of connections to circuitry outside the IC.

Design steps

A typical IC design cycle involves several steps:

1. Feasibility study and die size estimate2. Functional verification3. Circuit/RTL design4. Circuit/RTL simulation Logic simulation

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Floorplanning

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6. Design review7. Layout8. Layout verification9. Static timing analysis

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Layout review11. Design For Test and Automatic test pattern generation12. Design for manufacturability (IC)13. Mask data preparation14. Wafer fabrication15. Die test16. Packaging17. Post silicon validation18. Device characterization19. Tweak (if necessary)20. Datasheet generation Portable Document Format

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Ramp up22. Production23. Yield Analysis / Warranty Analysis Reliability (semiconductor)24. Failure analysis on any returns25. plan for next generation chip using production information if possible

Digital design

Roughly speaking, digital IC design can be divided into three parts

• ESL design: This step creates the user functional specification. The user may use a variety of

languages and tools to create this description. Examples include a C/C++ model, SystemC,SystemVerilog Transaction Level Models.

• RTL design: This step converts the user specification (what the user wants the chip to do) into aregister transfer level (RTL) description. The RTL describes the exact behavior of the digital circuitson the chip, as well as the interconnections to inputs and outputs.

• Physical design: This step takes the RTL, and a library of available logic gates, and creates a chipdesign. This involves figuring out which gates to use, defining places for them, and wiring themtogether.

Note that the second step, RTL design, is responsible for the chip doing the right thing. The third step, physical design, does not affect the functionality at all (if done correctly) but determines how fast the chip

operates and how much it costs.

RTL design

This is the hardest part, and the domain of functional verification. The spec may have some tersedescription, such as encodes in the MP3 format or implements IEEE floating-point arithmetic. Each of theseinnocent looking statements expands to hundreds of pages of text, and thousands of lines of computer code.It is extremely difficult to verify that the RTL will do the right thing in all the possible cases that the usermay throw at it. Many techniques are used, none of them perfect but all of them useful – extensive logicsimulation, formal methods, hardware emulation, lint-like code checking, and so on.

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A tiny error here can make the whole chip useless, or worse. The famous Pentium FDIV bug caused theresults of a division to be wrong by at most 61 parts per million, in cases that occurred very infrequently. No

one even noticed it until the chip had been in production for months. Yet Intel was forced to offer to replace,for free, every chip sold until they could fix the bug, at a cost of $475 million (US).

Physical design

Here are the main steps of physical design. In practice there is not a straightforward progression -considerable iteration is required to ensure all objectives are met simultaneously. This is a difficult problemin its own right, called design closure.

• Floorplanning: The RTL of the chip is assigned to gross regions of the chip, input/output (I/O) pins

are assigned and large objects (arrays, cores, etc.) are placed.• Logic synthesis: The RTL is mapped into a gate-level netlist in the target technology of the chip.• Placement: The gates in the netlist are assigned to nonoverlapping locations on the die area.• Logic/placement refinement: Iterative logical and placement transformations to close performance

and power constraints.• Clock insertion: Balanced buffered clock trees are introduced into the design.• Routing: The wires that connect the gates in the netlist are added.• Postwiring optimization: Remaining performance (Timing Closure), noise (Signal Integrity), and

yield (Design for Manufacturability) violations are removed.• Design for manufacturability: The design is modified, where possible, to make it as easy and

efficient as possible to produce. This is achieved by adding extra vias or adding dummy

metal/diffusion/poly layers wherever possible while complying to the design rules set by thefoundry.

• Final checking: Since errors are expensive, time consuming and hard to spot, extensive errorchecking is the rule, making sure the mapping to logic was done correctly, and checking that themanufacturing rules were followed faithfully.

• Tapeout and mask generation: the design data is turned into photomasks in mask data preparation.

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Process corners

Process corners provide digital designers the ability to simulate the circuit while accounting for variations in

the technology process.

A simple CMOS Operational Amplifier Layout

Analog design

Before the advent of the microprocessor and software based design tools, analog ICs were designed usinghand calculations. These ICs were basic circuits, op-amps are one example, usually involving no more thanten transistors and few connections. An iterative trial-and-error process and "overengineering" of devicesize was often necessary to achieve a manufacturable IC. Reuse of proven designs allowed progressivelymore complicated ICs to be built upon prior knowledge. When inexpensive computer processing becameavailable in the 1970s, computer programs were written to simulate circuit designs with greater accuracy

than practical by hand calculation. The first circuit simulator for analog ICs was called SPICE (SimulationProgram with Integrated Circuits Emphasis). Computerized circuit simulation tools enable greater IC designcomplexity than hand calculations can achieve, making the design of analog ASICs practical. Thecomputerized circuit simulators also enable mistakes to be found early in the design cycle before a physicaldevice is fabricated. Additionally, a computerized circuit simulator can implement more sophisticateddevice models and circuit analysis too tedious for hand calculations, permitting Monte Carlo analysis and process sensitivity analysis to be practical. The effects of parameters such as temperature variation, dopingconcentration variation and statistical process variations can be simulated easily to determine if an IC designis manufacturable. Overall, computerized circuit simulation enables a higher degree of confidence that thecircuit will work as expected upon manufacture.

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Coping with variability

A challenge most critical to analog IC design involves the variability of the individual devices built on the

semiconductor chip. Unlike board-level circuit design which permits the designer to select devices that haveeach been tested and binned according to value, the device values on an IC can vary widely which areuncontrollable by the designer. For example, some IC resistors can vary ±20% and β of an integrated BJTcan vary from 20 to 100. To add to the design challenge, device properties often vary between each processed semiconductor wafer. Device properties can even vary significantly across each individual IC dueto doping gradients. The underlying cause of this variability is that many semiconductor devices are highlysensitive to uncontrollable random variances in the process. Slight changes to the amount of diffusion time,uneven doping levels, etc. can have large effects on device properties.The design techniques necessary to reduce the effects of the device variation are:

• Using the ratios of resistors, which do match closely, rather than absolute resistor value.

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Using devices with matched geometrical shapes so they have matched variations.• Making devices large so that statistical variations becomes an insignificant fraction of the overall

device property.• Segmenting large devices, such as resistors, into parts and interweaving them to cancel variations.• Using common centroid device layout to cancel variations in devices which must match closely

(such as the transistor differential pair of an op amp).

Fortunately for IC design, the absolute values of the devices are less critical than the identical matching ofdevice performance. However, this fabrication variability forces certain design techniques and prevents theuse of other design techniques familiar to the board-level designer.

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Tanner IC Work Flow

Tanner Tools are fully-integrated solutions consisting of tools for schematic entry, circuit simulation,waveform probing, full-custom layout editing, placement and routing, netlist extraction, LVS and designrule checking (DRC) verification.

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IntroductionThis document gives a rough overview of how to design & simulate things with Tanner Tools. There arefour basic steps:

1. Design the schematic in S-EDIT.2. Simulate the schematic to make sure it behaves as you expect using T-SPICE.3. Layout the schematic in L-EDIT.4. Perform an LVS (Layout VS Schematic) to make sure your layout is functionally the same as the

schematic you designed in S-EDIT.5. Simulate the layout using T-SPICE with a high-level spice model, making sure L-EDIT generates

the parasitic capacitances so they are included in the simulation.

What follows is a brief overview of the steps.

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S-EDIT

Simulating Schematics in S-EDITRun Tanner Tools S-Edit, Tanner’s schematic entry program.File -> new design

Type the design name and locate it in a folder and click ok-

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Add libraries from libraries toolbar-Add (all.tanner), it includes complete library components.

This all folder is located at:My Documents\Tanner EDA\Tanner Tools v13.0\Libraries\All

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Now we need to create a cell:

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Give a name to cell0: (Inverter)

Scroll mouse for zoom in and zoom out-

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Click on devices for CMOS Inverter design-Select pmos and click on Instance

With mouse device will attached, place it by single click, right click on workspace or done to go back

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Similarly we can paste Nmos ->

Properties of devices can be changed from properties toolbar, it is customizable

Select misc from library toolbar, and paste Vdd and Gnd

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Select SPICE_Elements then voltagesource, Type of voltage can be changed by instance cell, as follows

Paste one DC and one Pulse voltage source at workspace

Now connections can be made from wire selection

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Just click on open node of device and wire the nodes accordingly

Now we need to add Input port and Output port

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Now connect input, output port accordingly

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Now include SPICE_commands (printvoltage) from library &Connect this to input and output port to check waveform

We need to include model file (hp05.md) with SPICE_commands -> includeHp05.md file location is inserted at value

“C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.0\L-Edit andLVS\LVS\SPR_Core\hp05.md”

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Paste this include command anywhere at workspace

To move a component anywhere at workspace, click on component, then by pressing scroll button, it can bemoved anywhere.

Now circuit is complete. Just save it.For simulation of design go to Setup-> spice_simulation

Select Spice options (analysis) then define time parameter

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Click OK, then Select Tools-> start simulation

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T-SPICE

It will automatically invoke T-Spice software

Then simulation -> run simulation

A Netlist file will be open as follows

Spice commands can be inserted from Insert Command Button

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W-EDIT

Waveform can be checked Using W-Edit; It will automatically invoked at the time of running T-spice

Waveform:

Input and outputs are overlapped in this waveform, we can separate it by Expand chart

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Now check the waveform

After selecting output, FFT can be seen from FFT Button

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L-EDITCMOS Inverter Structure: -

Double click on L-Edit;File -> new

Now copy TDB (Tanner Data Base) file from browse

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Path for TDB FileC:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.0\L-Edit andLVS\Tech\Mosis\morbn20.tdbAnd Click OK

Goto cell -> new

Name the cell->

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Grids spacing can be minimized or maximized using – or + signTo change the technology Goto setup-> Design

Select Lambda or microns accordingly and click ok

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Before designing layout we need to remember following equationsN Diffusion = N select and Active – (1)

P Diffusion = P select and Active - (2)

From layer palette, we can select layer then for drawing layer we need to switch at Drawing boxes as

follows

Now we can start layout designingWe are Taking Example of CMOS Layout designBackground of L-Edit is P-Substrate by default

We need to design PMOS, First draw active

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Now draw P select over Active with keeping in mind Lambda based design rules

Now draw poly over it accordingly

Now draw metal1 to design Contact

Now draw Active Contact for Active region

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We have designed source, gate and drain Now we need to put this in N-Well

We can perform DRC (Design Rule Check) at every stage

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If we are violating any Design rule then it will be shown in Error verification navigator

On pointing any error, it will be shown in corresponding layout, as follows

It is called lens, now we need to edit N-well

We can check DRC at every stage

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Now we need to draw Body terminal, Gate contact

After designing Body terminal (n select+ active+metal1+active contact), we need to design Gate contact

In case of Poly Layer, we need to draw Poly contact

To define port, go to (A)

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Type the name of port;

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Similarly we can design N MOS; and after connecting these two, CMOS layout will look like as follows

Now we can extract netlist by doing some settings

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Now select Extract standard rule set, and click on pencil

Now we need to include Extract file, and Spice output file at desired locationLocation for .ext file isC:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.0\L-Edit andLVS\Tech\Mosis\morbn20.ext

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Define location for output files

In output, select Names (writing nodes)

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Click ok, now go to extract button

Click on extract, An spice file will open as follows

We can open this spice file in T-Spice and can perform desired analysisWe need to include hp05.md file for analysis

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We need to insert some spice commands to perform transient analysis :

VVoltageSource_1 Vdd Gnd DC 5VVoltageSource_2 vin Gnd PULSE(0 5 0 5n 5n 95n 200n).PRINT TRAN V(vin)

.PRINT TRAN V(vout)

.tran 1ns 500ns

After saving spice file, we can simulate it, W-Edit will invoked and we can check the response:

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LVS

(Layout Vs Schematic)

We got two output files (one from S-Edit and second from L-Edit), Now we can compare results by usingLVS

Double click on LVS, and file -> new &Select file type-> LVS setup, then ok

We need to browse spice netlist files for layout netlist and Schematic netlist

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After including these files, we need to run verification as follows &Results can be checked from Verification Window.

Both netlists are equal.

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