2014 27th IEEE International

System-on-Chip Conference

(SOCC2014)

Las Vegas, Nevada, USA

2-5 September 2014

Airrr^rlbkc

IEEE Catalog Number: CFP14ASI-POD

ISBN: 978-1-4799-3379-2

TABLE OF CONTENTS

Day 1: Tuesday, September 2,2014 - TUTORIALDAY

n ac a nn. Registration7:45am-4:00pm

^5^^DESK

9:00am-5:00pm TutorialsChair: Yuejian Wu, mfinera

Morning - Tutorial Track A - SUNSET 1

T1A - Opportunities and Challenges for Secure Hardware and Verifying

8:30am- Trust in Integrated Circuits

10:00am M. TehranipoorUniv. of Connecticut

10:00am- 10:30amFOYER

T2A - Clock Implementation: A Question of Timing

10:30am-12:00n GM Blair

Avago

Morning - Tutorial TrackB - SUNSET 2

TIB - Wireless NoC as Interconnection Backbone for Multicore Chips:

8:30am- Promises and Challenges

10:00am P. Pande2, A. Nojeh1, A. Ivanov1'Univ. ofBritish Columbia, Canada, 2Washington State Univ.

10:00am-10:30am ^J*"*FOYER

T2B - Carbon Nanotubes and Opportunities for Wireless On-Chip

10:30am- Interconnect

12:00n A. Nojeh1, P. Pande2, A. Ivanov11 9

Univ. ofBritish Columbia, Canada, Washington State Univ.

nAn A1 OALunch Break

12:00noon-01:30pmSPICEMARKETBUFFET

Afternoon - Tutorial Track A - SUNSET 1

T3A - Design and Management of Multiprocessor Svstem-on-Chips

1:30pm - 3:00pm U. Y. OgrasArizona State Univ.

r> r\r\ o ->nCoffee Break

3:00pm-3:30pmFQYER

T4A - Svstein-on-Chip Design Using Tri-Gate Technology

3:30am-5:00pm A. MarshallUniv. of Texas in Dallas

Afternoon - Tutorial Track B - SUNSET 2

1:30pm- T3B - Recent Advancements in Fiber Optic Transmission Enabled by Highly

3:00pm Integrated Mixed Signal SoC and Advanced Digital Signal Processing

xv

H. Sun

Infinera

o aa- oCoffee Break

3:00pm-3:30pmFQYER

T4B - Formal Verification in Svstem-on-Chip Design; Scientific Foundations

3:30am- and Practical Methodology

5:00pm W. Kunz, D. Stoffel, J. UrdahlUniv. ofKaiserslautem, Germany

Day 2: Wednesday, September 3,2014

7J, A nf. Registration/:43am - 4:uupm ^q^^IONDESK

8:30am -11:55am Session WPL - Opening Session, KeyNote and Plenary - WILSHIRE A&B

Chair: Kaijian Shi, Cadence Design SystemsCo-Chair: Thomas Buechner, IBM

09 00am - 09-15amWelcome

Kaijian Shi, Cadence Design Systems, General Chair

Technical Program Overview

09:15am -09:30am Thomas Buechner, IBM, Technical Program Chair

DanellaZhao, Univ. ofLouisiana, Technical Program Co-Chair

09 30 -10 30amKevnote: "Tpe Internet of Everv-Thing; EDA Perspectives" 2

Tom Beckley, Senior Vice President ofR&D, Cadence Design Systems, Inc.

10:30am- 10:45am Coffee Break (Sponsored by Cadence Design Systems)

1045am-"SoCs for Mobile Applications: Systems from 0 MPH to over 100 MPH" 3

t' Scott Runner, VP ofadvanced methodologies and low-power design,11 :4oam

^ T

Qualcomm

n A* _mLunch Break

li-zuam ur.jupmSPICEmarketBUFFET

1:30pm - 2:45pm Session WP1A - Low Power Circuits - SUNSET 1Chair: Gururaj Shamanna, Intel

Co-Chair: Yuejian Wu, Infinera

WP1A-1 Low-Power High-Speed On-Chip Asynchronous Wave-pipelined CML

SerDes 5

Ashok Jaiswal, DominikWalk, Yuan Fang, Klaus HofmannTechnische Universitaet Darmstadt, Germany

WP1A-2 APower Efficient Reconfigurable Svstem-in-Stack: 3D Integration of

j.55Accelerators. FPGAs. and DRAM 11

Peter Gadfort1, AravindDasu', AHAkoglu2, YoonLeow2, Michael Fritze1!USC Information Sciences Institute, 2University ofArizona

WP1A-3 Variation-Aware Flip-Flop Energy Optimization for Ultra Low Voltage

2:20pm Operation 17Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

1:30pm

xvi

Kyoto University, Japan

1:30pm - SessionWP1B - Embedded Systems, Multi/Many Core Systems and Embedded

2:45pm Memory Technologies - SUNSET 2Chair: Ram Krishnamurthy, IntelCo-Chair: Oliver Sander, Karlsruhe Institute of Technology, Germany

WP1B-1 Multilayer Layer Graphene Nanoribbon Flash Memory:Analysis of

l-30omProgrammmg an

WP2B-2 Adaptive Multicast Routing Method for 3D Mesh-based Networks-on-

3.30DmChip. 70

" ^ Poona Bahrebar, Azarakhsh Jalalvand, Dirk Stroobandt

Ghent University, Belgium

WP2B-3 Thermal-Aware Memory Management Unit of 3D-Stacked DRAM for 3D

« High Definition (HP) Video 76pm

Chih-Yuan Chang, Po-Tsang Huang, Yi-ChunChen, Tian-Sheuan Chang, Wei HwangNational Chiao Tung University, Taiwan

4:45pm -6:15pm Poster session and reception (food and drinks) - LONDON CLUB

Chair: Thomas Buechner, IBMCo-Chair: Danella Zhao, Univ. ofLouisiana

PI Design of a 9-bit lGS/s CMOS Folding AID Converter with a Boundary Error

Reduction Technique. 83

Jongyoon Hwang1, Dongjoo Kim1, Munkyo Lee2, Sunphil Nah3, Minkyu Song1'DongguLUniv, Samsung Thales.CO.Ltd, 3Agency for Defense Development, Korea

P2 Design of a Low Power CMOS lObit Flash-SAR ADC 88

Gi-Yoon Lee andKwang-Sub YoonInha university, Korea

P3 A Systematic Methodology to Design High Power Terahertz and Millimeter-Wave

Amplifiers 92

Siavash Moghadami1, Farzaneh JalaliBidgoli2, Shahab Ardalan1!San Jose State University, 2AmirKabir University of Technology, Iran

P4 A Clock Generator Based on Multiplying Delay-Locked Loop 98

Chorng-Sii Hwang, Ting-Li Chu, Wen-Cheng ChenNational Yunlin University of Science and Technology, Taiwan

P5 ANew Design Methodology for Voltage-to-Time Converters (VTCs) Circuits suitable

for Time-Based Analog-to-Digital Converters fT-ADO 103

M. Wagih Ismail andHassan Mostafa'Cairo University, 2AUC and Zewail City of Science and Technology, Egypt

P6 Reducing the Turn-On Time and Overshoot Voltage for a Diode-Triggered Silicon-

Controlled Rectifier during an Electrostatic Discharge Event 109

Ahmed Ginawi1, Tian Xia1, Robert Gauthier2

'University ofVermont, 2JJBM

P7 Electromvograph Data Acquisition and Application using Cypress Programmable

System on Chip 115

Dhirendra Mehta, Shreyas Dome, Shreeyash Salunke, Keval Shah, Rishikesh DhamapurkarVeermata Jijabai Technological Institute (VJTI), India

P8 Microcells for ICA-SOC for Remote Sensing of High Energy Radiation 119

Vijay Jain

University of South Florida

P9 A Low Supply Voltage Mixed-Signal Maximum Power Point Tracking Controller for

Photovoltaic Power System 125 '

Jun-Hua Chiang, Bin-Da Liu, Shih-Mng Chen, Hong-Tzer YangNational Cheng Kung University, Taiwan

xviii

P10 Design and Implementation of Novel Source Synchronous interconnection in modern

GPU Chips 130

Tao Li and Greg Sadowski2'AMD, China,2AMD, BoxboroughPI 1 PVT-Aware Digital Controlled Voltage Regulator Design for Ultra-Low-Power (ULP)

DVFS Systems 136

Pei-Chen Wu1, Yi-PingKuo1, Chung-Shiang Wu1, Ching-Te ChuangYuan-Hua Chu2, WeiHwang1'National Chiao Tung University, 2Industrial Technology Research Institute, Taiwan

P12 MITH-Dvn : A Multi Vth Dynamic Logic Design Style Using Mixed Mode FinFETs 140

Ramesh Nair and Ranga Vemuri

University of Cincinnati

P13 Towards Platform Level Power Management in Mobile Systems 146

DavidKadjo , UmitOgras, RaidAyoub , Micheal Kishinevsky , PaulGratz1'Texas A&M University, 2Arizona State University, 3Intel Corporation

P14 Analysis of the Current-Voltage Characteristics of Silicon on Ferroelectric Insulator

Field Effect Transistor (SOF-FET) 152

Azzedin Es-Sakhi andMasud ChowdhuryUniversity ofMissouri - Kansas City

P15 Multichannel Tunneling Carbon Nanotube Field Effect Transistor (MT-CNTFET) 156

Azzedin Es-Sakhi and Masud ChowdhuryUniversity of Missouri - Kansas City

P16 A Low Power Charge Sharing Hierarchical Bitline and Voltage-Latched Sense

Amplifier for SRAM Macro in 28 nm CMOS Technology 160

Chi-Hao Hong', Yi-WeiChiu', Jun-Kai Zhao1, Shyh-Jye Jou1, Wen-Tai Wang2, ReedLee2'National Chiao Tung University, 2Glpbal Unichip Corporation, Taiwan

P17 Networks On Chip Design for Real-Time Systems 165

Ali Mahdoum

Centre de Developpement des Technologies Avancees, Algeria

P18 Comparison Between Optimal Interconnection Network in Different 2D and 3D NoC

Structures 171

Farzad Radfar, Masoud Zabihi, RezaSarvariSharifUniversity of Technology, Iran

P19 Flow control solution for efficient communication and congestion avoidance in NoC 177

Ahmed Aldammas, Adel Soudani, Abdullah Al-Dhelaan

King Saud University, Saudi Arabia

P20 Run-Time Voltage Detection Circuit for 3-D IC Power Delivery 183

Divya Pathak andIoannis SavidisDrexel University

P21 Collision Array Based Workload Assignment for Network-on-Chip Concurrency 188

He Zhou, Linda Powers, Janet Roveda

University ofArizona

xix

P22 On Circuit Design of On-Chip Non-Blocking Interconnection Networks 192

Yikun Jiang and Mei Yang

University of Nevada, Las Vegas

P23 Hardware Architecture of an Internet Protocol Version 6 Processor 198

Boris Traskav1, Ulrich Langenbach2, Klaus Hofinann1, Peter Gregorius2^echnische Universitaet Darmstadt, 2Fraunhofer Institute, HHI, Germany

P24 Flexible Reconfigurable Architecture for DSP Applications 204

Abdulfattah Obeid1, Syed Manzoor Qasim1, Mohammed S. BenSaleh1, ZiedMarrakchi2, HabibMehrez2, Heni Ghariani3, MohamedAbid3'KACST, Saudi Arabia, 2LIP6, University ofPierre and Marie Curie, France, 3CES, University ofSfax, Tunisia

P25 Very fast co-simulation model and accurate on-the-flv performance estimation

methodology for heterogeneous MPSoC 210

Nicolas Serna and Francois Verdier

Univ. Nice Sophia Antipolis, France

„ m nnV - The Ultimate Variety Show (Sponsored by Aldec)

8:30pm- 10:00pm :

Day 3: Thursday, September 4,2014

8:00am -4.00pm f^f9:00am - 11:10am Session TPL - Thursday Keynote and Plenary Speech - WILSHIRE A&B

Chair: Kaijian Shi, Cadence Design Systems

9 00am -Keynote: "The Future of Memory/Logic Technologies and Computing

10 00amSystem Architectures" 217

J. Thomas Pawlowski, Fellow and Chief Technologist, Micron Technology, Inc.

Plenary: "The Next Generation of Scale-Out Server Architecture : Building

10:00am- the QpenPOWER" 219

10:55am Jeffrey D. Brown, DistinguishedEngineer, Emerging Product Development andHardware Architect, SoC, IBM

mcc 11 mCoffee Break

10:55am-11:10amF0Y£R

11:10am - Session TA1A - Design Track: Power Management and Optimization -

12:10pm SUNSET 1

Chair: Haibo Wang, Southern Illinois UniversityCo-Chair: Karan Bhatia, Texas Instruments

TAlA-l Changing power optimization for finFet technology N/A

11:10am GerardMBlair and BruceE Zahn

Avago Technologies

TAlA-2 Module-Based Bus Gating Methodology in Low Power SoC Design N/A

11:30am ZheGe, Jinglin Zhang, MiaolinTanFreescale Semicondutor

xx

TA1A-3 Bus Transaction-Based Frequency and Voltage Regulation N/A

11:50am Zhang Lei, Mei Wangsheng, MengQing, BradHoskinsFreescale Semiconductor

11:10am - 11:50am Session TA1B - Design Track: Memory and DSP Applications -SUNSET2Chair: Mark Schrader, Schrader Consulting (m.schrader@ieee-socc.org')

TA1B-1 High Performance Fault Tolerant Memory Management Unit for Space

ni0amApplications N/A

Xiaofang Chen, Tianfang Niu, Sharon LimST Electronics (Satellite Systems), Singapore

TA1B-2 Development of a system with DSP technology for enhancing electronic

1130ampose Performance N/A

Cristhian Manuel Durdn Acevedo andIsaac Torres LopezPamplona University, Colombia

11 ia m /inLunch Break

12:10pm-01:40pmSPICE j^rketBUFFET

1:40pm - 3:20pm Session TP1A - Data Converters - SUNSET 1Chair: Poki Chen, National Taiwan University of Science and TechnologyCo-Chair: Danella Zhao, Univ. ofLouisiana

TP1A-1 An All-Digital On-Chip Abnormal Temperature Warning Sensor for

jDynamic Thermal Management 221

pChing-Che Chung and Jhih-Wei LiNational Chung Cheng University, Taiwan

TP1A-2 Time Stretcher for a Time-to-Digital Converter with a Precisely Matched

2_Q5Current Mirror 225

^Muhammad Tanveer, JohanBorg, Jonny JohanssonLulea Technical University, Sweden

TP1A-3 A 10-Bit 250MS/S Low-Glitch Binary-Weighted Digital-to-Analog

2.30pmConverter 231

pFang-Ting Chou and Chung-Chih HungNational Chiao Tung University, Taiwan

TP 1A-4 An Accelerated Successive Approximation Technique for Analog to Digital

Converter Design 236^

Haibo Wang andRam Harshvardhan RadhakrishnanSouthern Illinois University

1:40pm - 3:20pm Session TP IB - Networks on Chip - SUNSET 2Chair: Danella Zhao, Univ. ofLouisianaCo-Chair: Sakir Sezer, Queen's University Belfast

TP 1 B-l An Energy Efficient Wireless Network-on-Chip using Power-Gated

j.40Transceivers 243

^Hemanta Kumar Mondal and Sujay Deb

Indraprastha Institute of Information Technology, India

TP 1 B-2 Heterogeneous Photonic Network-on-Chip with Dynamic Bandwidth

2:05pm Allocation 249AnkitShah, NaseefMansoor, Ben Johnstone, Amlan Ganguly, Sonia Lopez-Alarcon

xxi

Rochester Institute of Technology

TP1B-3 Benefits and Costs of Prediction BasedDVFS for NoCs at Router Level 255

2:30pm Cristinel Ababei' and Nicholas Mastronarde2

'Marquette University, 2University at Buffalo

TP1B-4 Wiring Resom- Minimisation for Phvsicallv-ComplexNetwork-on-Chip

2.55 mArchitectures 261

' pNickvash Kani andAzadNaeemi

Georgia Institute ofTechnology

1:40pm - 3:20pm Session TP1C - System Level Design - SUNSET 3Chair: Sao-Jie Chen, National Taiwan University fs.chen@ieee-socc.org)Co-Chair: Mark Schrader, Schrader Consulting (m.scnrader@ieee-socc.org)

TP 1 C-l A Framework for Specifying, Modeling. Implementation and Verification

4Qof SOC Protocols 268

" pm Shahidlkram, IsamAkkawi, Jack Perveiler, DavidAsher, Jim Ellis

Cavium Networks

TP1C-2 Reliability Aware Logic Synthesis through Rewriting 274

„ neSatish Grandhi', Christian Spagnol1, Jiaoyan Chen1, Emanuel Popovici1, Sorin

2:05Pm Cotafona2'University College Cork, Ireland, 2University ofTechnology, Delft, The Netherlands

TP1C-3 Solar-Supercapacitor Harvesting System Design for Energy-Aware Applications 280

2:30pm Moeen Hassanalieragh, TolgaSoyata, Andrew Nadeau, GauravSharma

University of Rochester

TP1C-4 Methodology of Exploring ESL/RTL Manv-Core Platforms for Developing

Embedded Parallel Applications 286

2:55pm Jyu-Yuan Lai', Chih-Tsun Huang1, Ting-Shuo Hsu1, Jing-Jia Liou1, Tung-HuaYeh2, Liang-Chia Cheng2, Juin-MingLu2'National Tsing Hua University, 2Industrial Technology Research Institute, Taiwan

i on i ai\Coffee Break

3:20pm - 3:40pmF0YER

3:40pm - 5:20pm Session TP2A - DSP Architectures and Methodologies - SUNSET 1Chair: Tobias Noll, RWTH Aachen University

TP2A-1 Evaluating Mobile SOCs as an Energy Efficient DSP Platform 293

3:40pm Matt Briggs andPayman Zarkesh-Ha

University ofNew Mexico

TP2A-2 New Quantization Error Assessment Methodology for Fixed-Point Pipeline

4n,FFT Processor Design 299

pmChen Yang1, YizhuangXie1, He Chen1, YiDeng2'Beijing Institute ofTechnology, China, Polytechnic Institute and State University,TP2A-3 Energy Scalable Approximate DCT Architecture Trading Quality via

4.30-Boundary Error-resiliency 306

^BharatGarg, NiteshK Bharadwaj, GKSharmaABV-Indian Institute ofInformation Technology and Management, India

4:55pm TP2A-4 Compensating Imperfections in RF-DAC Based Transmitters Using LUT-

xxii

Based Predistortion 312

BastianMohr, Ye Zhang, Jan Henning Mueller, Stefan HeinenRWTH Aachen University, Germany

3:40pm - 5:20pm Session TP2B - Testability and Manufacturability - SUNSET 2Chair: Chris Ryan, Maxim IntegratedCo-Chair: Martin Margala, University of Massachusetts Lowell

TP2B-1 Errors in Solving Inverse Problem for Reversing RTN Effects on VCCmin

3.40pmShift in SRAMReliablitv Screening Test Designs 318

Hiroyuki Yamauchi and Worawit SomhaFukuoka Institute of Technology, Japan

TP2B-2 Cost-Optimal Design of Wireless Pre-bonding Test Framework 324

4:05pm Unni Chandran, DanellaZhao

University of Louisiana at Lafayette

TP2B-3 IP Watermark Verification Based on Power Consumption Analysis 330

4-30omdearie Marchand1, Lilian Bossuet1, EdwardJung2

^ 'Laboratoire Hubert Curien, UMRCNRS 5516, University ofLyon, France, 2Southern

Polytechnic State University

TP2B-4 A Unique Non-intrusive Approach to Non-ATE Based cul-de-sac SoC

Debug 336

4:55pm Vasant Easwaran, Virendra Bansal, GregShurtz, Rahul Gulati, Mihir Mody, PrashantKarandikar, Prithvi Shankar Y.A.

Texas Instruments, India

3:40pm - Session TP2C - Reconfigurable and Programmable Circuits and Systems -

5:20pm SUNSET 3Chair: Oliver Sander, Karlsruhe Institute of TechnologyCo-Chair: Helen Li, University ofPittsburgh

TP2C-1 REFLEX; Reconfigurable Logic for Entropy Extraction 341

3:40pm Vikram Suresh and Wayne Burleson

University ofMassachusetts, Amherst

TP2C-2 A Reconfigurable 0-L1-L2 S-MASH2 Modulator with High-Level Sizing

and Power Estimation 347p AbhilashKNand Srinivas .M.B

BITS Pilani, Hyderabad Campus, India

TP2C-3 A Configurable Packet Classification Architecture for Software-Defined

4.0QNetworking 353

"

Keissy Guerra Perez, XinYang, Sandra Scott-Hayward, SakirSezer

Queen's University Belfast, UK

TP2C-4 A Stochastic Learning Algorithm for Neuromemristive Systems 359

4:55pm Cory Merkel andDhireesha KudithipudiRochester Institute of Technology

*.on„mCoffee Break

5.20pm-5.30pm pqyer

5:30pm-7:00pm Panel Discussion - WILSHIRE A&BChair: Thomas Buechner, IBM

xxiii

The End of the Microprocessor Chip - Will SoCs dominate computing? 366

Panelists:

Jeffrey D. Brown, Distinguished Engineer, Emerging ProductDevelopment andHardware Architect, SoC, IBM

C. Norris Ip, Solutions Group Director, CadenceRam Krishnamurthy, HeadofHigh Performance andLow Voltage Circuits

Group, Intel Labs

Nigel Paver, ARMFellowSakir Sezer, Director ofResearch, ECIT, Queen's University Belfast and CTO,titanic systems

7:00pm - 9:00pm Banquet Dinner - LONDON CLUBChair: Kaijian Shi, Cadence Design Systems

Banquet Speech: "Democratizing the mobile hardware ecosystem: Google's

Project Ara" 369

Paul Eremenko, Director, Project Ara, Google

Day 4: Friday, September 5,2014

8:30am- 11:00am f^f9:00am - 10:15am Session FA1A - Special Session: Memristor-based Processors - SUNSET 1

Chair: Dhireesha Kudithipudi, Rochester Institute of TechnologyCo-Chair: Garrett Rose, Air Force Research Laboratories

FA1A-l On Designing Primitives for Cortical Processors with Memristive

Hardware 371

Dhireesha Kudithipudi1, Cory Merkel1, Yu Kee Ooi1, Qutaiba Saleh1, Garrett S. Rose2'Rochester Institute ofTechnology, 2AFRL

FA1A-2 Emerging Memristor Technology Enabled Next Generation Cortical

Processor 377

HaiLi, MiaoHu1, Xiaoxiao Liu1, MengjieMao1, Chuandong Li2, ShukaiDuan2'University ofPittsburgh, 2Southwest University, ChinaFA1A-3 Energy Efficient Memristor Crossbar Based Multicore NeuromorphicProcessors 383

Tarek Taha, Raqibul Hasan, Chris YakopcicUniversity ofDayton

9:00am - 09:50am Session FA1B - Analog Circuits - SUNSET 2Chair: Poki Chen, National Taiwan University of Science and TechnologyCo-Chair: Hongjiang Song, Intel

FA1B-1 Resistorless On-Die High Voltage Power Supply Noise Measurement 390

9:00am Siddharth Katare, RajDua, Narayanan NatarajanIntel, India

FA1B-2 Design of a Low Power Multistandard Transceiver Chain Based on

9:25am Current-reuse VCO 393

Ye Zhang, Jan Henning Mueller, Muh-Dey Wei, RalfWunderlich, Stefan Heinen

9:00am

9:25am

9:50am

xxiv

RWTH Aachen, Germany

9:50am-10:40am Session FA2B - Verification - SUNSET 2

Chair: Poki Chen, National Taiwan University of Science and Technology

FA2B-1 SoC Scan-Chain Verification Utilizing FPGA-based Emulation Platform

9.50amand SCE-MI Interface 398

Bill Jason Pidlaoan Tomas1, Yingtao Jiang2, Mei Yang2Cadence Inc., 2University ofNevada Las VegasFA2B-2 A New Approach Using Symbolic Analysis to Compute Path-Dependent

1015amEffective Properties Preserving Hierarchy 404

Sridhar Srinivasan, Ellis Cohen, Mark HofinannMentor Graphics Corp.

m ai\ iaccCoffee Break

10:40am-10:55amFQYER

10:55am - 12:10pm Session FA3A - Biomedical Circuits and Systems - SUNSET 1

Chair: Ken Hsu, Rochester Institute ofTechnology (

FA3A -1 A Highly Sensitive ISFET Using pH-to-Current Conversion for Real-

Time DNA Sequencing 410

10:55am Mohammad Uzzal, Payman Zarkesh-Ha, Jeremy Edwards, Ezequiel Coelho, PriyankaRawat

University of New Mexico

FA3A-2 A Neural Rehabilitation Chip with Neural Recording. Spike Detection,

1120amSmite Rate Counter, and Biphasic Neural Stimulator 415

HongjiangSong, Chen Chen, Meng-WeiLin, KaijunLi, JenniferBlain Christen

Arizona State University

FA3A-3 High-Frequencv and Power-Efficiency Ultrasound Beam-Forming

Processor for Handheld Applications 420

11:45am Guo-Zua Wu, Song-Nien Tang, Chih-Chi Chang1, Chien-Ju Lee1, Kuan-Hsien

Lin2, Oscal T.-C. Chen21 Industrial Technology Research Institute, 2National Chung Cheng University, Taiwan

10:55am- Session FA3B - Wireless and wireline communication circuits and

12:10pm methodologies - SUNSET 2Chair: Mark Schrader, Schrader ConsultingCo-Chair: Hongjiang Song, Intel

FA3B-1 ALow Complexity Multi Standard Dual Band CMOS Polar Transmitter

for Smart UtUitv Networks 426

10:55am Jan Henning Mueller, Ye Zhang, LeiLiao, AytacAtac, Zhimiao Chen, Bastion

Mohr, Stefan Heinen

RWTH Aachen University, Germany

FA3B-2 A 25.5mW lOGb/s inductorless receiver with an adaptive front-end in

H.20amQ-13 m CMOS. 431

'Sushrant Monga and2Shouri ChatterjeeCadence AMS Design Systems, 2Indian Institute of Technology, India

11 -45amFA3B-3 A Hardware Acceleration Scheme for Memory-Efficient Flow Processing 437

Xin Yang, Sakir Sezer, Shane O'Neill

xxv

Queen's University Belfast, UK

12:10pm Session FA3C - Advances in SRAMDesign - SUNSET 3

Chair: Norbert Schuhmann, Fraunhofer US

Co-Chair: Sakir Sezer, Queen's University Belfast

FA3C-1 ABody-Bias based Current Sense Amplifier for High- Speed Low-Power

Embedded SRAMs 444

Tahseen Shakir and Manoj Sachdev

University of Waterloo

FA3C-2 Comparative Study of FinFETs versus 22nm Bulk CMOSs: SRAM

Design Perspective 449

Hooman FarJchani1, AH Peiravi1, Jens Madsen Kargaard2, Farshad Moradi2'Ferdowsi University of Mashhad, Iran and 2Aarhus University, Denmark

FA3C-3 A 40nm256Mb 6T SRAMwith Threshold Power-Gating. Low-Swing

Global Read Bit-Line, and Charge-Sharing Write with Vtrip-Tracking and

Negative Source-Line Write-Assists 455

11:45am Chao-Kuei Chung1, Chien-YuLu1, Zhi-Hao Chang1, Shyh-Jye Jou1, Ching-TeChuang1, Ming-Hsien Tu2, Yu-Hsuan Chen2, Yong-Jyun Hu2, Paul-Sen Kan2, Huan-Shun Huang2, Kuen-DiLee2, Yung-Shin Kao2'National Chiao-Tung University, Faraday Technology Corporation, Taiwan

01:00pm-6:00pm Hoover DamTourChair: Venki Muthukumar, University ofNevada Las Vegas

xxvi