System Architecture of Sensor Network Processors Alan Pilecki.
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Transcript of System Architecture of Sensor Network Processors Alan Pilecki.
![Page 1: System Architecture of Sensor Network Processors Alan Pilecki.](https://reader035.fdocuments.us/reader035/viewer/2022072017/56649efe5503460f94c139fa/html5/thumbnails/1.jpg)
System Architecture of Sensor Network Processors
Alan Pilecki
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Outline What is a Sensor Network? What are the requirements of a
processor in a Sensor Network? What design decisions have been
made based on these requirements? What is the current state of the art
in this field? What does the future hold?
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Sensor Networks (1)
Designed for specialized applications including: Habitat monitoring Implanted medical devices (e.g. heart
monitor) Military detection systems
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Sensor Networks (2)
Hardware Specialized processors/coprocessors Radio Transceiver Sensor (e.g. audio, infrared,
temperature, vibration, etc.)
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Requirements
1. Low power consumption = Long life span
2. Self-powered Battery Power harvested from environment (e.g.
solar power, vibration, electro-magnetic radiation)
3. Small in size4. Very reliable / no maintenance
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Low Power Consumption This is the main driving force for the
design of a sensor processor. Ultimate goal is for a deployed sensor
node to provide continuous sensing for years without being touched.
Decisions made to save power may result in slower CCT, acceptable as long as specialized applications need is met.
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Common characteristics (1)
Event Driven Event execution/queue implemented
entirely in HW, eliminating need for OS.
Accelerates processing and dispatching of events.
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Common Characteristics (2)
Modularized specialized hardware. Accelerate common operations. Easily expandable. Allows for more power saving options.
Majority of HW is put to sleep when not actively sensing.
Quick wakeup time.
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SNAP/LE (1) Sensor Network Asynchronous
Processor / Low Energy Asynchronous processor
No clock for sequencing in any component. Synchronization done with a handshaking
protocol between hardware components. Results in extra hardware (Async overhead). Every signal must be without glitches or
switching hazards (no clock to help recover). Results in much lower power consumption.
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SNAP/LE (2) Processor Core
Event queue Instruction fetch Lookup table to map events to their
specific handlers. ISA
As simple as possible Main purpose is to execute event
handlers.
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SNAP/LE (3)
Time coprocessor 3 self-decrementing timers. Used to wake up the system to check
the state of the sensor environment. Message coprocessor
Interface between processor core and the external HW (radio and sensor).
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SNAP/LE (4)
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Features of other Sensor Processors (1) Hardware power leakage
Older technology is used in a lot of cases to minimize inactive power leakage.
Memory power saving: SRAM divided into banks of 256 bytes. Unused portions of memory are gated. Reduces active and leakage power. Resulting in over a 98% power reduction.
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Features of other Sensor Processors (2) Event priority levels
Two inputs to the event scheduler. High priority events can pre-empt low
priority events. General Purpose Processor
Used for uncommon operations. Gives programmer more flexibility. Consumes much more power than
specialized processors.
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Another example
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What does the future hold? Increase lifespan of sensors
Improved battery life (slow developing and expensive)
Harvesting power from the environment
Sensors that can run for long periods of time by recharging their power source from their surroundings.
Will open up the use of sensors to other fields/applications.
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Questions???