Summary Last Lecture

EECS 247 Lecture 25 Pipeline & Oversampled ADCs © 2007 H.K.

EE247Lecture 25

Pipelined ADCs (continued)• How many bits per stage?

– Algorithmic ADCs utilizing pipeline structure– Advanced background calibration techniques

Oversampled ADCs– Why oversampling?– Pulse-count modulation– Sigma-delta modulation

• 1-Bit quantization• Quantization error (noise) spectrum• SQNR analysis• Limit cycle oscillations

EECS 247 Lecture 25 Pipeline & Oversampled ADCs © 2007 H.K. Page 2

Summary Last Lecture

Pipelined ADCs (continued)– Effect gain stage, sub-DAC non-idealities on

overall ADC performance• Digital calibration (continued)• Correction for inter-stage gain nonlinearity

– Implementation • Practical circuits• Combining the digital bits• Stage implementation

–Circuits–Noise budgeting


How Many Bits Per Stage?• Many possible architectures

– E.g. B1eff=3, B2eff=1, ...vs. B1eff=1, B2eff=1, B3eff=1, ...

• Complex optimization problem, fortunately optimum tends to beshallow...

• Qualitative answer:– Maximum speed for given technology

• Use small resolution-per-stage (large feedback factor)– Maximum power efficiency for fixed, "low" speed

• Try higher resolution stages• Can help alleviate matching & noise requirements in stages

following the 1st stageRef: Singer VLSI 96, Yang, JSSC 12/01


14 & 12-Bit State-of-the-Art Implementations

260mW340mWPower

80MS/s75MS/sSpeed

~66dB/75dB~73dB/88dBSNR/SFDR

1-1-1-1-1-1-1-1-1-1-23-1-1-1-1-1-1-1-1-3Architecture

1214Bits

Loloee(ESSIRC 2002)

0.18μ/3V

Yang(JSSC 12/2001)

0.35μ/3V

Reference


10 & 8-Bit State-of-the-Art Implementations

30mW40mWPower

200MS/s125MS/sSpeed

~48dB/56dB~55dB/66dBSNR/SFDR

2.8 -2.8 - 41.5bit/stageArchitecture

810Bits

Kim et al(ISSCC 2005)

0.18μ/1.8V

Yoshioko et al(ISSCC 2005)

0.18μ/1.8V

Reference


Algorithmic ADC

• Essentially same as pipeline, but a single stage is reused for all partial conversions

• For overall Boverall bits need Boverall/Bstage clock cycles per conversion

Small area, slow

T/H sub-ADC(1….6 Bit)

Digital Output

VIN

Residue

DAC

Shift Register& Correction Logicstart of conversion

2B


Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to-Digital Converters

Ref: Y. Chiu, et al, “Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to-Digital Converters,“ IEEE TRANS. CAS, VOL. 51, NO. 1, JANUARY 2004

• Slow, but accurate ADC operates in parallel with pipelined (main) ADC• Slow ADC samples input signal at a lower sampling rate (fs/n)• Difference between corresponding samples for two ADCs (e) used to correct

fast ADC digital output via an adaptive digital filter (ADF) based on minimizing the Least-Mean-Squared error


Example: "A 12-bit 20-MS/s pipelined analog-to-digital converter with nested digital background calibration"

Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration”, IEEE JSSC, vol. 39, pp. 1799 - 1808, Nov. 2004

• Pipelined ADC operates at 20Ms/s @ has 1.5bit/stage• Slow ADC Algorithmic type operating at 20Ms/32=625ks/s• Digital correction accounts for bit redundancy• Digital error estimator minimizes the mean-squared-error


Algorithmic ADC Used for Calibration of Pipelined ADC (continued from previous page)

Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 12-bit 20-MS/s pipelined analog-to-digital converter with nested digital background calibration”, IEEE JSSC, vol. 39, pp. 1799 - 1808, Nov. 2004

• Uses replica of pipelined ADC stage • Requires extra SHA in front to hold residue• Undergoes a calibration cycle periodically prior to being used to calibrate

pipelined ADC


12-bit 20-MS/s Pipelined ADC with Digital Background Calibration


Sampling capacitors scaled:• Input SHA: 6pF• Pipelined ADC: 2pF,0.9,0.4,0.2, 0.1,0.1…• Algorithmic ADC: 0.2pF

Chip area: 13.2mm2

• Area of Algorithmic ADC <20%• Does not include digital

calibration circuitry estimated ~1.7mm2



Without Calibration

|INL|<4.2LSB

WithCalibration

|INL|<0.5LSB

Measurement Results12-bit 20-MS/s Pipelined ADC with Digital Background Calibration




Nyquist rate




Does not include digital calibration circuitry estimated ~1.7mm2

Alg. ADC SNDR dominated by noise


Oversampled ADCs


Analog-to-Digital Converters

• Two categories:– Nyquist rate ADCs fsig

max ~ 0.5xfsampling• Maximum achievable signal bandwidth higher compared

to oversampled type• Resolution limited to max. 12-14bits

– Oversampled ADCs fsigmax << 0.5xfsampling

• Maximum possible signal bandwidth lower compared to nyquist

• Maximum achievable resolution high (18 to 20bits!)


The Case for OversamplingNyquist sampling:

Oversampling:

• Nyquist rate fN = 2B• Oversampling rate M = fs/fN >> 1

fs >2B +δFreqB

Signal

“narrow”transition

SamplerAA-Filter

“Nyquist”ADC DSP

=MFreqB

Signal

“wide”transition

SamplerAA-Filter

OversampledADC DSP

fs

fs fN

fs >> fN??


Nyquist v.s. Oversampled ConvertersAntialiasing

|X(f)|

frequency

frequency

frequency

fB

fB 2fs

fB fs

Input Signal

Nyquist Sampling

Oversampling

fS ~2fB

fS >> 2fB

fs

Anti-aliasing Filter


Oversampling Benefits

• No stringent requirements imposed on analog building blocks

• Takes advantage of the availability of low cost, low power digital filtering

• Relaxed transition band requirements for analog anti-aliasing filters

• Reduced baseband quantization noise power• Allows trading speed for resolution


ADC ConvertersBaseband Noise

• For a quantizer with step size Δ and sampling rate fs :– Quantization noise power distributed uniformly across Nyquist

bandwidth ( fs/2)

– Power spectral density:

– Noise is distributed over the Nyquist band –fs /2 to fs /2

2 2

es s

e 1N ( f )

f 12 f

⎛ ⎞Δ= = ⎜ ⎟

⎝ ⎠

-fB f s /2-fs /2 fB

Ne(f)

NB


Oversampled ConvertersBaseband Noise

B B

B B

f f 2

B ef f s

2B

s

B s2

B0

B B0B B0

ss

B

1S N ( f )df df

12 f

2 f12 f

where for f f / 2

S12

2 f SS S

f Mf

where M oversampling rat io2 f

− −

⎛ ⎞Δ= = ⎜ ⎟

⎝ ⎠

⎛ ⎞Δ= ⎜ ⎟⎜ ⎟

⎝ ⎠

=Δ

=

⎛ ⎞= =⎜ ⎟⎜ ⎟

⎝ ⎠= =

∫ ∫

-fB f s /2-fs /2 fB

Ne(f)

NB


Oversampled ConvertersBaseband Noise

2X increase in M3dB reduction in SB½ bit increase in resolution/octave oversampling

B B0B B0

ss

B

2 f SS S

f Mf

where M oversampling rat io2 f

⎛ ⎞= =⎜ ⎟⎜ ⎟

⎝ ⎠= =

To increase the improvement in resolution: Embed quantizer in a feedback loop

Noise shaping (sigma delta modulation)


Pulse-Count Modulation

Vin(kT) Nyquist ADC

t/T0 1 2

OversampledADC, M = 8

t/T0 1 2

Vin(kT)

Mean of pulse-count signal approximates analog input!


Pulse-Count Spectrum

f

Magnitude

• Signal: low frequencies, f < B << fs• Quantization error: high frequency, B … fs / 2• Separate with low-pass filter!


Oversampled ADCPredictive Coding

• Quantize the difference signal rather than the signal itself• Smaller input to ADC Buy dynamic range• Only works if combined with oversampling• 1-Bit digital output• Digital filter computes “average” N-Bit output

+

_vIN

DOUT

Predictor

ADCTo Digital Filter


Oversampled ADC

Decimator:• Digital (low-pass) filter• Removes quantization error for f > B• Provides anti-alias filtering for DSP• Narrow transition band, high-order• 1-Bit input, N-Bit output (essentially computes “average”)

fs= MfN

FreqB

Signal“wide”

transition

SamplerAnalogAA-Filter

E.g.Pulse-CountModulator

Decimator“narrow”transition

fs1= M fN

DSP

Modulator DigitalAA-Filter

fs2= fN+ δ

1-Bit Digital N-BitDigital


Modulator (AFE)

• Objectives:– Convert analog input to 1-Bit pulse density stream– Move quantization error to high frequencies f >>B– Operates at high frequency fs >> fN

• M = 8 … 256 (typical)….1024• Since modulator operated at high frequencies need to

keep circuitry “simple”

ΣΔ = ΔΣ Modulator


Sigma- Delta Modulators

Analog 1-Bit ΣΔ modulators convert a continuous time analog input vIN into a 1-Bit sequence DOUT

H(z)+

_VIN

DOUT

Loop filter 1b Quantizer (comparator)

fs

DAC


Sigma-Delta Modulators• The loop filter H can be either switched-capacitor or continuous time• Switched-capacitor filters are “easier” to implement + frequency

characteristics scale with clock rate• Continuous time filters provide anti-aliasing protection• Loop filter can also be realized with passive LC’s at very high frequencies

H(z)+

_VIN

DOUT

fs

DAC


Oversampling A/D Conversion

• Analog front-end oversampled noise-shaping modulator• Converts original signal to a 1-bit digital output at the high rate of

(2MXB)• Digital back-end digital filter (decimation)

• Removes out-of-band quantization noise• Provides anti-aliasing to allow re-sampling @ lower sampling rate

1-bit@ fs

n-bit@ fs /M

Input Signal Bandwidth

B=fs /2MDecimation

Filter

Oversampling Modulator

(AFE)

fs

fs = sampling rateM= oversampling ratio

fs /M


1st Order ΣΔ ModulatorIn a 1st order modulator, simplest loop filter an integrator

+

_VIN DOUT∫

H(z) =z-1

1 – z-1

DAC


1st Order ΣΔ ModulatorSwitched-capacitor implementation

VIN

-

+

φ1 φ2 φ2

1,0DOUT

+Δ/2

-Δ/2

– Full-scale input range Δ– Note that Δ here is different from Nyquist rate ADC Δ (1LSB)


1st Order ΔΣ Modulator

• Properties of the 1st order modulator:– Maximum analog input range is equal to the DAC reference– The average value of DOUT must equal the average value of VIN

– +1’s (or –1’s) density in DOUT is an inherently monotonic function of VIN To 1st order, linearity is not dependent on component matching

– Alternative multi-bit DAC (and ADCs) solutions reduce the quantization error but loose this inherent monotonicity & relaxed matching requirements

+

_VIN

DOUT

∫-Δ/2≤VIN≤+Δ/2

DAC-Δ/2 or +Δ/2


1st Order ΣΔ Modulator

Instantaneous quantization error

Tally of quantization error

1-Bitquantizer

1-Bit digital output stream,

-1, +1

Implicit 1-Bit DAC+Δ/2, -Δ/2

(Δ = 2)

Analog input-Δ/2≤Vin≤+Δ/2

3Y

2Q

1X

Sine Wave

z -1

1-z -1Integrator Comparator

• M chosen to be 8 (low) to ease observability


1st Order Modulator Signals

T = 1/fs = 1/ (M fN)

X analog inputQ tally of q-errorY digital/DAC output

Mean of Y approximates XThat is exactly what the digital filter does

0 10 20 30 40 50 60

-1.5

-1

-0.5

0

0.5

1

1.5

Time [ t/T ]

Am

plitu

de

1st Order Sigma-DeltaXQY


ΣΔ Modulator Characteristics• Inherently linear for 1-Bit DAC

• Quantization noise and thermal noise (KT/C) distributed over –fs /2 to +fs /2

Total noise within signal bandwidth reduced by 1/MRequired capacitor sizes x1/M compared to nyquist rate ADCs

• Very high SQNR achievable (> 20 Bits!)

• To first order, quantization error independent of component matching

• Limited to moderate & low speed


Output Spectrum• Definitely not white!

• Skewed towards higher frequencies

• Notice the distinct tones

• dBWN (dB White Noise) scale sets the 0dB line at the noise per bin of a random -1, +1 sequence

Input

0 0.1 0.2 0.3 0.4 0.5-50

-40

-30

-20

-10

0

10

20

30

Frequency [ f /fs]

Am

plitu

de

[ dB

WN

]


Quantization Noise Analysis

• Sigma-Delta modulators are nonlinear systems with memory difficult to analyze directly

• Representing the quantizer as an additive noise source linearizes the system

Integrator

ΣQuantizer

Model

QuantizationError e(kT)

x(kT) y(kT)Σ1

1H( )1

zzz

−

−=−


Signal Transfer Function

( )

1

1

0

( )1

zH zz

H jjωωω

−

−=−

=

Signal transfer function low pass function:

IntegratorH(z)Σ

x(kT)y(kT)

-

Frequency

Mag

nitu

de

f0

( )

( )0

1

1 1

( ) ( ) Delay( ) 1 ( )

Sig

Sig

H j s

Y z H zH z zX z H z

ωω

−

=+

= = = ⇒+


Noise Transfer FunctionQualitative Analysis

22

0n

fv f⎛ ⎞× ⎜ ⎟⎝ ⎠

Σvi

-vo0

jωω

22 2

0eq n

fv v f⎛ ⎞= × ⎜ ⎟⎝ ⎠

Σvi -vo0

jωω

Frequencyf0

2nv

Σvi

-vo0

jωω

2 2

0eq n

fv v f⎛ ⎞= × ⎜ ⎟⎝ ⎠

• Input referred-noise zero @ DC (s-plane)

2eqv


STF and NTF

Signal transfer function:

1( ) ( )STF Delay( ) 1 ( )

Y z H z zX z H z

−= = = ⇒+

Noise transfer function:

erentiator Diff 1)(1

1)()(NTF 1 ⇒−=

+== −z

zHzEzY

Integrator

ΣQuantizer

Model

QuantizationError e(kT)

x(kT) y(kT)1

1H( )1

zzz

−

−=− Σ


Noise Transfer Function

( )( )

( ) ( )

( )

1

/2 /2/2

/2

/2 /2

/2

( ) 1 1 set( ) 1 ( )

( ) (1 )=2 2

2 sin / 2

2 sin /2

2sin /2

where 1/Thus: ( ) =2 sin / 2 =2 sin /

j T

j T j Tj T j T

j T

j T j

j T

s

Y zNTF z z eE z H z

e eNTF j e e

e j T

e e T

T e

T f

NTF f T f

ω

ω ωω ω

ω

ω π

ω π

ω

ω

ω

ω

ω π

−

−− −

−

− −

− −

⎛ ⎞⎜ ⎟⎜ ⎟⎝ ⎠

⎡ ⎤⎣ ⎦

⎡ ⎤⎣ ⎦

= = = − =+

−= −

=

= ×

=

=

( )

2

( ) ( ) ( )

s

y e

f

N f NTF f N f=


First Order ΣΔ ModulatorNoise Transfer Characteristics

Noi

se S

hapi

ng F

unct

ion

frequency

fB fN fs /2

First-Order Noise Shaping

Low-passDigital Filter

Key Point:Most of quantization noise pushed out of frequency band of interest

( )

2

2

( ) ( ) ( )

4 sin / ( )

y e

s e

N f NTF f N f

f f N fπ

= ⋅

= ⋅


First Order ΣΔ ModulatorSimulated Noise Transfer Characteristic

0 0.1 0.2 0.3 0.4 0.5

-40

-30

-20

-10

0

10

20

Frequency [f /fs]

Am

plitu

de

[ dB

WN

]

Simulated output spectrumComputed NTF

Signal

( ) 2( ) 4 sin /y sN f f fπ=

• Confirms assumption of quantization noise being white at insertion point


Quantizer Error• For quantizers with many bits

• Let’s use the same expression for the 1-Bit case

• Use simulation to verify validity

• Experience: Often sufficiently accurate to be useful, with enough exceptions to be very careful

( )12

22 Δ=kTe


First Order ΣΔ ModulatorIn-Band Quantization Noise

( )( ) ( )

( ) ( )

( )

2

2

2

1

2 2

2

2 2

2 2

3

1

sin / 1

1 2sin12

13 12

jfT

fsM

fsM

s

B

Y Q z eB

s

Y

NTF z z

NTF f 4 f f for M

S S f NTF z df

fT dff

SM

π

π

π

π

−

−

=−

= −

= >>

=

Δ≅

Δ→ ≈

∫

∫


Dynamic Range

M DR16 33 dB32 42 dB

1024 87 dB

2

2 2

3

32

32 2

full-scale signal power10log 10loginband noise power

1 sinusoidal input, 12 2

13 129

29 910log 10log 30log

2 2

3.

X

Y

X

Y

X

Y

SDRS

S STF

SM

S MS

DR M M

DR

π

π

π π

⎡ ⎤⎡ ⎤= = ⎢ ⎥⎢ ⎥⎣ ⎦ ⎣ ⎦

Δ⎛ ⎞= =⎜ ⎟⎝ ⎠

Δ=

=

⎡ ⎤ ⎡ ⎤= = +⎢ ⎥ ⎢ ⎥⎣ ⎦ ⎣ ⎦

= − 4 30logdB M+ +

2X increase in M 9dB (1.5-Bit) increase in dynamic range


Oversampling and Noise Shaping• ΣΔ modulators have interesting characteristics

– Unity gain for input signal VIN– Large in-band attenuation of quantization noise injected at quantizer

input– Performance significantly better than 1-Bit noise performance possible

for frequencies << fs

• Increase in oversampling (M = fs/fN >> 1) improves SQNR considerably– 1st order ΣΔ: DR increases 9dB for each doubling of M– To first order, SQNR independent of circuit complexity and accuracy

• Analysis assumes that the quantizer noise is “white”– Not true in practice, especially for low-order modulators– Practical modulators suffer from other noise sources also

(e.g. thermal noise)


DC Input• DC input A = 1/11

• Doesn’t look like spectrum of DC at all

• Tones frequency shaped the same as quantization noise

More prominent at higher frequencies

Seems like periodic quantization “noise”

0 0.1 0.2 0.3 0.4 0.5

-40

-20

0

20

Frequency [ f /fs ]

Am

plitu

de

[ dB

WN

]


Limit Cycle Oscillation

-111+110-19+18-17+16-15+14-13+12+11

DC input 1/11 Periodic sequence:

0 10 20 30 40 50

-0.4

-0.2

0

0.2

0.4

Time [t/T]

Out

put

First order sigma-delta, DC input


1st Order ΣΔLimit Cycle Oscillation

In-band spurious tone with f ~ DC input level

• Problem: quantization noise becomes periodic in response to low level DC inputs & could fall within passband of interest!

• Solution:Use dithering (inject noise-like signal at the input ): randomizes quantization noise- If circuit thermal noise if large enough acts as dither

Second order loop

Noi

se S

hapi

ng F

unct

ion

FrequencyfB fN fs /2

First-Order Noise Shaping


1st Order ΣΔ ModulatorLinearized Model Analysis

( )1 1( ) ( ) 1 ( ) Y z z X z z E z− −= + −LPF HPF


2nd Order ΣΔ Modulator

• Two integrators in series• Single quantizer (typically 1-bit)• Feedback from output to both integrators• Tones less prominent compared to 1st order


2nd Order ΣΔ ModulatorLinearized Model Analysis

( )

( )1 1 2

21 1 1

Recursive drivation: 2

Using the delay operator : ( ) ( ) 1 ( )

n n n n nY X E E E

z Y z z X z z E z

− − −

− − −

= + − +

= + −

LPF HPF


2nd Order ΣΔ ModulatorIn-Band Quantization Noise

( ) ( )( )

( )

21

2

44

1

2 sin / for 1s

NTF z z

NTF f

f f Mπ

−= −

=

= >>

( ) ( )

( )

2

2

2

2

24

4 2

5

1 2sin12

15 12

jfT

fsM

fsM

B

Y Q z eB

s

S S f NTF z df

fT dff

M

π

π

π

−

=−

=

Δ≅

Δ≈

∫

∫


Quantization Noise2nd Order ΣΔ Modulator vs 1st Order Modulator

4 2

51

5 12YSM

π Δ≈

2 2

31

3 12YSM

π Δ≈

Noi

se S

hapi

ng F

unct

ion

FrequencyfB fs /2

1st Order Noise Shaping

Ideal Low-passDigital Filter

2nd -Order Noise Shaping


2nd Order ΣΔ Modulator Dynamic Range

M DR (2nd) DR (1st)16 49 dB 33dB32 64 dB 42dB

1024 139 dB 87dB

2

4 2

5

54

54 4

full-scale signal power10log 10loginband noise power

1 sinusoidal input, 12 2

15 1215

215 1510log 10log 50log

2 2

X

Y

X

Y

X

Y

SDRS

S STF

SM

S MS

DR M M

DR

π

π

π π

⎡ ⎤⎡ ⎤= = ⎢ ⎥⎢ ⎥⎣ ⎦ ⎣ ⎦

Δ⎛ ⎞= =⎜ ⎟⎝ ⎠

Δ=

=

⎡ ⎤ ⎡ ⎤= = +⎢ ⎥ ⎢ ⎥⎣ ⎦ ⎣ ⎦

= 11.1 50logdB M− +

2X increase in M 15dB (2.5-bit) increase in DR


2nd Order vs 1st Order ΣΔ Modulator Dynamic Range

8.6 bit87dB (14.2bit)139 dB (22.8bit) 1024

6.8 bit68.8dB (11.1bit)109 dB (17.9bit) 256

3.6 bit42dB (6.7bit)64 dB (10.3bit) 32

2.6 bit33dB (5.2bit)49 dB (7.8bit) 16

Resolution Difference

1st OrderDR

2nd OrderDR

M

– Note: For higher oversampling ratios resolution of 2nd order modulator significantly higher compared to 1st order


2nd Order ΣΔ Modulator Example

M 256=28 to allow some margin so that thermal noise dominants & provides dithering & also choice of M power of 2 ease of digital filter implementation

Sampling rate (2x20kHz + 5kHz)M = 12MHz (quite reasonable!)

• Digital audio applicationSignal bandwidth 20kHzDesired resolution 16-bit

min

16 98 Dynamic Range

11.1 50log153

bit dB

DR dB MM

− →

= − +=


Limit Cycle Tones in 1st Order & 2nd Order ΣΔ Modulator

• Higher oversampling ratio

lower tones

• 2nd order much lower tones compared to 1st

• 2X increase in M decreases the tones by 6dB for 1st order loop and 12dB for 2nd order loop

Ref: B. P. Brandt, et al., "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp. 618 - 627, April 1991.R. Gray, “Spectral analysis of quantization noise in a single-loop sigma–delta modulator with dc input,” IEEE Trans. Commun., vol. 37, pp. 588–599, June 1989.

6dB

12dB 2nd Order ΣΔ Modulator

1st Order ΣΔ Modulator

Inband Quantization noise

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