Study for Mechanical Stress Impact in Scaled...

Study for Mechanical Stress Impact in Scaled MOSFETs

Nuo Xu, Lynn Wang, Xin Sun, Prof. Andrew Neureuther, Prof. Tsu-Jae King Liu

Electrical Engineering and Computer Sciences Department

University of California at Berkeley

03/10/2010

Introduction

*L.-T. Pang et al., 2006 Symp. VLSI Circuits

• Systematic Transistor Variations

S. E. Thompson, TED, 25, 191 (2004)

Intel 90nm HP Tech.

C.-H. Jan et al, IEDM, (2008)

NMOSFET PMOSFET

Intel 45nm LP Tech.

SiGe

CESL CESL

• Uniaxial Stress Technology is

already in production since…

A. Khakifirooz et al, IEDM, (2007)D. Chanem et al,2005 Symp. VLSI Tech.

• MOSFET Performance is Largely Improved

Outline

• Introduction

• Fast-models for Stress-induced Variations

• Injection Velocity Model for Strained MOSFET

• 3D Stress Design for Multigate FET

Stress-Layout Dependence The Impact of Process-induced Stress Variations on MOSFET:

SPICE/Compact models: Adjust mobility and threshold voltage empirically

by fitting a few layout parameters:

Models are too simplistic, do not capture all layout parameter effects

TCAD simulations: numerical (FEM) analysis to determine full stress

profiles in the transistor

Computationally expensive

Need a fast, accurate method for determining channel stress profile, for

accurate estimation of transistor performance

BSIM Stress Models

NMOS PMOS

TCAD Simulation from Synopsis

Flamant Solution

• Analytical solution to concentrated force problems in an infinite

large planeY

X

rr1 r2

Active

Channel

Point Source

(0,0)

-0.06 -0.04 -0.02 0.00 0.02 0.04 0.0610

2

103

104

Str

es

s X

X (

Pa

)

Distance from channel centre (um)

Lg = 40nm

Tox = 1nm

spacing (to channel centre): 90nm

Initial stress: Tensile 2GPa

stressor thickness: 60nm

stressor area: 2nmx2nm

numerical TCAD

analytical model

Gate Edge

Actual:

Stress contoursσx and σy distributions

Classical:

Simulation Approach

point-source stressor

1. Perform 3-D TCAD

simulations to determine the

channel stress profiles (σXX,

σYY) induced by a point

source in the source/drain

region

2. Fit analytical models to the

simulated stress profiles

3. Integrate point-source

contributions to obtain the full

channel stress profiles

Point-source Stress Function

-0.02 -0.01 0.00 0.01 0.02

500

1000

1500

2000

2500

3000

3500

4000

S

tre

ss

XX

(P

a)

Position along Channel Length (um)

Y=0nm

Y=10nm

Y=50nm

Model

-0.2 -0.1 0.0 0.1 0.2

0

300

600

900

1200

1500

1800

2100

Position along Channel Width (um)

Str

es

s X

X (

Pa

)

X=15nm

X=10nm

X=0nm

Model

𝑆1 =𝑆𝑥𝑥 ,0

𝑟𝛼 sin3 𝜃

𝑆2 = 𝑆𝑥𝑥′

1

𝑟1𝛽𝑒−𝑥𝐿0 +

1

𝑟2𝛽𝑒𝑥𝐿0

F.S. Term:

Correc. Term:

Stress XX

Y

X

0 10 15

50

10

0

Y

X

-18 0 18

50

0

Stress YY

𝑆1 =𝑆𝑦𝑦 ,0

𝑟𝛼 cos3 θ −

𝑆𝑦𝑦′

𝑟𝛽 sin3 𝜃

𝑆2 =

𝑆𝑦𝑦

"

𝑟0 𝑒

𝑥𝐿0 𝑟𝑖𝑔𝑕𝑡 𝑠𝑖𝑑𝑒

𝑆𝑦𝑦"

𝑟0 𝑒

−𝑥𝐿0 𝑙𝑒𝑓𝑡 𝑠𝑖𝑑𝑒

F.S. Term:

Correc. Term:

-0.2 -0.1 0.0 0.1 0.2

-200

-100

0

100

200


Str

es

s Y

Y (

Pa

)

X=18.5 nm

X=-18 nm

X=0 nm

Model

-0.02 -0.01 0.00 0.01 0.02

-200

-100

0

100

200

300

400

500


Str

es

s Y

Y (

Pa

)

Y=0nm

Y=50nm

Model

Channel Length (um)

Ch

an

nel W

idth

(um

)

a) b)

Superposition

in the channel

Stress XX Stress YY

Channel Stress Profiles

Impact from STI

-0.10 -0.05 0.00 0.05 0.10

100M

200M

300M

400M

500M

Stress YY

Str

es

s V

alu

es

(P

a)


STIV = 0nm

STIV = 50nm

STIV = 100nm

STIV = 200nm

Stress XX

-0.10 -0.05 0.00 0.05 0.10

50.0M

100.0M

150.0M

200.0M

250.0M

300.0M

350.0M

400.0M

450.0M

500.0M

Str

es

s V

alu

es

(P

a)


0nm

50nm

100nm

150nm Stress YY

Stress XX

-0.15 -0.10 -0.05 0.00 0.05 0.10 0.15

360M

390M

420M

450M

480M

510M

Model

STIP=100nm, STIV=100nm



Str

es

s X

X (

Pa

)

Distance along Channel Width (um)

-0.02 -0.01 0.00 0.01 0.02300M

400M

500M

600M

700M

800M

900M

1G

Str

es

s X

X (

Pa

)

Distance along Channel Length (um)

Model




Channel Length (um)

Ch

an

nel

Wid

th (

um

)

a) b)

LOD = 0.5um; W = 0.3um; Lg = 40nm

STIP = 0.1um; STIV = 0.1um

CESL 2GPa Tensile

Stress XX Stress YY

Model Verification with TCAD-1

• LOD Impact

-0.02 -0.01 0.00 0.01 0.02

300M

400M

500M

600M

700M

800M

900M

1G

Str

es

s X

X (

Pa

)


LOD = 700nm

LOD = 500nm

LOD = 300nm

Model

-0.15 -0.10 -0.05 0.00 0.05 0.10 0.1570M

80M

90M

100M

110M

120M

130M

Str

es

s Y

Y (

Pa

)


LOD = 300nm

LOD = 500nm

LOD = 700nm

Model

-0.02 -0.01 0.00 0.01 0.0250M

100M

150M

200M

250M

300M

350M

400M

450M

Str

es

s Y

Y (

Pa

)


LOD = 300nm

LOD = 500nm

LOD = 700nm

Model

-0.15 -0.10 -0.05 0.00 0.05 0.10 0.15

280M

320M

360M

400M

440M

480M

520M

Str

es

s X

X (

Pa

)


LOD = 700nm

LOD = 500nm

LOD = 300nm

Model

Model Verification with TCAD-2

• Channel Width Impact

-0.02 -0.01 0.00 0.01 0.02

300M

400M

500M

600M

700M

800M

900M

1G

Str

es

s X

X (

Pa

)


W = 300nm

W = 200nm

W = 400nm

Model

-1.0 -0.5 0.0 0.5 1.0

300M

330M

360M

390M

420M

450M

480M

510M

Str

es

s X

X (

Pa

)

Normalized Position along Channnel Width (W/2)

W = 300nm

W = 200nm

W = 400nm

Model

-0.02 -0.01 0.00 0.01 0.0250M

100M

150M

200M

250M

300M

350M

Str

es

s Y

Y (

Pa

)


W = 300nm

W = 200nm

W = 400nm

Model

-1.0 -0.5 0.0 0.5 1.0

60M

75M

90M

105M

120M

135M

Str

es

s Y

Y (

Pa

)

Normalized Position along Channel Width (W/2)

W = 300nm

W = 200nm

W = 400nm

Model

Verification with Silicon Data

Intrinsic Transistor Delay

Mobility %

Injection Velocity %

Threshold Voltage %

Effective Current %

RO Frequency %

13-stage Ring Oscillators Control Logic

0.2 0.3 0.4 0.5 0.6 0.7 0.80

2

4

6

8

10

12

% C

ha

ng

e i

n R

O F

req

ue

nc

y

LOD Length (um)

Conventional Model

Injection Velocity Model

Experimental Data

45nm RO Test Structure

with CESL

Channel Length (um)

Ch

an

nel W

idth

(u

m)

a) b)

x

x

x

x

x

x

LOD

Test Chip information:E. Josse et al, IEDM (2006)

Test RO

Mobility Distribution

Predictive Device Modeling

What limits the ON-state current for modern transistors ?

Drift + Diffusion Quasi-Ballistic

Low-field Mobility(Along whole channel)

High-field Saturation Velocity(Drain side)

Injection Velocity(Source edge)

?

Lg >> Lg ~ (20nm for Si)

Source Drain

CESL

Lg

l

Channel Potential

Compact Modeling Flow

Low-field Mobility

Backscattering Rates

Critical length

Average stress in critical

length region

Band shift

Effective Mass Variation

Charge density

Surface Fermi Level

Subband Energy

Calculate current

Drain bias

Stress

profiles

Gate bias

Self-consistentsolution

Quasi-ballistic current:

“Critical length”:

Backscattering rate:0.0 0.2 0.4 0.6 0.8 1.0 1.2

5

10

15

20

25

30

35

40

Av

era

ge

stre

ss

_x

x* (P

a)

Cri

tic

al

Le

ng

th (

nm

)

Drain bias (V)

Ave. Stress_xx along

whole channel

Vds = 1.2V

Lg = 40nm

240M

250M

260M

270M

280M

Energy-band

diagram:

𝐼 = 𝑞𝑊 2𝑚𝑦

2𝑕2

𝑖𝑥 ,𝑦 ,𝑧

𝑘𝑇

𝜋

32

(1− 𝑅) ℱ12

𝜂𝑖1 − ℱ12

𝜂𝑖2

𝑙 = 𝐿𝑔 ×

𝑘𝐵𝑇

𝑞𝑉𝑑× 𝑡𝑎𝑛−1

𝑞𝑉𝑑𝑘𝐵𝑇

𝑅 =𝑙

𝑙 + 0

𝜆 =

2𝜇

𝜈𝑇

𝑘𝐵𝑇

𝑞

ℑ02 (𝐸𝑓 )

ℑ1′ (𝐸𝑓 ) × ℑ1

2(𝐸𝑓)

𝐼 =𝑞𝑊 2𝑚𝑦

𝑘𝐵𝑇𝜋

32

2ℏ2 1 − 𝑅 [ℑ1

2

𝐸𝑓1 − ℑ12

𝐸𝑓2 ]

Mean Free Path

Backscattering Rates

Critical Length

Injection Velocity Model

A. Rahman et al. TED 49, 481 (2002).

Model Verification

0.0 0.2 0.4 0.6 0.8 1.0 1.21E-8

1E-7

1E-6

1E-5

1E-4

1E-3

Vds = 0.05 V

Id

(A)

Vgs (V)

Exp. Data in [11]

Model

Vds = 1.0 V

Fitting Parameters:

Gate Control Para. 0.85

Drain Control Para. 0.06

Low-field Mobility 250 cm2/V.s

Series Resistance 180 Ohm.um

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.40

400

800

1200

1600

2000

Exp. Data in [11]

Model

Id

(uA

/um

)

Vds (V)

1.2V

1.1V

1.0V

0.9V

0.8V

0.7V

0.6V

0.5V

0.4V

S. Mayuzumi et al., IEDM Tech. Dig. p. 293, 2007

Experiment data from:

• Only 4 fitting parameters

• Physically-based, Predictive

Model Prediction

15 20 25 30 35 40 45 50

12

15

18

Poly gate

Metal gate

Work in [11]

Channel Length (nm)

Inje

cti

on

Ve

loc

ity

(1

06

cm

/s)

Ballistic velocity w/o strain

Injection velocity w/o strain

Injection velocity with strain

15 20 25 30 35 40 45 500.4

0.5

0.6

0.7

0.8

0.9

1.0

Work in [11]

Poly gate

Metal gate

Channel Length (nm)In

trin

sic

De

lay

(p

s)

W/O Strain

With Strain

ITRS

HP Tech Node 90nm 68nm 52nm 40nm

Lg (nm) 32 25 20 16

Tinv(nm) 1.93 1.84 1.04 0.82

Body Doping

(cm-3) 3.3e18 4.8e18 4.1e18 6.6e18

S/D Series

Resistance

(Ohm.um)

180 200 200 180

Vdd (V) 1.1 1.1 1 1

𝜏 =

𝑉𝑑𝑑 − 𝑉𝑡𝑕 +𝐶𝑓𝑉𝑑𝑑𝐶𝑖𝑛𝑣𝐿𝑔

3− 𝛿 𝑉𝑑𝑑

4− 𝑉𝑡𝑕

𝐿𝑔

𝑣𝑖𝑛𝑗

Technology Parameters from ITRS 2007

Modern bulk MOSFETs are still far from

ballistic limits

Stress benefits decrease as Lg scales

Planar & 3D MOSFET Design

*J.G. Fossum, IEDM 2004

MuGFET Design Rule

*X. Sun, to be published

Performance Benefits Reduced Variations

*X. Sun, EDL 29,p493(2008)

3D Stress Design for MuGFETs

• Various Stress Configurations

a) Uniaxial Stress

(CESL)b) Biaxial Stress c) Transverse Stress

(Metal Gate)

PolyCESL

Si

Poly

SOI

Si

Metal Gate

Si

Poly

y

Z(100)

x <110> or <100>

Sxx : Szz = 1 : -1 Sxx : Syy = 1 : 1 Syy : Szz = 1 : 1

Only transverse direction

Compressive

NMOS: Tensile

PMOS: Compressive

NMOS: Tensile

PMOS: Tens. & Comp.

• Experiments

0 5 10 15 20 25 30 350

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18strain vs micrometer knob

micrometer knob

str

ain

bi-axile tensile

bi-axile compressive

0.11%

Micrometer Knob

Str

ain

[%

]

TEM Cross-section - Test chip from TI

<110> NMOS

Lg=5um

Gate Voltage [V]

1E-14

1E-12

1E-10

1E-08

1E-06

1E-04

-0.5 0 0.5 1 1.5

0E+00

1E-05

2E-05

0.11%

0%

1E-14

1E-12

1E-10

1E-08

1E-06

1E-04

-1.5 -1 -0.5 0 0.5

0E+00

1E-05

2E-05

3E-05

4E-05

5E-05

0.11%

0%

DR

AIN

CU

RR

EN

T [

A]

TR

AN

SC

ON

DU

CT

AN

CE

[S]

<110> PMOS

Lg=1um

• Simulation (Fully Quantum Mechanical)

N-MuGFET 2D Poisson-EMA Schrodinger

Analytical model for strain impact

non-parabolic E-k for mobility calculation

P-MuGFET2D Poisson-6x6 K.P

Luttiger-Kohn Hamiltonian, with strain

impact coupled

Detailed E-k for mobility calculation

Parameter set (calibrated with experiments):NMOS:Dac = 14.7eVDk_LO=11x1010 eV/mDk_TO=2x1010 eV/mDk_TA=2x1010 eV/mPMOS:Dac = 9.6eVDk = 12.9x1010 eV/mhw= 61.2meVSurface Roughness:

(100) Top surface: =3.30A =20A

(100) Sidewall: =4.05A =20A

(110) Sidewall: =6.90A =26A

hw_LO=64meVhw_TO=64meVhw_TA=48meV

MuGFET Universal Mobility

• Simulation & Measurements

0.0 3.0x1012

6.0x1012

9.0x1012

1.2x1013

1.5x1013

100

150

200

250

300

350

400

450

500

N-MuGFET

HSi

= 58nm

TSi

= 20nm

(100) WaferEle

ctr

on

Mo

bil

ity

(c

m2/V

s)

Ninv

(cm-2)

<100> Unstrained

<100> Metal Gate

<100> Biaxial Tensile

<110> Unstrained

<110> Metal Gate


Simulation

0.0 3.0x1012

6.0x1012

9.0x1012

1.2x1013

100

150

200

250

300

350

<110> Unstrained

<110> Metal Gate


<100> Unstrained

<100> Metal Gate


Simulation

P-MuGFET

HSi

= 58nm

TSi

= 20nm

(100) Wafer

Ho

le M

ob

ilit

y (

cm

2/V

s)

Ninv

(cm-2)

Electron Hole

Mobility vs. Different Types of Stress

• Simulation Results

0 200 400 600 800 1000 1200 14000

20

40

60

80

100

120

140

160

180

Ninv

= 9x1012

cm-2

HSi

= 58nm, TSi

= 20nm

(100) wafer

<110> CESL

<110> Bi. Tens.

<110> Gate

<100> CESL

<100> Bi. Tens.

<100> Gate

Mo

bil

ity

Ch

an

ge

(%

)

Stress (MPa)

0 200 400 600 800 1000 1200 1400-40

-20

0

20

40

60

80

100

120

140

160

180

200

Mo

bil

ity

Ch

an

ge

(%

)

Stress (MPa)

<110> CESL

<100> CESL

<110> Bi. Comp.

<100> Bi. Comp.

<100> Gate

<100> Bi. Tens.

<110> Gate

<110> Bi. Tens.

Ninv

= 1x1013

cm-2

HSi

= 58nm, TSi

= 20nm

(100) wafer

<110> channel/fin is more sensitive to stress

CESL stress gives largest mobility enhancement

Electrons Holes

Bench Marking between FinFET & TriGate


0 200 400 600 800 1000 1200 1400100

200

300

400

500

open symbols: FinFET

closed symbols: Tri-Gate

Ele

ctr

on

Mo

bil

ity

(c

m2/V

s)

Stress (MPa)

<100> CESL

<110> CESL



0 200 400 600 800 1000 1200 1400

100

200

300

400

500

600



Ho

le M

ob

ilit

y (

cm

2/V

s)

Stress (MPa)

<110> CESL

<110> Biaxial Compressive


Electrons Holes

FinFET-like:

TSi = 1/3 Lg

HSi = Lg

TriGate:

TSi = Lg

HSi = 1/3 Lg

MuGFET Injection Velocity


20 40 60 80 100 1200.0

2.0x104

4.0x104

6.0x104

8.0x104

1.0x105

1.2x105

1.4x105

1.6x105

Vds

= 1V

Ninv

= 1x1013

cm-2



Ele

ctr

on

In

jec

tio

n V

elo

cit

y (

m/s

)

Channel Length (nm)

<100> CESL 1400MPa

<110> CESL 1400MPa

<100> unstrained

<110> unstrained

Extracted Data

uniaxial stressed

unstrained

20 40 60 80 100 120140

0.0

2.0x104

4.0x104

6.0x104

8.0x104

1.0x105

1.2x105



unstrained

Ho

le I

nje

cti

on

Ve

loc

ity

(m

/s)

Channel Length (nm)

<110> CESL -1400MPa

<110> unstrained

<100> unstrained

Extracted Data

uniaxial stressed

Vds

= -1V

Ninv

= 1x1013

cm-2

Electrons Holes

<110> channel/fin has large stress enhancement

TriGate & FinFET is similar due to effective mass domination

Simulation compared with published planar CMOS measured data

Summary

• A Fast Way to evaluate stress-induced layout dependent variations

physically-based functions, rely on few parameters

very fast, yet accurate enough for DFM research

• A Compact Model for MOSFET I-V under quasi-ballistic regime

Only 4 fitting parameters

Predictive for future technology node transistor performance

• A Quantum Simulation Approach for MuGFET mobility study

Design the stress strategy for 3D MOSFET structures

Explore new physical phenomena for scaled devices

• … …

Stress will be used … to the end of CMOS!

New problems research opportunities raised for scaled devices

Acknowledgements

• IMPACT program & UC Discovery Grant

• UC Berkeley Graduate Fellowship

• Test chips donated from STMicroelectronics &

Texas Instruments

Study for Mechanical Stress Impact in Scaled...

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