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STC12C5A60S2 series MCUSTC12LE5A60S2 series MCU

Data Sheet

STC MCU Limitedwww.STCMCU.com

Update date: 2011-7-15

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CONTENTSChapter 1. Introduction .................................................................8

1.1 Features .................................................................................................. 81.2 Block diagram ........................................................................................ 91.3 Pin Configurations ............................................................................... 101.4 STC12C5A60S2 series Selection Table ............................................... 131.5 STC12C5A60S2 series Minimum Application System ....................... 161.6 STC12C5A60S2 series Application Circuit for ISP ............................. 181.7 Pin Descriptions ................................................................................... 201.8 Package Dimension Drawings .............................................................. 211.9 STC12C5A60S2 series MCU naming rules ......................................... 261.10 Global Unique Identification Number (ID) ........................................ 27

Chapter 2. Clock, Power Management and Reset ....................302.1 Clock .................................................................................................... 30

2.1.1 On-Chip R/C Clock and External Crystal/Clcok are Optional in STC-ISP.exe . 302.1.2 Divider for System Clock ................................................................................... 312.1.3 How to Know Internal RC Oscillator frequency(Internal clock frequency) ...... 322.1.4 Programmable Clock Output ............................................................................... 35

2.1.4.1 Timer 0 Programmable Clock-out on P3.4 .........................................................................372.1.4.2 Timer 1 Programmable Clock-out on P3.5 .........................................................................382.1.4.3 Baud Rate Generator and Programmable Clock Output on P1.0 .......................................38

2.2 Power Management Modes .................................................................. 392.2.1 Slow Down Mode ................................................................................................ 402.2.2 Idle Mode ............................................................................................................. 412.2.3 Stop / Power Down (PD) Mode ........................................................................... 42

2.3 RESET Sources .................................................................................... 482.3.2 External Low Voltage Detection Reset (high reliable Reset, RST2 pin Reset) ... 492.3.3 External Low Voltage Detection if not be used RST2 can be as Interrupt .......... 502.3.4 Software RESET .................................................................................................. 542.3.5 Power-On Reset (POR) ........................................................................................ 542.3.5 MAX810 power-on-Reset delay .......................................................................... 552.3.3 Watch-Dog-Timer ................................................................................................ 562.3.8 Warm Boot and Cold Boot Reset ......................................................................... 60

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Chapter 3. Memory Organization ..............................................613.1 Program Memory ................................................................................. 613.2 Data Memory ........................................................................................ 62

3.2.1 On-chip Scratch-Pad RAM .................................................................................. 623.2.2 Auxiliary RAM .................................................................................................... 643.2.3 External Expandable 64KB RAM (Off-Chip RAM) ........................................... 70

3.3 Special Function Registers ................................................................... 733.3.1 Special Function Registers Address Map ............................................................ 733.3.2 Special Function Registers Bits Description ....................................................... 743.3.3 Dual Data Pointer Register (DPTR) .................................................................... 78

Chapter 4. Configurable I/O Ports of STC12C5Axx series .....804.1 I/O Ports Configurations ...................................................................... 804.2 P4/P5 of STC12C5A60S2 series .......................................................... 854.3 I/O ports Modes .................................................................................... 87

4.3.1 Quasi-bidirectional I/O ........................................................................................ 874.3.2 Push-pull Output .................................................................................................. 884.3.3 Input-only (High-Impedance)Mode..................................................................... 884.3.4 Open-drain Output ............................................................................................... 88

4.4 I/O port application notes ..................................................................... 894.5 Typical transistor control circuit ........................................................... 894.6 Typical diode control circuit ................................................................. 894.7 3V/5V hybrid system ............................................................................ 904.8 How to make I/O port low after MCU reset ......................................... 914.9 I/O status while PWM outputing .......................................................... 914.10 I/O drive LED application circuit ....................................................... 924.11 I/O immediately drive LCD application circuit .................................. 934.12 Using A/D Conversion to scan key application circuit ...................... 94

Chapter 5. Instruction System ....................................................955.1 Addressing Modes ................................................................................ 955.2 Instruction Set Summary ...................................................................... 965.3 Instruction Definitions ........................................................................ 101

Chapter 6. Interrupt System .....................................................1386.1 Interrupt Structure .............................................................................. 1406.2 Interrupt Register ................................................................................ 142

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6.3 Interrupt Priorities .............................................................................. 1536.4 How Interrupts Are Handled .............................................................. 1546.5 External Interrupts ............................................................................. 1556.6 Response Time .................................................................................. 1596.7 Demo Programs about Interrupts (C and Assembly Programs) ......... 160

6.7.1 External Interrupt 0 (INT0 ) Demo Programs (C and ASM) ............................ 1606.7.2 External Interrupt 1 (INT1 ) Demo Programs (C and ASM) ............................ 1646.7.3 Programs of P3.4/T0/INT Interrupt(falling edge) used to wake up PD mode .. 1686.7.4 Programs of P3.5/T1/INT Interrupt(falling edge) used to wake up PD mode .. 1706.7.5 Program of P3.0/RxD/INT Interrupt(falling edge) used to wake up PD mode . 1726.7.6 Demo Program of Low Voltage Detection Interrupt used to wake up PD mode 1756.7.7 Program of PCA Interrupt used to wake up Power Down mode ....................... 178

Chapter 7. Timer/Counter 0/1 ..................................................1827.1 Special Function Registers about Timer/Counter ............................... 1827.2 Timer/Counter 0 Mode of Operation (Compatible with traditional 8051 MCU) ......... 187

7.2.1 Mode 0 (13-bit Timer/Counter) ...................................................................................... 1877.2.2 Mode 1 (16-bit Timer/Counter) and Demo Programs (C and ASM) .............................. 1887.2.3 Mode 2 (8-bit Auto-Reload Mode) and Demo Programs (C and Assembly Program) ... 1927.2.4 Mode 3 (Two 8-bit Timers/Couters) ............................................................................... 195

7.3 Timer/Counter 1 Mode of Operation .................................................. 1967.3.1 Mode 0 (13-bit Timer/Counter) ...................................................................................... 1967.3.2 Mode 1 (16-bit Timer/Counter) and Demo Programs (C and ASM) .............................. 1977.3.3 Mode 2 (8-bit Auto-Reload Mode) and Demo Programs (C and ASM) ......................... 201

7.4 Programmable Clock Output and Demo Programs (C and ASM) ..... 2047.4.1 Timer 0 Programmable Clock-out on P3.4 and Demo Program ........................ 2067.4.2 Timer 1 Programmable Clock-out on P3.5 and Demo Program ........................ 2097.4.3 Baud Rate Generator Programmable Clock-Out on P1.0 and Demo Progra