(1).

(2). Every flip-flop has restrictive time regions around the active clock edge in which input should not change. We call them restrictive because any change in the input in this regions the output may be the expected one (*see below). It may be derived from either the old input, the new input, or even in between the two. Here we define, two very important terms in the digital clocking. Setup and Hold time. 

The setup time is the interval before the clock where the data must be held stable. The hold time is the interval after the clock where the data must be held stable.

Hold time can be negative, which means the data can change slightly before the clock edge and still be properly captured. Most of the current day flip-flops has zero or negative hold time. 

To avoid setup time violations: 

The combinational logic between the flip-flops should be optimized to get minimum delay.

Redesign the flip-flops to get lesser setup time. Tweak launch flip-flop to have better slew at the clock pin, this will make launch flip-

flop to be fast there by helping fixing setup violations. Play with clock skew (useful skews).

To avoid hold time violations: 

By adding delays (using buffers). One can add lockup-latches (in cases where the hold time requirement is very huge,

basically to avoid data slip).

(3). Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability.In metastable state Pmos and Nmos transistor in cmos circuit in switch on state so it will draw more power/current.so circuit can burn due to this,so we should stop this by some logic.When the frequency of clock is increses (means faster clock) time for metastability to get stablised decreses.So more sycrhonizer circuit are required in high frequency domain.

Traditional double synchronizer The most common way to tolerate metastability is to add one or more successive synchronizing flip-flops to the synchronizer. This approach allows for an entire clock period (except for the setup time of the second flip-flop) for metastable events in the first

synchronizing flip-flop to resolve themselves. This does, however, increase the latency in the synchronous logic's observation of input changes.

Place the flops as near as possible to allow more time for metastability to resolve special flops are avialabe in lib which have high MTBF (mean time between failure) .The chance of metastabilty to get stabilized to the correct logic value is represented by MTBF.

We can use a metastable hardened flip-flop Cascade two or three D-Flip-Flops (two or three stages synchronizer).

(4).

(5).

(6).

(7). Even a single glitch in clock path can cause the chip to be metastable and even fail. A glitch is

any unwanted clock pulse that may cause the sequential cells to consider it as an actual clock

pulse. Thus, a glitch can put your device in an unwanted state that is functionally never possible.

That is why; there should never be a glitch in clock path. Every effort should be done by designers to

minimize its probability. The figure below shows a flip-flop receiving a data signal and a clock

signal; if there is some glitch (unwanted change of state) in clock, it will take it as a real clock edge

and latch the data to its output. However, if the pulse is too small, the data may not propagate

properly to output and the flop may go metastable.

Figure showing functional glitch in clock path

(8) inverter delay is lesser than buffer for the same drive capacity. buffer is basically 2 inverters connected back to back. so the insertion delay [modelled by set_clk_latency in DC]of the clock tree will be lesser.

(9).

(10).

(11).

(12). Negative hold check means that the data pin of the flip-flop can change ahead of the clock pin and still meet the hold time check.

setup values of a flip-flop can also be negative. This means that at the pins of the flip-flop, the data can change after the clock pin and still meet the setup time check.

For the setup and hold checks to be consistent, the sum of setup and hold values should be positive. Thus, ifthe setup (or hold) check contains negative values - the corresponding hold (or setup) should be sufficiently positive so that the setup plus hold value is a positive quantity.

Both both setup and hold cannot be negative

(13).   Ways To Fix Setup violation

Method 1 : Reduce the amount of buffering in the path.

Method 2 : Replace buffers with 2 Inverters place farther apart

Method 3 : HVT swap. Means change HVT cells into SVT/RVT or into LVT.

Method 4 : Increase Driver Size or say increase Driver strength (also known as upsize the cell)

Method 5 : Insert Buffers

Method 6 : Inserting repeaters:

Method 7 : Adjust cell position in layout.

Ways to Fix Hold Violations:

Method 9 : By Adding delays.

Method 10 : Decreasing the size of certain cells in the data path.

(14). http://vlsi-soc.blogspot.in/2012/06/pvt-and-how-they-impact-timing.html

(15). As the "convergence" means (dictionary) "the occurrence of two or more things coming together". So we can assume that its also related to 2 clock path coming together.

As you can see that flop share a common clock but are placed physically at the different places in the same die. Or in other way you can say that Launch clock path and capture clock path 

As we know that every cell has two type of delay as a part of its specification, "Max Delay" and "Min delay". There are several scenario in the design where we use either max delay or min delay of a particular cell. Such as best case analysis (BC), worst case (WC) analysis, OCV (on chip variation) analysis during timing analysis.

Clock reconvergence pessimism = (maximum clock delay) - (minimum clock delay)

(16). http://tech.tdzire.com/what-is-temperature-inversion/

(17)