Sprinkler Buddy Presentation #7: “Redesign of Adder Parts And Layout of Other Major Blocks”...
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Transcript of Sprinkler Buddy Presentation #7: “Redesign of Adder Parts And Layout of Other Major Blocks”...
Sprinkler Buddy
Presentation #7:
“Redesign of Adder Parts
And Layout of Other
Major Blocks”
3/07/2007
Team M3Kalyan Kommineni
Kartik Murthy Panchalam Ramanujan
Sasidhar UppuluriDevesh Nema
Design Manager: Bowei Gai
“Low Cost Irrigation Management For Everyone ! ”
Current Status Determine Project Develop Project Specifications Plan Architectural Design
Determination of all components in design Detailed logical flowchart
Design a Floor Plan Create Structural Verilog Make Transistor Level Schematic Layout
(~65% done with all big modules except FP Add passing LVS …)
Testing (Extraction, LVS, and Analog Sim.) (ongoing…)
Last Week’s Floor Plan
Current Floor Plan
Transistor Count …
Block (# used) Old TC New TC
40:20 Muxes (6) 362 362
60:20 Muxes (2) 644 644
Counter (2) 220 220
KC ROM (1) 1256 1256
P ROM (1) 122 122
Metric Storage SRAMS (2)
2430 2430
Constant Storage ROM (1)
428 428
Floating Point Adder (4)
3210 3977Floating Point Multiplier (2)
1398 102610 Bit Registers (9)
210 210
Datapath Logic / Misc.
2305 2305
Total:
32,921
Updated Design SizeBlock (# used) Size (um)
40:20 Muxes (4) 20 x 80
60:20 Muxes (2) 20 x 120
Counter (2) 12 x 17
KC ROM (4 parts) 181 x 8
P ROM (1) 70 x 8
Metric Storage SRAMS (2)
181 x 60
Constant Storage ROM (1)
181 x 8
Floating Point Adder (4)
96x151
Floating Point Multiplier (2)
89 x 40
10 Bit Registers (8) 50 x 10
• 441um x 411 um• ~ 1 : 1.07 aspect ratio• .181 mm^2 area
Layout: Progress
Everything laid out has density > .3 transistors/um2
All Big Modules LVS FP Add is the exception
Had to redo many components Initial layout was too big and messed up
the floor plan Currently done with all components except
new shifter New layouts enable us to match initial size
estimate
Layout : Muxes
1 bit
6 bit
Density: .42 transistors/um2
Layout : Registers
10 bits
Density: .40 transistors/um2
1bit
Layout : Register Enable
Custom “AND” Gate
Layout : “Is Zero?” Unit
Density: .41 transistors/um2
•Sideways Inverters
•Split NAND Gate
Layout : Leading Zero Counter
Density: .40 transistors/um2
Layout : Conditional Add/Sub
Density: .30 transistors/um2
Layout : Subtract
Density: .33 transistors/um2
Layout : New Barrel Shifter
Still needs decoder and input buffers
Layout : FP Add Exponent Unit
Density: .34 transistors/um2
Inputs
Outputs
Layout : FP Add Sig. Unit
Density: .30 transistors/um2
Inputs
OutputsThere is some wiring
left and the shifter must be inserted
Layout : FP Adder
Density: .33 transistors/um2
Needs to be wired
Layout : Redone Integer Multiply
So, why did we leave a
HUGE hole?
Density: .32 transistors/um2
Layout : Floating Point Multiply
Density: .31 transistors/um2
Inputs Outputs
Design Challenges and Implementation
DecisionsFor The Past Week
Design Challenge
Translation to HW
Low Power Design
• Although we tried to get make extremely compact layouts we were cognizant of power• We didn’t make sacrifices such as long poly lines which could have yielded more compressed layout
Problems/QuestionsWe cannot accurately lay out our control
logic until the FP Adder is done and global layout is all positioned
For Next TimeLots and Lots more Layout
Finish the FP Adder Place all blocks into global layout and fit
control logic into the gaps Global routing