SPIO-4 Precision Signal-Path Controller Board

1SNAU112A–December 2010–Revised May 2018Submit Documentation Feedback

Copyright © 2010–2018, Texas Instruments Incorporated

SPIO-4 Precision Signal-Path Controller Board

User's GuideSNAU112A–December 2010–Revised May 2018


This user’s guide describes the characteristics, operation, and use of the SPIO-4 precision signal-pathcontroller board. This document includes a schematic, reference printed circuit board (PCB) layouts, and acomplete bill of materials (BOM).

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2 SNAU112A–December 2010–Revised May 2018Submit Documentation Feedback



Contents1 System Overview ............................................................................................................ 32 System Functionality ........................................................................................................ 53 PCB Layout, Schematics, and Bill of Materials......................................................................... 11

List of Figures

1 SPIO-4 System Block Diagram ............................................................................................ 52 GPSI 16 DUT to SPIO4 Mating ............................................................................................ 73 GPSI 32 DUT to SPIO4 Mating ............................................................................................ 74 SPIO-4 Board Layout – Component Side............................................................................... 115 Board Photo Showing Respective Layout From ...................................................................... 116 SPIO-4 Interface Board Block Diagram ................................................................................. 127 Atmel ARM Microcontroller: Power, Debug, and Analog ............................................................. 138 Atmel ARM Microcontroller and Port Connection ...................................................................... 149 SPIO4 PSRAM ............................................................................................................. 1510 SPIO-4 FPGA SRAM and Configuration Interface..................................................................... 1611 SPIO-4 FPGA DEBUG, JTAG Interfaces and Power ................................................................. 1712 SPIO4 FPGA GPSI32 Interface .......................................................................................... 1813 SPIO-4 Micro SD Card .................................................................................................... 1914 USB, CPU JTAG ........................................................................................................... 2015 SPIO-4 Power Distribution ................................................................................................ 2116 3.3-V, 1.2-V, 1.8-V, and DUT Power Supplies ......................................................................... 22

List of Tables

1 Main Component Reference Designators ................................................................................ 42 Test Points.................................................................................................................... 43 LED Behavior ................................................................................................................ 64 GPSI-32 Signals ............................................................................................................. 85 Bill of Materials ............................................................................................................. 23

TrademarksAll trademarks are the property of their respective owners.

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www.ti.com System Overview




1 System OverviewThe SPIO-4 is one of several National Semiconductor digital controller and capture boards that are usedby multiple evaluation systems. The objective of these software and hardware evaluation systems is toallow our customers to easily and accurately evaluate TI's signal-path devices in a lab setting. At the timeof the SPIO-4 release, two different evaluation system software applications and graphical user interfaces(GUIs) make use of this board: the WaveVision-5 and the Sensor AFE. The board ships with the currentversion of the WaveVision-5 software.

In addition to the controller and capture board (in this case, the SPIO-4) and the evaluation GUI software(for example, WaveVision-5 or Sensor AFE), the third essential element of an evaluation system is thedevice or signalpath evaluation board that plugs into the controller board. This evaluation board isgenerically referred to as the DUT board. Each DUT board comes with a user's guide that documents thespecific features of the board. Each DUT board also comes with some software that the user must installbefore initial use. In the case of the WaveVision-5 GUI, this software is essentially a device-specificmodule that adds support for the future device evaluation boards. In the case of Sensor AFE devicefamily, the evaluation board comes with a complete, custom Sensor AFE that is specifically paired withthat device.

The WaveVision-5 and Sensor AFE GUI software have respective user's guide documents that describehow to interact with the respective GUI.

This user’s guide describes only the SPIO-4 board. The user is expected to refer to this guide only ifnecessary. The DUT user’s guide and the GUI user's guide are the primary documents that describe howto work with a TI signal-path evaluation board.

The latest version of this document may be obtained from the Texas Instruments web site at www.ti.com.

1.1 System Features• Captures or sources multiple signal-path data streams and transfers them to and from the PC-based

application software through a USB 2.0 connection (USB 1.1 compatible).• Supports a jumper-less, plug-and-play configuration. The GUI automatically discovers the attached

DUT board and loads the appropriate software module for it.• Supports a wide variety of signal-path evaluation board through a standardized connector (GPSI- 16 or

GPSI-32).• Capable of storing up to 8 MBytes of signal-path data.• DUT interface can be SPI, I2C, or parallel.• Powered either by PC via USB or external supply.

1.2 Packing ListThe SPIO-4 kit (order number SPIO-4/NOPB) consists of the following components:• SPIO-4 board• USB cable• User’s guide (this document)• WaveVision-5 GUI software

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System Overview www.ti.com




1.3 Component DescriptionTable 1 describes both the onboard connectors and the main components used in the SPIO-4 systemshown in Figure 4.

Table 1. Main Component Reference Designators

Component DescriptionJ1 Serial debug connectorJ2 Header to provide access to the FPGA JTAG interface for debugJ3 Jumper to select J4 IO voltage (3.3 V or programmable)J4 (DBG) Debug and development connector(see Section 2.6)J6 (GPSI-32) GPSI-16/32 connector to DUTJ7 (micro_SD) Holds the microSD card for storage or development purposesJ8 (USB) USB cable connectionJ9 (JTAG) Atmel processor JTAG debug headerJ10 (POWER) 5-v to 6-V power supply connection; optional (see Section 2.9)J14 (USNAP) Additional header providing power and serial interface to processorJP1 Jumpers for test purposes onlyU1 Atmel SAM3U processorU4 8Mx16 PSRAMU5 Xilinx Spartan LX16 FPGAD1-D4 FPGA status LEDs (see Section 2.4)D6 1.8-V PSRAM core voltage surface-mount power LEDD7 3.3-V DUT supply voltage surface-mount power LEDD8 5.0-V DUT supply voltage surface-mount power LEDD10 USB input power LEDD11 1.2-V FPGA Core voltage surface-mount power LEDSW1 Reset switchSW2 Power on push-button

1.4 SPIO-4 Board Test PointsTable 2 describes the available test points.

Table 2. Test Points

Test Point DescriptionTP1, TP3, TP16, TP18 (GND) Ground test pointsTP11 3.3-V digital I/O voltage for SPIO boardTP12 1.2 V for FPGA core voltageTP13 1.8 V for PSRAM core voltageTP14 3.3 V for DUT digital supplyTP15 5.0 V for DUT analog supply

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8MBx16PSRAM

(U4)

Spartan 6XC6SLX16

(U5)

IO Voltage

A23-1

D15-0

NCS0

NWR

NRD

NBS0-1

NCS2 NCS3/FPGA_CFG

LP3910MultipleSupply

SwitchingRegulator

(U11)

JTAG(J2)

DEBUG(J4)

Micro-ControllerAtmel SAM3U

(U1)

USBConnector

(J8)

USB

SDCard(J7)

Static Mem intrfc

GPIO

3.3 V

DebugConnector

(J1)

DebugConnector

(J9)

12 MHZXtal

32 kHZXtal

InputProtection

Ext Pwr(J10)

DUT3.3V_EN

BoostRegulator

(U12)Filter

DUT 5 V

>Level Shift

GPSI A

GPSI A

<Level Shift

3.3 V DUT

3.3 V DUT

I2C(SCL)

I2C(SCL)

3.3 V

DUT 3.3 V

GPSI B

DUT 3.3 V

VDDIO

GPSI A

GPSI A

DUT 5 V

GPSI 32Connector

(J6)

DUT3.3V_EN

Pins 1, 3, 7, 8, 16

Pins 5, 6, 9

Pin 15

Pin 12

Pin 11

Pin 13

Pin 14

Pin 23-30

I2C

USB 5 V

1.8 V

1.2 V

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2 System Functionality

2.1 System Block Diagram

Figure 1. SPIO-4 System Block Diagram

2.2 General System OverviewThe SPIO-4 board is controlled via the Atmel SAM3U, a microcontroller that is based on an ARM M3, 32-bit embedded core. This miscrocontroller provides the interface to the computer via a USB interface. TheDUT board interfaces to the SPIO-4 via J6, the GPSI-16/32 connector. The GPSI-16/32 interface providescontrol, data and power to the DUT board. The interfaces on the GPSI-32 can be I2C, SPI with multiple-device capability, or parallel interface. The dedicated I2C interface on the GPSI-16/32 is primarily forcontrol and DUT identification, while the dedicated SPI interface may be used for control or for datatransfer. The I2C interface is derived from the peripheral of the microcontroller. There can be a widevariety of SPI requirements for DUTs; therefore, the SPI interface can be provided via a processorperipheral and over the dedicated SPI lines as shown in this document, or the onboard Xilinx SpartanXC6SLX16 FPGA may be used. In fact, the FPGA may be used to implement DUT interfaces other thanSPI, such as high-speed I2C for data purposes, and parallel data-plus-clock interfaces. A large externalSRAM 8Mx16 is connected to both the processor and the FPGA, and is used to provide additional devicedata storage in case the microcontroller or FPGA onboard memory is insufficient.

Power is provided to the system via the USB cable or external power jack. A switching regulator is used toproduce the 3.3-V supply required by the microcontroller and GPSI-32 devices. A boost regulator createsthe regulated 5-V supply required by the devices interfaced to the GPSI-32 connector.

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System Functionality www.ti.com




2.3 Automatic Device Detection and ConfigurationThe SPIO-4 system supports automatic hardware detection and configuration of the device under test.The GUI software actually carries out the device detection and configuration task. The FPGA isreconfigured on-the-fly by the host PC when the SPIO-4 board is powered on, or whenever ADCevaluation boards are exchanged and SPIO-4 power is cycled.

Each DUT board has either an FPGA configuration file or a microcontroller firmware module unique to theboard. The GUI software, in conjunction with the USB microcontroller, determines which DUT board hasbeen plugged in. The GUI then loads a configuration file tailored for that DUT board into the FPGA, themicrocontroller, or both.

Normally, the configuration process is totally transparent to the user, and requires no intervention.However, some devices may allow this process to be overridden. Refer to the evaluation board manual formore information.

NOTE: Many of our device evaluation boards do require jumper configurations to select channels,voltages, or other options. Please consult the manual that came with the evaluation board forspecific information.

CAUTIONBe aware that DUT boards are NOT hot swappable. Power down both theSPIO-4 board and the DUT board prior to swapping DUT board.

2.4 LED IndicatorsThere are several LED indicators on the SPIO-4 board. The LED indicators described in Table 3 aredriven directly by separate power rails on the SPIO-4 board. Those rails can only be controlled by theprocessor; therefore, the LEDs not only indicate a particular rails is powered on, but the LEDs also showthe state of the SPIO-4 firmware, as shown in Table 3.

Table 3. LED Behavior

LED Number DescriptionD10 Indicates power (USB or external) is present to SPIO boardD5 3.3-V digital I/O voltage for SPIO board is up (required for all operations)

D6 1.2 V for FPGA core voltage. Indicates processor has completed low-level hardware initialization, and isready to program the FPGA.

D11 1.8 V for PSRAM core voltage. Indicates processor has completed low-level hardware initialization, andis able to use the PSRAM

D7 and D8 3.3-V and 5-V DUT supplies. Indicates the processor has detected a DUT board is inserted, and haspowered the board.

2.5 DUT Interface (GPSI-16/32)The SPIO-4 data capture board is connected to the DUT through the GPSI-16/32 (J6) connector. Asdescribed in this user's guide, the GPSI-32 interface provides control, data, and power to the DUT board.See Table 4 for signal specifics. The GPSI-16/32 interface also supports a subset called GPSI-16 thatconsists of the lower order pins 1 to 16. A given DUT board may use a 16-pin, GPSI-16 port only, or mayuse the whole 32-pin port. GPSI-16 has level shifters allowing some of the DUT interface voltages to gofrom 1.65-V to 5.5-V LVTTL levels under the direct control of the DUT board circuitry. To achieve thatvoltage range, the voltage level shifters are NOT bidirectional. A DUT board requiring bidirectional signalsmust use the upper-order portion of the GPSI-32. However, that upper-order portion of GPSI-32 requiresadherence to 3.3-V LVTTL voltage levels because the upper-order portion does not have level shifters.

Figure 2 and Figure 3 show two photos demonstrating the proper mating of a GPSI16 and a GPSI32 DUTboard to the SPIO4.

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Figure 2. GPSI 16 DUT to SPIO4 Mating

Figure 3. GPSI 32 DUT to SPIO4 Mating

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2.5.1 Level ShiftersThe board incorporates level shifters to allow flexible output voltages on the unidirectional SPI signals ofGPSI-16 port, as shown in Figure 1. VDDIO, a supply voltage from the GPSI-16/32 connector coming fromthe DUT board, provides the voltage to the output side of the level translators. If the DUT has no specialrequirements for voltage and simply needs basic 3.3-V signal levels, the 3.3-V output from the GPSIconnector can be connected to VDDIO on the DUT board. The level shifters are unidirectional. If VDDIO isnot provided, the level shifters enter a shutdown state with all input pins in a tri-state condition. The statepassed along to the processor in this case is logic low. Table 4 shows the full list of available level-shifterconfigurations.

Table 4. GPSI-32 Signals

Pin # Signal Name Signal Function Voltage Level Direction(From SPIO-4)

Pins 1-16 form the GPSI-16 subset:1 SCS0_A~ Serial Bus A – Chip select for device 0. 1.65 V to 5.5 V Output2 GND Ground N/A N/A3 SCK_A Serial Bus A – Serial clock from the master to the device. 1.65 V to 5.5 V Output

4 DUT_Present~ The DUT board grounds this pin. The SPIO-4 senses this pin todetermine the DUT board presence. N/A Input

5 SMISO_A

Serial Bus A – Data from the slave (device) to the master. Thedevice may implement this as a tri-state signal that can be drivenby multiple devices on Serial Bus A in a bussed fashion. The pullupresistor, if required, is on the DUT board.

1.65 V to 5.5 V Input

6 Dev_INT~/SDRDY_A~

In certain applications, if required, this pin serves as the DRDY~signal from the DUT to the SPIO-4. In other cases, this pin may bea general interrupt pin from the device to the SPIO-4. On the SPIO-4 board, this signal connects to an interrupt pin on themicrocontroller.

1.65 V to 5.5 V Input

7 SMOSI_A Serial Bus A – Data from the master to the slave (device). 1.65 V to 5.5 V Output8 SCS1_A~ Serial Bus A – Chip select for device 1. 1.65 V to 5.5 V Output

9 Ref_CLK Reference clock from the DUT board to the SPIO-4 board. If notused, the DUT board should ground this pin. 1.65 V to 5.5 V Input

10 GND Ground N/A N/A

11 SDA Data line of the I2C bus. Pulled up to +3.3V_DUT on the SPIO-4board through a 1.5-kΩ resistor. 3.3 V Bidirectional

12 SCL Clock line of the I2C bus. Pulled up to +3.3V_DUT on the SPIO-4board through a 1.5-kΩ resistor. 3.3 V Bidirectional

13 +3.3V_DUT

Switched by the SPIO-4 conditional parameter on theDUT_Present pin. The ID EEPROM and the entire I2C bus on theDUT board must be unconditionally powered by this supply.Maximum peak current = 50 mA (subject to total power budget limitof 200 mW over both supplies). Maximum capacitor loading for thisnode is not to exceed 50 µF.

3.3 V Output

14 +5V_DUT

This supply is sourced by the SPIO-4 and is intended to power thecore functionality of the DUT board, if desired. Nominal current =35 mA. Maximum peak current = 50 mA (subject to total powerbudget limit of 200mW over both supplies). If power from the SPIO-4 is not required, the DUT board must leave this pin open.Maximum capacitor loading for this node is not to exceed 50 µF.

5.0 V Output

15 VDDIO 1.65 V to 5.5 V Input16 SCS2_A~ 1.65 V to 5.5 V Output

17 DUT_PWR_Enable 3.3 V Output

18 Available for implementation-specific use. Refer to the DUT boardmanual. If unused, leave it open. (Possible use: DUT_RESET~) 3.3 V N/A

19 Available for implementation-specific use. Refer to the DUT boardmanual. If unused, leave it open. 3.3 V N/A


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Table 4. GPSI-32 Signals (continued)

Pin # Signal Name Signal Function Voltage Level Direction(From SPIO-4)



23 SCS0_B~

Available for implementation-specific use. Refer to the DUT boardmanual. If unused, leave it open.If a second SPI bus is implemented, then use this pin as shown:Serial Bus B – Chip select for device 0.

3.3 V N/A

24 SDRDY_B~

Available for implementation-specific use. Refer to the DUT boardmanual. If unused, leave it open.If a second SPI bus is implemented, then use this pin as shown:In certain SPI applications, if required, this pin serves as theDRDY~ signal from the DUT to the SPIO-4.

3.3 V N/A

25 SCK_B

Available for implementation-specific use. Refer to the DUT boardmanual. If unused, leave it open.If a second SPI bus is implemented, then use this pin as shown:Serial Bus B – Serial clock from the master to the device.

3.3 V N/A

26 SCS1_B~


3.3 V N/A

27 SMISO_B

Available for implementation-specific use. Refer to the DUT boardmanual. If unused, leave it open.If a second SPI bus is implemented, then use this pin as shown:Serial Bus B – Data from the slave (device) to the master. Thedevice may implement this as a tri-state signal that can be drivenby multiple devices on Serial Bus B in a bussed fashion. The pullupresistor, if required, is on the DUT board.

3.3 V N/A

28 SCS2_B~


3.3 V N/A

29 SMOSI_B

Available for implementation-specific use. Refer to the DUT boardmanual. If unused, leave it open.If a second SPI bus is implemented, then use this pin as shown:Serial Bus B – Data from the master to the slave (device).

3.3 V N/A

30 SCS3_B~

Available for implementation-specific use. Refer to the DUT boardmanual. If unused, leave it open.If a second SPI bus is implemented, then use this pin as shown:Serial Bus B – Chip Select for device 3.

3.3 V N/A

31 Reserved Reserved for future use. The DUT board leaves this pin open. 3.3 V N/A32 GND Ground N/A N/A

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2.6 Auxiliary InterfaceThe SPIO-4 board can be connected to auxiliary test equipment through debug connector J4 located onthe board.

2.7 Computer InterfaceThe SPIO-4 board communicates with a PC via standard USB 2.0 at high-speed (up to a 480 Mbits/secsignaling rate). The board is fully backward-compatible with USB 1.1 devices and cables.

2.8 MemoryThe SPIO-4 board comes with 8M × 16 bits of PSRAM for data storage. The memory is a single MicronMT45W8MW16BGX PSRAM configured for asynchronous accesses. In asynchronous configuration, thefastest access speed is 70 ns latency, or approximately 14.2 MHz per 16-bit transfer. Both the processorand the FPGA have read and write access to the PSRAM. The processor’s static memory interfacemastership is controlled by firmware within the processor because there is no hardware mechanism toshare the bus.

2.9 Power RequirementsThe SPIO-4 data capture board can be solely powered using the USB interface power, but can also bepowered by an external power supply. The SPIO-4 data capture board consumes up to 500 mA of currentdepending on the DUT load. ADC evaluation boards differ widely in their power consumption; consult themanual that came with your evaluation board, and verify if an external supply is required for your DUTboard. External power can be supplied via J10, and must be greater than 4.5 V and less than 6.0 V dcwith a current rating of at least 1 A.

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U5XC6SLX16 FPGA

324 FBGA18x18

U4PSRAM

U11LP3910

1.2 V, 1.8 V,3.3 V

SW1

U1SAM3U

100 LQFP16x16

U10

U9

U6

U8

U7

J8USB

J6 G

PS

I-16

/32

SW2

ExtPwrJ10

JTA

G D

ebugC

onnector

J3

JP1J4 J1

J7SD

Card

U125 V

J2J14

5"

3"

J9

DUT5 V

D8

DUT3.3 V

D7

SPIO3.3 V

D5

PSRAM1.8 V

D6

FPGA1.2 V

D11

D4 D3 D2 D1D10

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3 PCB Layout, Schematics, and Bill of MaterialsThe following section shows the printed circuit board (PCB) layout overview, the schematics, and the billof materials (BOM).

3.1 PCB Layout OverviewFigure 4 shows the component side of the SPIO-4 board layout.

Figure 4. SPIO-4 Board Layout – Component Side

Figure 5. Board Photo Showing Respective Layout From Figure 4

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8MBx16PSRAM

(U4)

Spartan 6XC6SLX16

(U5)

IO Voltage

A23-1

D15-0

NCS0

NWR

NRD

NBS0-1

NCS2 NCS3/FPGA_CFG

LP3910MultipleSupply

SwitchingRegulator

(U11)

JTAG(J2)

DEBUG(J4)

Micro-ControllerAtmel SAM3U

(U1)

USBConnector

(J8)

USB

SDCard(J7)

Static Mem intrfc

GPIO

3.3 V

DebugConnector

(J1)

DebugConnector

(J9)

12 MHZXtal

32 kHZXtal

InputProtection

Ext Pwr(J10)

DUT3.3V_EN

BoostRegulator

(U12)Filter

DUT 5 V

>Level Shift

GPSI A

GPSI A

<Level Shift

3.3 V DUT

3.3 V DUT

I2C(SCL)

I2C(SCL)

3.3 V

DUT 3.3 V

GPSI B

DUT 3.3 V

VDDIO

GPSI A

GPSI A

DUT 5 V

GPSI 32Connector

(J6)

DUT3.3V_EN

Pins 1, 3, 7, 8, 16

Pins 5, 6, 9

Pin 15

Pin 12

Pin 11

Pin 13

Pin 14

Pin 23-30

I2C

USB 5 V

1.8 V

1.2 V

PCB Layout, Schematics, and Bill of Materials www.ti.com




3.2 SchematicsThe following pages show the schematics of the board. These are provided for general informationpurposes only. TI reserves the right to make modifications to the board design at any time.

Figure 6. SPIO-4 Interface Board Block Diagram

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Atmel ARM Microcontroller - Power, Debug, Analog

OSC_32768HZ_SMD

74LVC2G06

OSCIL_12M_SMD_3.3V

1.0K

499R

DFSD_MDFSD_P

XOUT1XIN_CLK

VBG

XOUT32XIN32_CLK

XOUT1

XIN_CLK

VBG

CLK_12MHZA_R

CLK_32K_R XIN32_CLK

CLK_12MHZA

XIN32_CLK

XOUT32

CLK_12MHZ1_R

CLK_12MHZ2_R

XIN_CLK

VDDBU

DGND

DGND

DGND

VUTMI

VANA

DGND

DGND

DGND

DGND

3p3V

3p3V

DGND

DGND

DGND

DGND

3p3V

3p3V

DGND

3p3V

3p3V

VCORE

DGND

3p3V

3p3V

VCORE

VUTMI

VANA

DGND

DGND

DGND

DGND

DGND

DGND

DGND

VANA

3p3V

3p3V

DGND

NRST_PWR11

TDI9TDO9TMS9TCK9

DHSD_M9DHSD_P9

RSTN9

CLK_12MHZ 5

C310.1uFC310.1uF

C90.1uFC90.1uF

SW1SW1A B

C230.1uFC230.1uF

U3

DNS

U3

DNS

OE1

GND2

OUT3

VDD4

C60.1uFC60.1uF

C180.1uFC180.1uF

C21

10pF

C21

10pF

R3 39RR3 39R

C19

10uF

C19

10uF

C24 15pFC24 15pFL110uH/100mAL110uH/100mA

Y232.768KHz

Y232.768KHz

R7

DNS

R7

DNS

C170.1uFC170.1uF

R5

0R

R5

0RC22

10uF

C22

10uF

C150.1uFC150.1uF

C260.1uFC260.1uF

C3

10uF

C3

10uF

R71

DNS

R71

DNS

JP1 JPJP1 JP

C13

10uF

C13

10uF

U1BSAM3UU1BSAM3U

NRST11

TDI1

TDO/TRACESWO4

TMS/SWDIO7

TCK/SWCLK9

VBG39

DHSDP37

DHSDM38

DFSDM41

DFSDP42

FWUP135

SHDN136

ERASE137

TEST138

NRSTB141

XIN32144

XOUT32143

XIN36

XOUT35

ADVREF74

AD12BVREF76

VDDCORE116

VDDCORE227

VDDCORE344

VDDCORE450

VDDCORE586

VDDCORE6125

VDDOUT2

VDDIN3

VDDIO117

GND118

GNDPLL33

VDDUTMI40

GNDUTMI43

VDDIO251

GND252

GND360

VDDANA73

GNDANA75

VDDIO385

GND490

VDDIO4104

GND5126

VDDIO5127

VDDBU139

GNDBU140

VDDPLL34

JTAGSEL142

C30 15pFC30 15pF

C120.1uFC120.1uF

C28

4.7uF

C28

4.7uF

U13

DNS

U13

DNS

1A1

GND2

2A3

2Y4

VCC5

1Y6

C591.0uFC591.0uF

C140.1uFC140.1uF

C29 15pFC29 15pF

C160.1uFC160.1uF

R67

DNS

R67

DNS

L210uH/100mAL210uH/100mA

C40.1uFC40.1uF

C5

10uF

C5

10uF

R69

DNS

R69

DNS

C80.1uFC80.1uF

R4

6.8K

R4

6.8K

Y112.000MHz

Y112.000MHz

R660R R660R

C200.1uFC200.1uF

R6

0R

R6

0R

R68

DNS

R68

DNS

C100.1uFC100.1uF

C20.1uFC20.1uF

R8

DNS

R8

DNS

R2 39RR2 39R C110.1uFC110.1uF

C32

4.7uF

C32

4.7uF

C1

10nF

C1

10nF

C270.1uFC270.1uF

R70

DNS

R70

DNS

U2

DNS

U2

DNS

OE1

GND2

OUT3

VDD4

C70.1uFC70.1uF

R1 DNSR1 DNS

C25 15pFC25 15pF





Figure 7. Atmel ARM Microcontroller: Power, Debug, and Analog

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Atmel ARM Microcontroller, Port Connection

UART Debug Interface header

USNAP INTERFACE

PCB REVISION RESISTORS

R82 R83 PCB REV

DNS DNS A

1.5K DNS B

DNS 1.5K C

___ ___ ______

D0D1D2D3

D7

D4

D6D5

D11

D8

D9

D15

D12

D9

D13D14

A13

A5

A9

A4

A8

A2

A11

A3

A7A6

A12

A10

A17

A21

A16

A20

A14A15

A19A18

A22

A1

A23

RXD_INTXD_OUT

USNAP_SEL_NUSNAP_IRQ_NUSNAP_SCLK_NUSNAP_MOSIUSNAP_MISOUSNAP_RST_N

NWEA22

D14

D10D11

D8D9

D13

A17

A14A15A16

A23A20

A18A19

D12

A21NCS0

NBS0D15

D2

D0A1

D6D5D4D3

D1

NRD

D7

USNAP_RST_NA13

A5

A9

DA3DA2DA1DA0CDA

NBS1

A4

A8

A2

A11

A3

A7A6

A12

A10

CK

RXD_INTXD_OUT

USNAP_SCLK_NUSNAP_MOSIUSNAP_MISO

USNAP_SEL_NUSNAP_IRQ_N

DUT_SDA

DUT_SCL

SDA

SCL

CD

USNAP_RST_N

USNAP_IRQ_N

3p3V

DGND

3p3V

DGND

DGND

D[15:0] 4,5

A[23:1] 4,5

NWE 4,5

NWAIT 4,5

NCS0 4,5NRD 4,5

NBS0 4,5

NCS3 5

DUT_PWR_EN 7

DUT_PRSNT_N 7

FPGA_DONE_N 6

FPGA_M0 5FPGA_M1 5FPGA_PRGM_N 6

FPGA_INIT_N 5

PCK1 5

IRQ_PWR_N 11

CPU_CS1N_A 7

NCS2 5

CPU_MOSI_A7

SDA11

CPU_CS2N_A7

SCL11

NBS14,5

DA28DA38

DA08DA18

CDA8CK8

VUSB_DET9,11

CPU_SCLK_A7CPU_CS0N_A7

DUT_SDA7

DUT_SCL7

ONSTAT11USBISEL11

SCC_TD5

SCC_TF5

PCK5SCC_CLK5

SRAM_CNTRL_REG4

DUTDRDYN_A7

CPUMISO_A7

DUT_5VEN 11DUT_3VEN 11

DUTCLKIN7CD8

TP17TP17

1

R82 1.5KR82 1.5K

TP19TP19

1

J1

hdr_5pin

J1

hdr_5pin

11

22

33

44

55

TP7TP7

1

J14

2mm_hdr_6pin

J14

2mm_hdr_6pin

11

22

33

44

55

66

77

88

99

1010

U1ASAM3UU1ASAM3U

PA0/WKUP0109

PA1/WKUP1111

PA2/WKUP2113

PA3/CK115

PA4/CDA117

PA5/DA0119

PA6/DA1121

PA7/DA2123

PA8/DA3128

PA9/TWD0130

PA10/TWCK0132

PA11/URXD133

PA12/UTXD134

PA13/MISO87

PA14/MOSI88

PA15/SPCK91

PA16/NPCS093

PA17/WKUP795

PA18/WKUP899

PA19/WKUP9100

PA20/TXD1101

PA21/RXD1102

PA22/RTS177

PA23/CTS2103

PA24/WKUP11105

PA25/WKUP12106

PA26/TD107

PA27/PCK064

PA28/TK45

PA29/PWMH146

PA30/TF78

PA31/RF48

PB0/PWMH053

PB1/PWMH155

PB2/PWMH257

PB3/AD12BAD279

PB4/AD12BAD380

PB5/AD165

PB6/D1566

PB7/A0/NBS067

PB8/A168

PB9/D031

PB10/D130

PB11/D259

PB12/D361

PB13/D462

PB14/D529

PB15/D697

PB16/D796

PB17/NANDOE26

PB18/NANDWE25

PB19/NRD24

PB20/NCS023

PB21/A21/NANDALE21

PB22/A22/NANDCLE20

PB23/NWR0/NWE19

PB24/NANDRDY15

PB25/D814

PB26/D913

PB27/D1012

PB28/D1110

PB29/D128

PB30/D136

PB31/D145

PC0/A2110

PC1/A3112

PC2/A4114

PC3/A5116

PC4/A6118

PC5/A7120

PC6/A8122

PC7/A9124

PC8/A10129

PC9/A11131

PC10/A1289

PC11/A1392

PC12/NCS194

PC13/RXD398

PC14/NPCS228

PC15/NWR1/NBS181

PC16/NCS282

PC17/AD12BAD683

PC18/AD12BAD784

PC19/NPCS132

PC20/A14108

PC21/A1522

PC22/A1647

PC23/A1749

PC24/A1854

PC25/A1956

PC26/PWMH258

PC27/A2363

PC28/DA469

PC29/DA570

PC30/DA671

PC31/DA772

R83 DNSR83 DNS

TP4TP4

1





Figure 8. Atmel ARM Microcontroller and Port Connection

http://www.ti.com


MT45W8MW16BGX

D0D1D2D3

D7

D4

D6D5

D11

D8

D10

D15

D12

D9

D13D14

A4

A14

A3

A8

A5

A2

A15

A6

A10

A12

A16

A7

A13

A9

A11

A19A18A17

A1

A22A21A20

A23

DGND

1p8V3p3V

DGND

3p3V

DGND

A[23:1]3,5

D[15:0]3,5

NWAIT 3,5

NCS03,5NRD3,5NWE3,5

NBS13,5NBS03,5

SRAM_CNTRL_REG3,5

C341.0uFC341.0uF C35

0.1uFC350.1uF

C37

10uF

C37

10uF

C330.1uFC330.1uF C36

0.1uFC360.1uF

U4

MT45W8MW16BGX

U4

MT45W8MW16BGX

A1A4 A0A3

CREA6

A2A5

LBA1

OEA2

DQ8B1

UBB2

A3B3

A4B4

CSB5

DQ0B6

DQ9C1

DQ10C2

A5C3

A6C4

DQ1C5

DQ2C6

VSSQD1

DQ11D2

A17D3

DQ14F1DQ13F2

VSSQE6

DQ6F6

DQ4E5

VCCQE1

A16E4 A15F4 A14F3

DQ15G1

DQ5F5

A7D4

DQ12E2

DQ3D5

VCCD6

A9H3

A18H1

A8H2

A20H6

A10H4

A11H5

A19G2

A12G3

A13G4

WEG5

DQ7G6

WAITJ1

CLKJ2 ADVJ3

RFU3J5

RFU4J6

A21E3

A22J4





Figure 9. SPIO4 PSRAM

http://www.ti.com


REQUIRED SIGNALS TO CONFIG FPGA

RDWR_B T5

VIA SERIAL OR BYTE WIDE (SELECTMAP)

CSI_B T13

CCLK R15

DO_DIN R13D1 T14D2 V14D3 U5D4 V5D5 R3D6 T3D7 R5

INIT U3

M0 T15M1 N12

RSTUFF OPTIONS TO SUPPORT

SERIAL AND PARALLEL FPGA CONFIG

NOTE:D0-7 SWAPPED GOING INTO CONFIG BITS

D2

D1

D0

D4

FPGA_CFG_CSN

D6D5

D11

D8

D10

D15

D12

D9

D13D14

A1

A23

A4

A14

A3

A8

A5

A2

A15

A6

A10

A12

A16

A7

A13

A9

A11

A19A18A17

A22A21A20

NBS1NBS0

NWAIT

NCS0

NRDA1

A17

A21

A16

A20

A14A15

A19A18

A22A23

D0D1D2D3

D7

D4

D6D5

D11

D8

D9

D15

D12

D9

D13D14

A13

A5

A9

A4

A8

A2

A11

A3

A7A6

A12

A10

FPGA_CCLK

FPGA_CFG_CSN

DATA_D7_CFG_D0

FPGA_CCLK

D7

DATA_D7_CFG_D0

DATA_D7_CFG_D0

D3

DGND

3p3V

DGND

3p3V

3p3V

NWE3,4

FPGA_INIT_N3

FPGA_M13

FPGA_M03

NRD3,4

NCS03,4

NBS13,4NBS03,4

NWAIT3,4

D[15:0]3,4

A[23:1]3,4

SCC_TD3

NCS33

SCC_TF3

CLK_12MHZ2

PCK13

PCK3

SCC_CLK3

NCS23

R73DNS R73DNS

R75DNS R75DNS

R77DNS R77DNS

C430.1uFC430.1uF

C440.1uFC440.1uF

C45

10uF

C45

10uF

R740R R740R

R760R R760R

R780R R780R

U5-2

XC6SLX9CSG324

U5-2

XC6SLX9CSG324

IO_L44N_A2_M1DQ7_1J18

IO_L45N_A0_M1LDQSN_1K18

IO_L45P_A1_M1LDQS_1K17

IO_L41N_GCLK8_M1CASN_1K16

IO_L44P_A3_M1DQ6_1J16

IO_L42P_GCLK7_M1UDM_1L15

IO_L41P_GCLK9_IRDY1_M1RASN_1K15

IO_L36N_A8_M1BA1_1H14

IO_L29P_A23_M1A13_1C17

IO_L29N_A22_M1A14_1C18

IO_L31P_A19_M1CKE_1D17

IO_L31N_A18_M1A12_1D18

IO_L33P_A15_M1A10_1E16

IO_L33N_A14_M1A4_1E18

IO_L35N_A10_M1A2_1F18

IO_L35P_A11_M1A7_1F17

IO_L1N_A24_VREF_1F16

IO_L1P_A25_1F15

IO_L38N_A4_M1CLKN_1G18

IO_L38P_A5_M1CLK_1G16

IO_L43N_GCLK4_M1DQ5_1H18

IO_L43P_GCLK5_M1DQ4_1H17

IO_L37N_A6_M1A1_1H16

IO_L37P_A7_M1A0_1H15

IO_L49N_M1DQ11_1P18

IO_L49P_M1DQ10_1P17

IO_L51P_M1DQ12_1T17

IO_L52P_M1DQ14_1U17

IO_L48N_M1DQ9_1N18

IO_L48P_HDC_M1DQ8_1N17

IO_L50N_M1UDQSN_1N16

IO_L74P_AWAKE_1P15

IO_L74N_DOUT_BUSY_1P16

IO_L47N_LDC_M1DQ1_1M18

IO_L47P_FWE_B_M1DQ0_1M16

IO_L50P_M1UDQS_1N15

IO_L53N_VREF_1N14

IO_L46N_FOE_B_M1DQ3_1L18

IO_L46P_FCS_B_M1DQ2_1L17

IO_L42N_GCLK6_TRDY1_M1LDM_1L16

IO_L51N_M1DQ13_1T18

IO_L52N_M1DQ15_1U18

IO_L30P_A21_M1RESET_1F14

IO_L30N_A20_M1A11_1G14

IO_L32P_A17_M1A8_1H12

IO_L32N_A16_M1A9_1G13

IO_L34P_A13_M1WE_1K12

IO_L34N_A12_M1BA2_1K13

IO_L36P_A9_M1BA0_1H13

IO_L39P_M1A3_1J13

IO_L39N_M1ODT_1K14

IO_L40P_GCLK11_M1A5_1L12

IO_L40N_GCLK10_M1A6_1L13

IO_L53P_1M14

IO_L61P_1L14

IO_L61N_1M13

VCCO_1E17

VCCO_1G15

VCCO_1J14

VCCO_1J17

VCCO_1M15

VCCO_1R17

C410.1uFC410.1uF

U5-3

XC6SLX9CSG324

U5-3

XC6SLX9CSG324

IO_L62P_D5_2R3

IO_L65P_INIT_B_2U3

IO_L63P_2T4

IO_L49P_D3_2U5

IO_L48N_RDWR_B_VREF_2T5

IO_L43N_2V7

IO_L43P_2U7

IO_L46N_2T7

IO_L41N_VREF_2V8

IO_L41P_2U8

IO_L31N_GCLK30_D15_2T8

IO_L30N_GCLK0_USERCCLK_2V10

IO_L30P_GCLK1_D13_2U10

IO_L29N_GCLK2_2T10

IO_L23P_2U11

IO_L16N_VREF_2T11

IO_L14N_D12_2V13

IO_L14P_D11_2U13

IO_L3N_MOSI_CSI_B_MISO0_2T13

IO_L12N_D2_MISO3_2V14

IO_L12P_D1_MISO2_2T14

IO_L1N_M0_CMPMISO_2T15

IO_L2N_CMPMOSI_2V16

IO_L2P_CMPCLK_2U16

IO_L45N_2V6

IO_L65N_CSO_B_2V3

IO_L63N_2V4

IO_L49N_D4_2V5

IO_L32N_GCLK28_2V9

IO_L45P_2T6

IO_L23N_2V11

IO_L62N_D6_2T3

IO_L1P_CCLK_2R15

IO_L3P_D0_DIN_MISO_MISO1_2R13

IO_L13P_M1_2N12

IO_L13N_D10_2P12

IO_L16P_2R11

IO_L29P_GCLK3_2R10

IO_L31P_GCLK31_D14_2R8

IO_L32P_GCLK29_2T9

IO_L46P_2R7

IO_L48P_D7_2R5

IO_L64P_D8_2N5

IO_L64N_D9_2P6

VCCO_2P9

VCCO_2R12

VCCO_2R6

VCCO_2U14

VCCO_2U4

VCCO_2U9

C400.1uFC400.1uF

C420.1uFC420.1uF

C471.0uFC471.0uF





Figure 10. SPIO-4 FPGA SRAM and Configuration Interface

http://www.ti.com


XILINX JTAG HDR FOR CONFIG OR CHIPSCOPE

JUMER TO SELECT BANK VOUT

DONE V17

PROGRAM V2

DBG4DBG6DBG8DBG10DBG12DBG14DBG16DBG18DBG20DBG22

DBG2


DBG24

DBG46DBG48



DBG23

DBG47DBG45

DBG1

FPGA_TDOFPGA_TMS

FPGA_TCKFPGA_TDI

BNK3_VDDIO

DBG9DBG10DBG11DBG12DBG13DBG14DBG15DBG16DBG17DBG18DBG19DBG20

DBG31


DBG7DBG8

DBG1DBG2DBG3DBG4DBG5DBG6

DBG47

DBG45DBG46

DBG48

DBG43DBG44

DBG34DBG35DBG36DBG37DBG38DBG39DBG40DBG41DBG42

DBG32DBG33

BNK3_VDDIO

DGND

3p3V1p2V

DGND

DGND DGND

3p3V

3p3V

DGND

3p3V

VTEST

DGND

DGND

DGND

1p2V

3p3V

DGNDDGND

3p3V

3p3V

FPGA_DONE_N3FPGA_PRGM_N3

C520.1uFC520.1uF

U5-5

XC6SLX9CSG324

U5-5

XC6SLX9CSG324

TCKA17

TDID15

TMSB18

TDOD16

SUSPENDR16

CMPCS_B_2P13

DONE_2V17

PROGRAM_B_2V2

GNDA1

GNDA18

GNDB13

GNDB7

GNDC16

GNDC3

GNDD10

GNDD5

GNDE15

GNDG12

GNDG17

GNDG2

GNDG5

GNDH10

GNDH8

GNDJ11

GNDJ15

GNDJ4

GNDJ9

GNDK10

GNDK8

GNDL11

GNDL9

VCCAUXB1

VCCAUXB17

VCCAUXE14

VCCAUXE5

VCCAUXE9

VCCAUXG10

VCCAUXJ12

VCCAUXK7

VCCAUXM9

VCCAUXP10

VCCAUXP14

VCCAUXP5

VCCINTG7

VCCINTH11

VCCINTH9

VCCINTJ10

VCCINTJ8

VCCINTK11

VCCINTK9

VCCINTL10

VCCINTL8

VCCINTM12

VCCINTM7

GNDM17

GNDM2

GNDM6

GNDN13

GNDR1

GNDR14

GNDR18

GNDR4

GNDR9

GNDT16

GNDU12

GNDU6

GNDV1

GNDV18

C560.1uFC560.1uF

C491.0uFC491.0uF

D1 GRN_LEDD1 GRN_LED

C570.1uFC570.1uF


C58

10uF

C58

10uF C600.1uFC600.1uF

R9 750RR9 750R

C610.1uFC610.1uF

C62

10uF

C62

10uF

TP20TP20

1

U5-4

XC6SLX9CSG324

U5-4

XC6SLX9CSG324

IO_L54N_M3A11_3D3

IO_L54P_M3RESET_3E4

IO_L50P_M3WE_3E3

IO_L55P_M3A13_3F6

IO_L55N_M3A14_3F5

IO_L51P_M3A10_3F4

IO_L51N_M3A4_3F3

IO_L53N_M3A12_3G6

IO_L53P_M3CKE_3H7

IO_L49P_M3A7_3H6

IO_L49N_M3A2_3H5

IO_L44P_GCLK21_M3A5_3H4

IO_L44N_GCLK20_M3A6_3H3

IO_L47P_M3A0_3J7

IO_L47N_M3A1_3J6

IO_L45N_M3ODT_3K6

IO_L40P_M3DQ6_3J3

IO_L42N_GCLK24_M3LDM_3K3

IO_L42P_GCLK25_TRDY2_M3UDM_3K4

IO_L43N_GCLK22_IRDY2_M3CASN_3K5

IO_L43P_GCLK23_M3RASN_3L5

IO_L45P_M3A3_3L7

IO_L31P_3L6

IO_L39P_M3LDQS_3L4

IO_L83P_3C2

IO_L83N_VREF_3C1

IO_L52P_M3A8_3D2

IO_L52N_M3A9_3D1

IO_L50N_M3BA2_3E1

IO_L48P_M3BA0_3F2

IO_L48N_M3BA1_3F1

IO_L46N_M3CLKN_3G1

IO_L46P_M3CLK_3G3

IO_L41N_GCLK26_M3DQ5_3H1

IO_L41P_GCLK27_M3DQ4_3H2

IO_L40N_M3DQ7_3J1

IO_L38P_M3DQ2_3K2

IO_L38N_M3DQ3_3K1

IO_L37N_M3DQ1_3L1

IO_L37P_M3DQ0_3L2

IO_L36N_M3DQ9_3M1

IO_L35P_M3DQ10_3N2

IO_L35N_M3DQ11_3N1

IO_L1N_VREF_3N3

IO_L34N_M3UDQSN_3P1

IO_L34P_M3UDQS_3P2

IO_L2N_3P3

IO_L33N_M3DQ13_3T1

IO_L33P_M3DQ12_3T2

IO_L32N_M3DQ15_3U1

IO_L32P_M3DQ14_3U2

IO_L36P_M3DQ8_3M3

IO_L2P_3P4

IO_L1P_3N4

IO_L31N_VREF_3M5

IO_L39N_M3LDQSN_3L3

VCCO_3E2

VCCO_3G4

VCCO_3J2

VCCO_3J5

VCCO_3M4

VCCO_3R2

J4

50PIN_MALE_HDR

J4

50PIN_MALE_HDR

1 23 45 67 89 10

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50

R11 750RR11 750R

R10 750RR10 750R

U5-6

XC6SLX9CSG324

U5-6

XC6SLX9CSG324

NC1E7

NC2E8

NC3F7

NC4E6

NC5G8

NC6F8

NC7G11

NC8F10

NC9F11

NC10E11

NC11D12

NC12C12

NC13C13

NC14A13

NC15F12

NC16E12

NC17U15

NC18V15

NC19T12

NC20V12

NC21N10

NC22P11

NC23M10

NC24N9

NC25M11

NC26N11

NC27N7

NC28P8

NC29M8

NC30N8

NC31N6

NC32P7

C101

100uF

C101

100uF

C540.1uFC540.1uF

C530.1uFC530.1uF

R12 750RR12 750R

C480.1uFC480.1uF

TP1TP1

1


C550.1uFC550.1uF

C100

100uF

C100

100uF

R72

10.0K

R72

10.0K


J3

hdr_3pin

J3

hdr_3pin

11

22

33

C631.0uFC631.0uFC51

0.1uFC510.1uF

J2

hdr_6pin

J2

hdr_6pin

11

22

33

44

55

66

TP3TP3

1C500.1uFC500.1uF





Figure 11. SPIO-4 FPGA DEBUG, JTAG Interfaces and Power

http://www.ti.com


DUT INPUT LEVEL SHIFTERS

DUT OUTPUT LEVEL SHIFTERS

RSTUFF OPTIONS TO SUPPORT CPU ONLY

CAPABILITY (NO FPGA)

DUT_VDDIO

REF_CLKASDRDYN_A

SCS1N_A_R

SCLK_A_R

SCS0N_A_R

SMOSI_A_R

SCS2N_A_R

DUTCS2N_A

SCS0N_ASCLK_A

DUT_SDA

DUT_VDDIO

SMISO_A

DUT_SCL

SMOSI_ASDRDYN_A

REF_CLKA

SCS0N_BSCLK_BSMISO_BSMOSI_B

SCS1N_BSCS2N_BSCS3N_B

SDRDYN_B

SCS2N_BSCS3N_B

SDRDYN_BSCS1N_B

SCS0N_BSCLK_BSMISO_BSMOSI_B

DUTCLKIN_R

DUTMISO_A_R

SCS1N_A

SCLK_A

SCS0N_A

SMOSI_A

SCS2N_A

DUTDRDYN_R

DUTSCLK_A

DUTCLKIN

DUTMISO_A

DUT_SDA

DUT_SCL

CPUMISO_A_R

SMISO_A

SCS2N_A

SCS1N_A

DUT_PWR_EN

DUT_PWR_EN

5VDUT_FLTERD

DUTMOSI_ADUTCS0N_A

DUTCS1N_A

3p3V

3p3V

DGND

DGND

DGND

DGND

DGND

3p3V

DGND

3p3V_DUT

DGND

DGND

3p3V

3p3V_DUT

DGND

DGND

DGND

DGND

5p0V_DUT

DUTCLKIN 3

DUT_SDA3

DUT_PWR_EN3

DUT_SCL 3

CPU_CS1N_A 3

DUTDRDYN_A 3

CPUMISO_A 3

CPU_SCLK_A 3

CPU_CS0N_A 3

CPU_MOSI_A 3

DUT_PRSNT_N 3

CPU_CS2N_A 3

DUT_VDDIO11

U5-1

XC6SLX9CSG324

U5-1

XC6SLX9CSG324

IO_L33N_0A8

IO_L39N_0A11

IO_L41N_0A12

IO_L37N_GCLK12_0A10

IO_L35N_GCLK16_0A9

IO_L62N_VREF_0A14

IO_L64N_SCP4_0A15

IO_L66N_SCP0_0A16

IO_L4N_0A3

IO_L6N_0A5

IO_L8N_VREF_0A6

IO_L5N_0A4

IO_L10N_0A7

IO_L1P_HSWAPEN_0D4

IO_L1N_VREF_0C4

IO_L2P_0B2

IO_L2N_0A2

IO_L3P_0D6

IO_L3N_0C6

IO_L4P_0B3

IO_L5P_0B4

IO_L6P_0C5

IO_L10P_0C7

IO_L8P_0B6

IO_L11P_0D8

IO_L11N_0C8

IO_L33P_0B8

IO_L34P_GCLK19_0D9

IO_L34N_GCLK18_0C9

IO_L35P_GCLK17_0B9

IO_L36P_GCLK15_0D11

IO_L36N_GCLK14_0C11

IO_L37P_GCLK13_0C10

IO_L38P_0G9

IO_L38N_VREF_0F9

IO_L39P_0B11

IO_L41P_0B12

IO_L62P_0B14

IO_L63P_SCP7_0F13

IO_L63N_SCP6_0E13

IO_L64P_SCP5_0C15

IO_L65P_SCP3_0D14

IO_L65N_SCP2_0C14

IO_L66P_SCP1_0B16

VCCO_0B10

VCCO_0B15

VCCO_0B5

VCCO_0D13

VCCO_0D7

VCCO_0E10

R53 0RR53 0R

R17 33RR17 33R

C990.1uFC990.1uF

C660.1uFC660.1uF

C640.1uFC640.1uF

R55 0RR55 0R

R57 0RR57 0R

C1080.1uFC1080.1uF

U8

SN74LVC2T45SSOP

U8

SN74LVC2T45SSOP

VCCA1

A12

A23

GND4DIRA2B5

B26 B17

VCCB8

C671.0uFC671.0uF

C690.1uFC690.1uF

R79 1.5KR79 1.5K

C73

10uF

C73

10uF

R20 33RR20 33R

R80 1.5KR80 1.5K

C1050.1uFC1050.1uF

R18 33RR18 33R

R16 33RR16 33R

R13 33RR13 33R

C460.1uFC460.1uF

C1040.1uFC1040.1uF

R54 DNSR54 DNS

J6

32PIN_FEM_HDR_RA

J6

32PIN_FEM_HDR_RA

1 23 45 67 89 10

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 32

U7

SN74LVC2T45SSOP

U7

SN74LVC2T45SSOP

VCCA1

A12

A23

GND4DIRA2B5

B26 B17

VCCB8

R59 0RR59 0R

R58 0RR58 0R

C700.1uFC700.1uF

C980.1uFC980.1uF

U10

SN74LVC2T45SSOP

U10

SN74LVC2T45SSOP

VCCA1

A12

A23

GND4DIRA2B5

B26 B17

VCCB8

C1030.47uFC1030.47uF

C1061.0uFC1061.0uF

C650.1uFC650.1uF

R15 33RR15 33R

C680.1uFC680.1uF

R56 0RR56 0R

C710.1uFC710.1uF

U6

SN74LVC2T45SSOP

U6

SN74LVC2T45SSOP

VCCA1

A12

A23

GND4DIRA2B5

B26 B17

VCCB8

C720.1uFC720.1uF

C1091.0uFC1091.0uF

R14 33RR14 33R

R19 33RR19 33R

U9

SN74LVC2T45SSOP

U9

SN74LVC2T45SSOP

VCCA1

A12

A23

GND4DIRA2B5

B26 B17

VCCB8





Figure 12. SPIO4 FPGA GPSI32 Interface

http://www.ti.com


Micro SD Card

DA2

CDADA3

CK

DA0DA1

CD

DGND

DGND

DGND

3p3V3p3V3p3V

3p3V

DA23DA33

DA03DA13

CDA3

CK3

CD 3

C740.1uFC740.1uF

R23

46.4K

R23

46.4K

R24

46.4K

R24

46.4K

R22

46.4K

R22

46.4K

C75

10uF

C75

10uF

R2110.0KR2110.0K

R25

46.4K

R25

46.4K R2610.0KR2610.0K

J7

MICRO_SD

J7

MICRO_SD

DAT21

CD/DAT32

CMD3

VDD4

CLK5

VSS6

DAT07

DAT18

GND19

GND210

GND311

GND412

CD13





Figure 13. SPIO-4 Micro SD Card

http://www.ti.com


USB, CPU JTAG

VUSB_DET

VUSB_RTN

VUSB_IN

DGNDDGND

DGND

DGND

DGND

3p3V

VUSB

DGND

DHSD_M2DHSD_P2

RSTN2

TDI2

TCK2

TDO2

TMS2

VUSB_DET3,11

R3010.0KR3010.0K

R28 46.4KR28 46.4K

C790.1uFC790.1uF

R3310.0KR3310.0K

R3210.0KR3210.0K

R3110.0KR3110.0K

C78

10pF

C78

10pF

F1

0R

F1

0R

J8USB TYPE B PORTJ8USB TYPE B PORT

VBUS1

D-2 D+3

GND4

E_GND05 E_GND16

C760.1uFC760.1uF

R27 0RR27 0R

R3410.0KR3410.0K

C77

4.7uF

C77

4.7uF

J9IDC20-2.54mmJ9IDC20-2.54mm

VTref1

Vsupply2

nTRST3

GND14

TDI5

GND26

TMS7

GND38

TCK9

GND410

RTCK11

GND512

TDO13

GND614

nSRST15

GND716

DBGRQ17

GND818

DBGACK19

GND920

R29

68K

R29

68K

R35 0RR35 0R

C80

10uF

C80

10uF





Figure 14. USB, CPU JTAG

http://www.ti.com


VinSwitching

Li-IonChrg

Circuit

Logic& Cntrl

LDO1

LDO2

Buck1

Buck2

Buck/Boost

5 Vin from Wall Supply

~5 Vin from USB

SAM3UCPU

VDDcore

VDDIO

NRST_PWR

3.3V_DUT_SW**

1.2V_FPGA**

1.8V_SRAM**

FPGAIO

3.3V_SPIO

FETSW

BOOSTReg 5 V

3.3V_DUT

SD Card

VDDIO

PSRAM

VDDIO VDDCore

1.8V_SRAM

FPGA

VDDIO VDDCore

IO

VDDIO

J4

3.3V_SPIO FPGAIO

J3

LP3910

3.3V_SPIO

LDO

I2C

TO DUT

1.2V_SRAM





Figure 15. SPIO-4 Power Distribution

http://www.ti.com


3.3V, 1.2V, 1.8V, DUT Power Supply

Test Points

Connector for using LI-Ion w/internal temp sense

TMP_SNS

1V2_SW

3V3_D_SW1

ISEN

IREF

VREFHVBATT

5VINVIN

CP1+

CP1-

VIN

PWR_ON

VBATT

DUT_VDDIO_MEAS

TP_CHGTP_STAT

TP_USBSPTP_PWRACK

3V3_D_SW2

TP_PWRACK

3V3_DUT_SW

3V3_DUT_SW

5V_DUT_OUT

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

1p2V

3p3V

1p8V

3p3V

DGNDDGND

DGND

DGND

DGND

DGND

1p2V 3p3V_DUT 5p0V_DUT3p3V 1p8V

DGND DGND

5p0V_DUT

3p3V

1p8V

1p2V

3p3V_DUT

VUSB

DGND

3p3V

VTEST

3p3V

DGND

DGND

3p3V

DGND

DGND

DGND

DGND

DGND

DGND

DGND

3p3V_DUT

3p3V

DGND

5p0V_DUT

DGND

DGND

SCL3

IRQ_PWR_N 3ONSTAT 3NRST_PWR 2

SDA3

DUT_VDDIO7

USBISEL3

VUSB_DET3,9

DUT_3VEN3

DUT_5VEN3

R62 100KR62 100K

TP22TP221

C81

1.0uF

C81

1.0uF

TP10TP10 1

TP16TP16

1

C86

4.7uF

C86

4.7uF

F2

PTC_1A_1812

F2

PTC_1A_1812

in1

out2

C90

10uF

C90

10uF

TP18TP18

1

U12

LM2750

U12

LM2750

VIN18

VIN29

C1+10

C1-7

VOUT11

VOUT22

SD_N4 GND1

3

GND25

GND36

GND4DAP

TP14TP14

1

D10

GRN_LED

D10

GRN_LED

R43 10.0KR43 10.0K

C91

10uF

C91

10uF

R52 121KR52 121K

TP9TP9 1

C110

10uF

C110

10uF

C87

10uF

C87

10uF

TP21TP211

D12

DIODE ZENER

D12

DIODE ZENER C89

10uF

C89

10uFPJ037A

J10

PJ037A

J10

TIP1

RING2

TP8TP8 1

TP11TP11

1

C107

10uF

C107

10uF

R41 1.5KR41 1.5K

C38

10uF

C38

10uF

L6

100MHZ FERRITE

L6

100MHZ FERRITEU14

FDG6342L_SC70-6

U14

FDG6342L_SC70-6

R21

VOUTB2VOUTA3

VIN4

OFF5 R1/C16

D6

GRN_LED

D6

GRN_LED

C94

10uF

C94

10uF

R4810.0KR4810.0K

C111

10uF

C111

10uF

L8

100MHZ FERRITE

L8

100MHZ FERRITE

C93

0.1uF

C93

0.1uF

R4710.0KR4710.0K

J13

DNS

J13

DNS

11

22

33

C92

100uF

C92

100uF

R63 680KR63 680K

C97

10uF

C97

10uF

D5

GRN_LED

D5

GRN_LED

U11

LP3910

U11

LP3910

TS1

VBATT12

AGND3

VREFH4

LDO2EN5

VLDO26VIN1

7VLDO1

8

POWERACK9

I_SEN10

ADC211 ADC112

~IRQB13

~NRST14

CHG15

STAT16

BUCK1EN17

VFB118

BCKGND119VBUCK120

VIN221

VIN322

VBUCK223

BCKGND224

VFB225

ON/~OFF26

I2C_SCL27

VDDIO28

I2C_SDA29

ONSTAT30

VBBFB31

VBBOUT32

VBBL233

BBGND134

VBBL135

VIN436

USBSUSP37

USBISEL38

BBGND239

DGND40

VDD341 VDD242

VBATT343 VBATT244

USBPWR45

VDD146

CHG_DET47

I_REF48

DAP49

D11

GRN_LED

D11

GRN_LED

J12

DNS

J12

DNS

+1

-2

R60

10.0K

R60

10.0K

R4610.0KR4610.0K

L3 2.2uHL3 2.2uH1 2

R45 1.5KR45 1.5K

R37 0RR37 0R

R44 1.5KR44 1.5K

C95

10uF

C95

10uF

C88

10uF

C88

10uF

C112

0.1uF

C112

0.1uF

Q1

MMBT3904

Q1

MMBT3904

32

1

TP5TP5

1 D7

GRN_LED

D7

GRN_LED

R85

10.0K

R85

10.0K

TP15TP15

1

C850.1uFC850.1uF

C39

10uF

C39

10uF

C83

10uF

C83

10uFR39 1.5KR39 1.5K

C82

10uF

C82

10uF

R42

650

R42

650

R64

10.0K

R64

10.0K

R36 750RR36 750R

C102

10uF

C102

10uF

R86

9.2K

R86

9.2K

L7

100MHZ FERRITE

L7

100MHZ FERRITE

C96

1.0uF

C96

1.0uF

R40

100K

R40

100K

L4 2.2uHL4 2.2uH1 2

R38 750RR38 750R

D8

GRN_LED

D8

GRN_LED

C84

4.7uF

C84

4.7uF

L5 2.2uHL5 2.2uH1 2

R49 10.0KR49 10.0K

R61 10.0KR61 10.0K

TP12TP12

1

SW2SW2A B

D9

DIODE_SCHOTTKY_1A

D9

DIODE_SCHOTTKY_1A

R51 4.64k_1%R51 4.64k_1%

TP13TP13

1





Figure 16. 3.3-V, 1.2-V, 1.8-V, and DUT Power Supplies

http://www.ti.com






3.3 Bill of Materials (BOM)Table 5 shows the bill of materials (BOM) for the SPIO-4 precision signal-path controller board.

Table 5. Bill of Materials

Item Description Qty Reference Manufacturer Name Manufacturer No.1 CAP CER 10000PF 25V Y5V 0603 1 C1 MURATA ELECTRONICS (VA) GRM188F51E103ZA01D2 CAP CER .47UF 10V X7R 0603 1 C103 TAIYO YUDEN (VA) LMK107B7474KA-T

3 CAP .10UF 16V CERAMIC X7R 0603 58

C2,C4,C6,C7,C8,C9,C10,C11,C12,C14,C15,C16,C17,C18,C20,C23,C26,C27,C31,C33,C35,C36,C40,C41,C42,C43,C44,C46,C48,C50,C51,C52,C53,C54,C55,C56,C57,C60,C61,C64,C65,C66,C68,C69,C70,C71,C72,C74,C76,C79,C85,C93,C98,C99,C104,C105, C108,C112

YAGEO (VA) CC0603KRX7R7BB104

4 CAP CERAMIC 10PF 50V NP0 0603 2 C21,C78 KEMET (VA) C0603C100J5GACTU5 CAP CER 15PF 50V C0G 5% 0603 4 C24,C25,C29,C30 TDK CORPORATION (VA) C1608C0G1H150J6 CAP CER 4.7UF 10V Y5V 0603 5 C28,C32,C77,C84,C86 MURATA ELECTRONICS (VA) GRM188F51A475ZE20D

7 CAP CER 10UF 6.3V Y5V 0603 22 C3,C5,C13,C19,C22,C37,C38,C39,C45,C58,C62,C73,C75,C80,C82,C83,C87,C88,C89,C90,C91,C102 TDK CORPORATION (VA) C1608Y5V0J106Z

8 CAP CER 1.0UF 10V X7R 0603 9 C34,C47,C49,C59,C63,C67,C81,C106,C109 TAIYO YUDEN (VA) LMK107B7105KA-T9 CAP CER 100UF 10V X5R 1210 3 C92,C100,C101 TAIYO YUDEN (VA) LMK325BJ107MM-T10 CAP CER 10UF 10V X5R 0805 6 C94,C95,C97,C107,C110,C111 JOHANSON DIELECTRICS INC (VA) 100R15X106KV4E11 CAP CER 1.0UF 16V X7R 20% 1206 1 C96 TDK CORPORATION (VA) C3216X7R1C105M/0.85

12 LED TOPLED 570NM GREEN CLR SMD 10 D1,D2,D3,D4,D5,D6,D7,D8,D10,D11 OSRAM OPTO SEMICONDUCTORSINC(VA) LG M67K-G1J2-24-0-2-R18-Z

13 DIODE ZENER 6.2V 3W DO214AA 1 D12 MICRO COMMERCIAL CO (VA) 3SMBJ5920B-TP14 DIODE SCHOTTKY 1A 20V SOD-123 1 D9 MICRO COMMERCIAL CO (VA) MBRX120LF-TP15 RES 0.0 OHM 1/2W 1210 SMD 1 F1 VISHAY/DALE (VA) CRCW12100000Z0EA16 PTC RESETTABLE 1.10A 16V 1812 1 F2 BOURNS INC (VA) MF-MSMF110/16-217 CONN HEADER VERT 5POS .100 TIN 1 J1 TYCO ELECTRONICS AMP 640454-518 CON PWR JCK 2.0 X 6.5MM W/O SW 1 J10 CUI INC PJ-037A19 CONN HEADER 10POS 2MM VERT T/H 1 J14 3M 951110-8622-AR20 CONN HEADER VERT SGL 6POS GOLD 1 J2 3M 961106-6404-AR21 BERGSTIK II .100" SR STRAIGHT 1 J3 FCI 68000-203HLF22 CONN FEMALE 32POS DL .1" R/A TIN 1 J6 SULLINS CONNECTOR SOLUTIONS PPTC162LJBN-RC23 CONN MICRO SD R/A HING TYPE SMD 1 J7 HIROSE ELECTRIC CO LTD (VA) DM3C-SF24 CONN RCPT USB TYPE B R/A PCB 1 J8 FCI 61729-0010BLF25 CONN HEADER 2.54MM 20POS GOLD 1 J9 SULLINS CONNECTOR SOLUTIONS SBH11-PBPC-D10-ST-BK26 BERGSTIK II .100" SR STRAIGHT 1 JP1 FCI 68001-202HLF

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Table 5. Bill of Materials (continued)Item Description Qty Reference Manufacturer Name Manufacturer No.27 INDUCTOR 10UH 100MA 0805 2 L1,L2 MURATA ELECTRONICS (VA) LQM21FN100M70L28 INDUCTOR 2.2UH 1.20A 20% 1210 3 L3,L4,L5 TDK CORPORATION (VA) NLCV32T-2R2M-PFR29 FERRITE CHIP 2700 OHM 200MA 0805 3 L6,L7,L8 MURATA ELECTRONICS (VA) BLM21BD272SN1L30 TRANSISTOR NPN GP 40V SOT23 1 Q1 MICRO COMMERCIAL CO (VA) MMBT3904-TP31 RES 33.0 OHM 1/10W 1% 0603 SMD 8 R13,R14,R15,R16,R17,R18,R19,R20 YAGEO (VA) RC0603FR-0733RL32 RES 39 OHM 1/10W 5% 0603 SMD 2 R2,R3 PANASONIC - ECG (VA) ERJ-3GEYJ390V

33 RES 10K OHM 1/10W 1% 0603 SMD 17 R21,R26,R30,R31,R32,R33,R34,R43,R46,R47,R48,R49,R60,R61, R64,R72,R85 STACKPOLE ELECTRONICS INC (VA) RMCF0603FT10K0

34 RES 46.4K OHM 1/10W 1% 0603 SMD 5 R22,R23,R24,R25,R28 STACKPOLE ELECTRONICS INC (VA) RMCF0603FT46K435 RES 68K OHM 1/10W 5% 0603 SMD 1 R29 PANASONIC - ECG (VA) ERJ-3GEYJ683V36 RES 1.5K OHM 1/10W 5% 0603 SMD 7 R39,R41,R44,R45,R79,R80,R82 STACKPOLE ELECTRONICS INC (VA) RMCF0603JT1K5037 RES 6.8K OHM 1/10W 1% 0603 SMD 1 R4 STACKPOLE ELECTRONICS INC (VA) RMCF0603FT6K8038 RES 100K OHM 1/10W 1% 0603 SMD 2 R40,R62 STACKPOLE ELECTRONICS INC (VA) RMCF0603FT100K39 RES 649 OHM 1/10W 1% 0603 SMD 1 R42 PANASONIC - ECG (VA) ERJ-3EKF6490V

40 RES 0.0 OHM 1/10W 0603 SMD 15 R5,R6,R27,R35,R37,R53,R55,R56,R57,R58,R59,R66,R74,R76,R78 STACKPOLE ELECTRONICS INC (VA) RMCF0603ZT0R00

41 RES 4.64K OHM 1/10W 1% 0603 SMD 1 R51 PANASONIC - ECG (VA) ERJ-3EKF4641V42 RES 121K OHM 1/10W 1% 0603 SMD 1 R52 STACKPOLE ELECTRONICS INC (VA) RMCF0603FT121K43 RES 680K OHM 1/10W 5% 0603 SMD 1 R63 PANASONIC - ECG (VA) ERJ-3GEYJ684V44 RES 9.1K OHM 1/10W 5% 0603 SMD 1 R86 PANASONIC - ECG (VA) ERJ-3GEYJ912V45 RES 750 OHM 1/10W 1% 0603 SMD 6 R9,R10,R11,R12,R36,R38 STACKPOLE ELECTRONICS INC (VA) RMCF0603FT750R

46 SWITCH TACT SPST W/O GND SMD 2 SW1,SW2 OMRON ELECTRONICS INC-ECB DIV(VA) B3U-1000P

47 PC TEST POINT MINIATURE SMT 14 TP1,TP3,TP4,TP5,TP7,TP11,TP12,TP13,TP14,TP15,TP16,TP17, TP18,TP19 KEYSTONE ELECTRONICS (VA) 5015

48 ATSAM3U4EA-AU-ND 1 U1 ATSAM3U4EA-AU-ND49 LP3910SQ-AA 1 U11 LP3910SQ-AA50 LM2750LD-5.0CT-ND 1 U12 LM2750LD-5.0CT-ND51 IC LOAD SWITCH INTEGRATED SC70-6 1 U14 FAIRCHILD SEMICONDUCTOR (VA) FDG6342L52 IC PSRAM 128MBIT 70NS 54VFBGA 1 U4 MICRON TECHNOLOGY INC (VA) MT45W8MW16BGX-701 IT TR53 XC6SLX16-2CSG324C 1 U5 XC6SLX16-2CSG324C54 IC BUS TRANSCVR 2BIT N-INV SM8 5 U6,U7,U8,U9,U10 TEXAS INSTRUMENTS (VA) SN74LVC2T45DCTR55 CRYSTAL 12.00 MHZ 8PF SMD 1 Y1 NDK (VA) NX5032GA 12MHZ AT-W56 CRYSTAL 32.768KHZ 12.5PF SMD 1 Y2 ABRACON CORPORATION (VA) ABS10-32.768KHZ-T57 PCB Fab 1 Fab TEXAS INSTRUMENTS (VA) 551600474-001

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Changes from Original (December 2010) to A Revision ................................................................................................ Page

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STANDARD TERMS FOR EVALUATION MODULES1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or

documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordancewith the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility

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2 Limited Warranty and Related Remedies/Disclaimers:2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License

Agreement.2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM

to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused byneglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that havebeen altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specificationsor instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality controltechniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.

2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or creditUser's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warrantyperiod to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair orreplace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall bewarranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) daywarranty period.

3 Regulatory Notices:3.1 United States

3.1.1 Notice applicable to EVMs not FCC-Approved:FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or softwareassociated with the kit to determine whether to incorporate such items in a finished product and software developers to writesoftware applications for use with the end product. This kit is not a finished product and when assembled may not be resold orotherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the conditionthat this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit mustoperate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:

CAUTIONThis device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may notcause harmful interference, and (2) this device must accept any interference received, including interference that may causeundesired operation.Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority tooperate the equipment.

FCC Interference Statement for Class A EVM devicesNOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 ofthe FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment isoperated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if notinstalled and used in accordance with the instruction manual, may cause harmful interference to radio communications.Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required tocorrect the interference at his own expense.

FCC Interference Statement for Class B EVM devicesNOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 ofthe FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residentialinstallation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordancewith the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interferencewill not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, whichcan be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or moreof the following measures:

• Reorient or relocate the receiving antenna.• Increase the separation between the equipment and receiver.• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.• Consult the dealer or an experienced radio/TV technician for help.

3.2 Canada3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247

Concerning EVMs Including Radio Transmitters:This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:(1) this device may not cause interference, and (2) this device must accept any interference, including interference that maycause undesired operation of the device.

Concernant les EVMs avec appareils radio:Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitationest autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doitaccepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.

Concerning EVMs Including Detachable Antennas:Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna typeand its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary forsuccessful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna typeslisted in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibitedfor use with this device.

Concernant les EVMs avec antennes détachablesConformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type etd'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillageradioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotroperayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Leprésent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans lemanuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antennenon inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation del'émetteur

3.3 Japan3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に

輸入される評価用キット、ボードについては、次のところをご覧ください。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page

3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certifiedby TI as conforming to Technical Regulations of Radio Law of Japan.

If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow theinstructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):1. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal

Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule forEnforcement of Radio Law of Japan,

2. Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect toEVMs, or

3. Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japanwith respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please notethat if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.

http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page


【無線電波を送信する製品の開発キットをお使いになる際の注意事項】開発キットの中には技術基準適合証明を受けていないものがあります。技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用

いただく。2. 実験局の免許を取得後ご使用いただく。3. 技術基準適合証明を取得後ご使用いただく。

なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。日本テキサス・イ

ンスツルメンツ株式会社東京都新宿区西新宿６丁目２４番１号西新宿三井ビル

3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page

3.4 European Union3.4.1 For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):

This is a class A product intended for use in environments other than domestic environments that are connected to alow-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment thisproduct may cause radio interference in which case the user may be required to take adequate measures.

4 EVM Use Restrictions and Warnings:4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT

LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling

or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety informationrelated to, for example, temperatures and voltages.

4.3 Safety-Related Warnings and Restrictions:4.3.1 User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user

guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable andcustomary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to inputand output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, orproperty damage. If there are questions concerning performance ratings and specifications, User should contact a TIfield representative prior to connecting interface electronics including input power and intended loads. Any loads appliedoutside of the specified output range may also result in unintended and/or inaccurate operation and/or possiblepermanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting anyload to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuitcomponents may have elevated case temperatures. These components include but are not limited to linear regulators,switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using theinformation in the associated documentation. When working with the EVM, please be aware that the EVM may becomevery warm.

4.3.2 EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with thedangers and application risks associated with handling electrical mechanical components, systems, and subsystems.User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronicand/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safelylimit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility andliability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors ordesignees.

4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes allresponsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility andliability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and localrequirements.

5. Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurateas possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites asaccurate, complete, reliable, current, or error-free.




6. Disclaimers:6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT

LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALLFAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUTNOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESSFOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADESECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.

6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BECONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL ORINTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THEEVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY ORIMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.

7. USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITSLICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANYHANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLYWHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGALTHEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.

8. Limitations on Damages and Liability:8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,

INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESETERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OFSUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL ORREINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OFUSE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TIMORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HASOCCURRED.

8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDEDHEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR INCONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAREVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARECLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.

9. Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not ina resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicableorder, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),excluding any postage or packaging costs.

10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating tothese terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive reliefin any United States or foreign court.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2018, Texas Instruments Incorporated

IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES

Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to,reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who aredeveloping applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you(individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms ofthis Notice.TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TIproducts, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,enhancements, improvements and other changes to its TI Resources.You understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing yourapplications and that you have full and exclusive responsibility to assure the safety of your applications and compliance of your applications(and of all TI products used in or for your applications) with all applicable regulations, laws and other applicable requirements. Yourepresent that, with respect to your applications, you have all the necessary expertise to create and implement safeguards that (1)anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures thatmight cause harm and take appropriate actions. You agree that prior to using or distributing any applications that include TI products, youwill thoroughly test such applications and the functionality of such TI products as used in such applications. TI has not conducted anytesting other than that specifically described in the published documentation for a particular TI Resource.You are authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that includethe TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TOANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTYRIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, orother intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationregarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty orendorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of thethird party, or a license from TI under the patents or other intellectual property of TI.TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES ORREPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING TI RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TOACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OFMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUALPROPERTY RIGHTS.TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY YOU AGAINST ANY CLAIM, INCLUDING BUT NOTLIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IFDESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL,COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH ORARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THEPOSSIBILITY OF SUCH DAMAGES.You agree to fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of your non-compliance with the terms and provisions of this Notice.This Notice applies to TI Resources. Additional terms apply to the use and purchase of certain types of materials, TI products and services.These include; without limitation, TI’s standard terms for semiconductor products http://www.ti.com/sc/docs/stdterms.htm), evaluationmodules, and samples (http://www.ti.com/sc/docs/sampterms.htm).

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2018, Texas Instruments Incorporated

http://www.ti.com/sc/docs/stdterms.htm

http://www.ti.com/lit/pdf/SSZZ027

http://www.ti.com/lit/pdf/SSZZ027

http://www.ti.com/sc/docs/sampterms.htm

SPIO-4 Precision Signal-Path Controller Board

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