SPECIAL TOPICS IN COMPUTER ARCHITECTURE …tera.yonsei.ac.kr/class/2013_1/lecture/Topic 7...

SPECIAL TOPICS IN COMPUTER ARCHITECTURE AND VLSI DESIGN: Overview of Data ConvertersOverview of Data Converters

Prof. Youngcheol Chae

[email protected]

Office: Room B712, Office Hours: Fri. 4~6PM

Related Course

Mixed‐Signal VLSI (EEE 6632) : Graduate CourseMixed Signal VLSI (EEE 6632) : Graduate Course

Covers Data Converters (ADCs and DACs)

Prerequisites

Microelectronics II, CMOS VLSI,

Analog VLSI or equivalent (e.g. transistor level circuit design including

opamp)opamp)

Prior exposure to Spectre or Hspice

EEE Spring 2013 Slide 2

Outline of EEE 6632

Sampling and quantization

DAC architecture

Sample and hold Sample and hold

Switched capacitor circuits

Comparators

Nyquist‐rate conversion

Oversampled conversion

Limits in accuracy

Calibration, DEM, and DWA

Test and specification


Test and specification

Motivation


All electronic systems rely on data converters

Motivation• ADC / DAC : Interface Between Analog Media and DSP System

• Higher Performance of Data Converters Required

• Trends of SoC Implementation

• Main Bottleneck of Design Time and Resources• Main Bottleneck of Design Time and Resources


System Design Trendy g

• VLSI Design & Tech Improvement

– More Signal Processing Performed in Digital Signal Domain

– Implementation Trend : A → B• Partition Criteria Determined Mainly By• Partition Criteria Determined Mainly By

– Available Design Resources of Analog Front End Such as ADC/DAC & ASP (Analog Signal Processing)

– Required Performance Specifications : (B) > (A)

– Applications & System Requirements


A/D Converter Application Spacepp p


Analog IC Marketg


Example 1p

EEE Spring 2013 Slide 9 9Source: www.apple.com

Example 1p

EEE Spring 2013 Slide 10 10

Example 2p


Example 3p


The Data Conversion Problem


Overview


Performance metric of Data Converter

• Number of Bits

• Data Conversion Rate

• Power Dissipation / Hardware Area

• Static Parameters• Static Parameters

– Gain & Offset Errors

– Non‐Linearity : DNL (Differential), INL (Integral)y ( ), ( g )

– Non‐Monotonicity, Missing Codes

• Dynamic Parameters

– SNR (Signal‐to‐Noise Ratio)

– THD (Total Harmonic Distortion)

SNDR (Signal to {Noise+Distortion} Ratio)– SNDR (Signal‐to‐{Noise+Distortion} Ratio)

– ENOB (Effective Number of Bits)

– Signal Bandwidth


g

Let’s look at Data Sheet


Input/Output Relationp / p

DAC ADC


Static Errors

Linear Errors: Offset, Gain errors Non-monotonicity, Missing CodesN Li E→ Non Linear Errors


Static Errors

Diff ti l N Li it (DNL) I t l N Li it (INL)Differential Non-Linearity (DNL) Integral Non-Linearity (INL)


Quantization Error (Noise)( )

Digital-Out

2/ 22 2

/ 2

112

q x dx

D

8

222)(

2

2

N

FS

S

V

fPSignal Power: 8

222)(

2

2

N

FS

S

V

fPSignal Power:

2328

2

)f(P)f(PSNR N2

2

2N

S

2328

2

)f(P)f(PSNR N2

2

2N

S

Error

)(P)(S S

212

)f(PN

)(P)(S S

212

)f(PN

E 76.1N02.6)dB(PP)dB(SNR

N

S 76.1N02.6)dB(PP)dB(SNR

N

S


Dynamic Errorsy

SNR

Peak SNR

0dB

Dynamic rangeAmplitude


Anti‐Alias Filteringg

Brick Wall

Attenuation

ffs 2fs ffs 2fsffs 2fs ffs 2fs

f/fs0.5 f/fs0.5

Ideal AAF Real AAF


Sampling & AAF p g

• In order to prevent aliasing, we need

fsig,max < fs/2

• The sampling rate fs=2fsig,max is called Nyquist rates sig,max

• Can tradeoff sampling speed against filter order

• In high speed converters, making fs/fsigmax > 10 is usually g p g s sigmax yimpossible, therefore we need fairly high order filters


Classes of Samplingp g


Classification of ADCs

• Flash• Two-step• Pipeline

• Flash• Two-step• Pipelinepe e• Successive approximation• Algorithmic• Dual SlopeADC

• Nyquist-ratepe e

• Successive approximation• Algorithmic• Dual SlopeADC

• Nyquist-rate

p• ...

• Sigma-delta• SC (Switched-Capacitor)

implementations• CT (Continuous-Time)

ADC

• Oversampled

p• ...

• Sigma-delta• SC (Switched-Capacitor)

implementations• CT (Continuous-Time)

ADC

• OversampledCT (Continuous Time)implementationsCT (Continuous Time)implementations


Example: Flash ADCp


Performance Limits

1.E+07

1 E+05

1.E+06

1.E 07

1 E 03

1.E+04

1.E+05

[pJ]

1.E+02

1.E+03

P/f s

nyq

ISSCC 2013VLSI 2012

1.E+00

1.E+01VLSI 2012ISSCC 1997-2012VLSI 1997-2011FOMW=10fJ/conv-stepFOMS 170dB

1.E-0110 20 30 40 50 60 70 80 90 100 110 120

SNDR @ Nyquist [dB]

FOMS=170dB


@ yq [ ]

Results from Yonsei

ISSCC’ 13

High precision SAR+ hybrid ADC 20bit resolution 6ppm INL 1uV offset and 6 3uW power

ISSCC 13


20bit resolution, 6ppm INL, 1uV offset, and 6.3uW power

Performance Limits

1 E 11

1.E+10

1.E+11ISSCC 2013VLSI 2012ISSCC 1997-2012VLSI 1997 2011

1.E+08

1.E+09

z]

VLSI 1997-2011Jitter=1psrmsJitter=0.1psrms

1.E+06

1.E+07

BW

[H

1.E+04

1.E+05

1.E+0310 20 30 40 50 60 70 80 90 100 110 120

SNDR [dB]


SNDR [dB]

Ideal DAC


The Reconstruction Problem


Zero-Order Hold Reconstruction


Dirac Pulses


Spectrump


Finite Hold Pulse


Envelope with Hold Pulse Tp=Tsp p


Examplep


Reconstruction Filter


Example: Resistor String DACp g

Resistors : Current DivisionCapacitors : Charge Division

i i i i


Transistors : Current Division

Overview


Thank you for your attention !

Prof. Youngcheol Chae

[email protected]

Office: Room B712, Office Hours: Fri. 4~6PM

41

SPECIAL TOPICS IN COMPUTER ARCHITECTURE …tera.yonsei.ac.kr/class/2013_1/lecture/Topic 7...

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