IMPLEMENTATION METHODOLOGY FOR DUAL-MODE GPS RECEIVER

GPS functionality has been synonymous with in-car navigation but has recently emerged as a must-have feature in recent cellphones such as the Apple iPhone, Blackberry Pearl and Nokia N95. These are examples of embedded positioning, capable of enabling features and functionality in a wide range of additional portable electronics such as digital cameras, watches and media players.

Air has developed a GPS receiver optimized for the requirements of embedded positioning. Capable of supporting today’s “killer” navigation application, the Air architecture is optimized for the more demanding requirements of embedded GPS and critically, for the first time, offers the capability of 24/7 continuous location awareness for mobile, battery powered, consumer devices.

This paper outlines design flow and implementation decisions utilized in the successful development of Air’s first generation airwave1 product, optimized for the first non-cellular embedded GPS application – geotagging – in the digital camera market.

Conventional wisdom dictates that complex system-level products demand both a “bleeding edge” process node (45nm, etc) and $25M+ of venture capital investment to bring initial silicon to market. The product described in this paper was implemented in 130nm CMOS technology and taken from concept to engineering sample silicon within 3 years with significantly less than $25M by the combination of an experienced team and robust methodology.

Successful realization of Air’s target power budget for airwave1 demanded a wide range of low power techniques spanning system and architecture level through RTL, gate and transistor levels.

Air partnered with Synopsys for both digital EDA tools and also physical IC design services. The resulting product enables GPS functionality for less than the standby current of a cellphone.

I. INTRODUCTION

Development of any low-power product demands optimization from system to transistor level. This paper outlines the recent experiences at Air in the development of a 130nm structured custom 41.6M transistor GPS receiver IC, with specific focus on the back-end physical silicon design. Air is a pre-revenue venture capital funded fabless semiconductor company developing a family of embedded GPS receivers optimized for 24/7 operation in mobile devices. Start-up’s must identify new, emerging markets but also deliver disruptive products before competitors. As a result, anything and everything that can be performed in parallel must be done in parallel to support this target. This demands back-end physical IC design starts before front-end activities have completed. Many of the decisions required for back-end work need to be taken (at risk) before all or even most of the

1 David Tester (david.tester@air-semi.com) is co-founder and CTO of Air 2 Jon Young, Chris Atkinson and Tom Ryan are with Synopsys

required information is either available or frozen. The resulting inherent conflict between schedule and execution steers key back-end decisions. Challenges associated with back-end implementation of complex system-level products, in the context of a large well resourced organization, are well documented. This paper outlines the start-up’s perspective on the same problem, but in the context of taking a product from concept to market in the minimum time with minimum investment and resources. The conflict between exhaustive, conclusive analysis and getting a product to market is not for everyone! Many of the critical implementation decisions can only be made based on previous experiences and instinct. Disruptive products are created through new innovative architecture decisions which exploit system optimizations not available to competitors. Products are not “made” through careful implementation of circuit level functionality but the same product opportunity can be “lost” through inappropriate implementation of that same circuit level functionality. This paper will not present any architectural details for Air’s first generation dual-mode low power GPS receiver. Instead the focus is how the unique architecture was successfully mapped to silicon with specific focus on back-end IC design.

II. PRODUCT OVERVIEW AND ARCHITECTURE

airwave1 is a single die consumer GPS solution containing optimized GPS signal processing and integrated radio with embedded processor, memory and support peripherals with additional on-chip support analog functions. Implemented in a 130nm CMOS process the IC requires a GPS antenna, SAW filter, crystal and passive support components. airwave1 provides independent GPS searching and tracking capabilities. Multiple instances of two implementations of the proprietary satellite tracking DSP are provided comprising 125K and 100K gates along with the 1.1M gate searching DSP. The embedded 32b microprocessor requires 47K gates with various support digital blocks utilizing an additional 61K gates. The integrated GPS radio and general purpose support analog are implemented as two independent analog macro’s. Standard cell logic and the device pad ring are implemented with libraries from TSMC and ARM Physical IP whilst the power management functionality uses a mix of cells from both Air and ARM Physical IP. Memory macros were licensed from both Dolphin and ARM Physical IP.

Implementation Methodology for Dual-Mode GPS Receiver

David Tester1; J Young, C Atkinson, T Ryan2

IMPLEMENTATION METHODOLOGY FOR DUAL-MODE GPS RECEIVER

III. DEVELOPMENT FLOW AND EDA TOOLS

airwave1 was constructed as a “structured custom” device within a conventional digital IC development flow that includes additional verification stages to ensure the product power budget was not violated, as discussed later in the paper. Digital functionality is implemented with a combination of VHDL and Verilog, synthesized with Design Compiler and RTL to gate level netlist (and later pre-P&R and post-P&R) verification performed with Formality. Static timing analysis was performed with PrimeTime. Device layout was with ICC. Clock gating functionality was inserted with PowerCompiler. P&R blocks used macros developed by Air and characterized by Synopsys using Liberty NCX and NanoTime prior to use in a traditional DesignCompiler based logic synthesis flow. RTL design and verification was performed by Air. Custom digital macro characterization was performed by Synopsys. Logic synthesis and formal verification was performed by Air. Digital and analog macro layout was performed by Air. Block layout and device layout was performed by Synopsys. Pre-P&R static timing was performed by Air with post-P&R static timing being performed both by Air and Synopsys using post layout parasitic extracted by Star-RCXT. The radio and support analog are developed in a traditional design flow by an internal team and delivered into the ICC flow as GDS with a CDL netlist. Prior to integration these macros were verified as DRC and LVS clean both in tools from the analog design flow and with Hercules. Final LVS and DRC verification for the complete device was performed by Synopsys with Hercules.

IV. LEAKAGE AND POWER MANAGEMENT ISSUES

Dynamic power consumption of a conventional GPS receiver is impacted by the balance between functionality implemented as hardware and that implemented as software. Static power consumption increases with logic complexity and memory requirements. Each transistor potentially contributes to the total static (or leakage) power consumption for a device. What are the options to reduce static power consumption? Leakage from each transistor is defined by the bias conditions for that component. Within a custom IC flow this offers the opportunity of local power down transistors to force bias conditions on circuits that are not required. Additionally the size of transistors can be optimized. Minor variations in transistor sizes can often provide a significant reduction in leakage. Finally, the supply voltage to individual circuits can be removed when specific functionality is not required. In the context of semi-custom IC design these techniques are not directly available. The opportunity to change transistor sizing for an existing standard cell library would violate the library license agreement and would demand characterization of the new library. Skills and design tools required to perform these activities are often not available. What options remain? Custom digital cells were developed for airwave1 but not to directly address dynamic (or static) power consumption issues.

Static power is a function of the total number of logic gates powered by the digital supply rail. If further reduction in total gate count is not an option (or is already minimized) then an additional option is to break functionality into blocks and then remove power from individual blocks – power islands. Replacement of a single digital supply voltage by multiple switched power domains can eliminate leakage current from major functional blocks when those parts of a system are idle. airwave1 comprises 44 independent digital supply domains. Reducing total gate count in a design reduces total transistor gate area but often at the cost of increased development time. For a start-up, additional optimization to refine, rather than create, functionality can conflict with schedule requirements. Embedded memory within an IC presents exactly the same static power consumption issues. Rather than optimize gate count the challenge becomes optimization of memory size. Leakage current is also temperature dependant. Obtaining an acceptable leakage current at 25°C is often not a challenge. Reaching that acceptable leakage current at 85°C is complex.

V. UNDERSTANDING DYNAMIC POWER CONSUMPTION

Battery powered products, such as GPS receivers, must optimize the power consumed during normal operation. 1. What options to minimize dynamic power are available? 2. What is the minimum data processing rate required? 3. What clock frequency does the design operate with? 4. Are all clock edges required for processing? 5. Are “spare” clock cycles available in the system timing? 6. Do all subsystems operate at the same frequency? 7. Does all logic within a block operate at the same rate? 8. Can further clock edges be removed with clock gating? 9. Can clock gating be added at the RTL level? Capturing

clock gating at this level ensures that maximum knowledge about the processing rates is captured - with potential schedule cost.

Additional optimization can be realized with tools such as Synopsys PowerCompiler to automatically identify flip-flops that could be gated either because the clock edge is not required or because the data does not change. airwave1 development utilized a mixture of both techniques. Investigation of power dissipated by typical flip-flop designs shows 10% to 20% of power consumed can relate directly to switching activity on flip-flop clock pins and internal buffers. Efficiency of clock gating depends on where the gating cells are placed within the buffer chain used to build the clock tree. Does a design really need both the Q and QN output pins for each latch or flip-flop? Provision of both pins increases both the area and power consumption of each cell. Deep cones of logic between flip-flops can risk non-minimum switching activity when driving registers change state. Such logic can significantly increase total power consumption for adders and multipliers, for example.

IMPLEMENTATION METHODOLOGY FOR DUAL-MODE GPS RECEIVER

Reduction of digital power supply voltage, either on a global or block-by-block basis can reduce the dynamic power consumed by core logic although the overall efficiency improvement depends on the voltage regulation architecture.

VI. PREDICTING DYNAMIC POWER CONSUMPTION

Predicting digital power consumption in the traditional synthesis based semi-custom flow is a challenge. Power is not modeled in the typical RTL based logic simulation flow. Switching activity, gate drive strength information and P&R parasitic capacitance is not modeled until the final stages of the typical design flow. Influence of these factors on decisions made during the architecture stage of implementation remains unknown until late (often too late) in the development process. The “power aware” design flow used is shown in Figure 1.

Figure 1 – Power Aware Design Flow

Logic complexity and switching activity is minimized through careful system design and modeling (prior to RTL coding) and efficiency of the resulting implementation is peer reviewed throughout the development process. Rather than perform circuit level simulations after the P&R process is completed to discover the power consumption the post-layout parasitic capacitance is bounded at the start of the design process with a P&R constraint, enabling circuit level simulation of key blocks long before P&R has taken place. Circuit level simulation of key digital blocks was performed pre-layout with estimated (and bounded) routing parasitics and post-layout with extracted parasitics in a Cadence analog flow with Spectre and UltraSim circuit simulators. Evaluation of the resulting silicon shows actual power consumption for the most power critical digital blocks on airwave1 are within 10% of simulations.

VII. LOGIC SYNTHESIS, TIMING CONSTRAINTS AND LAYOUT

airwave1 includes multiple independent signal processing blocks for satellite detection and tracking operating at various clock rates of 96MHz, 64MHz, 32MHz and 16MHz. The maximum clock rate blocks contain logic with hundreds of paths containing over 92 levels of logic between flip-flops.

Analysis of post-layout performance suggests that high drive strength logic gates don’t offer an optimum tradeoff for power when routing is limited and parasitic capacitance minimized. Circuit level simulation for key logic paths within airwave1 confirms this gate drive strength vs routing parasitic tradeoff. Synthesis strategies for the various DSP blocks in airwave1 are very different. Within the high data processing rate satellite searching DSP timing closure is complex, demanding gate delay after post-layout parasitic capacitance less than 200ps. Only X1, X2 and X4 drive strength cells were permitted both in initial logic synthesis and in post-placement optimization. In contrast, the low data processing rate satellite tracking DSP requires a clear minimum drive strength and minimum logic area rather than a timing driven synthesis strategy. Circuit level simulations of the gate level netlist after logic synthesis but prior to layout was essential to confirm power consumption for each functional block remained within the overall power budget for the complete system.

VIII. CLOCK TREE ESTIMATION AND IMPLEMENTATION

Clock trees within design directly impact power consumption. Typical clock trees constructed with automatic CTS tools will provide functional, but over designed, results. Target requirements for clock skew and transition times affect power consumption of the clock tree built by CTS. Whilst P&R tools will typically remove all logic within a pre-layout clock tree realistic targets for clock skew and transition times are essential in initial synthesis to create logic suitable for minimal optimization after construction of the clock trees. Whilst the device was constructed with a hierarchical block-by-block approach the total number of clock domains within the design exceeds 44 major clocks and 400 in total. Each domain contains multiple levels of clock gating, both manually inserted in RTL and inserted automatically with PowerCompiler. Multiple iterations of P&R are mandatory to tune the synthesis model of clock uncertainty and transitions if clock trees that don’t contain strings of X20 buffers are to be avoided. Estimation of clock tree power consumption remains a manual activity. Circuit level simulation of clock tree performance was essential to confirm block power budgets post-layout were met.

IX. ROUTING CONGESTION AND POST-LAYOUT CAPACITANCE

airwave1 is implemented in CMOS 130nm 6LM UTM process. Impact on switching performance and power consumption of post-layout parasitic capacitance can be significant and reliable prediction of digital power consumption demands control of post-layout routing capacitance. More metal layers generally give better utilization after P&R but what are the implications of “ultra thick” top layer metal? Minimum metal pitch and spacing rules for UTM metal have the effect of making upper metal ineffective for detailed signal routing and suitable only for power supply distribution. It is

IMPLEMENTATION METHODOLOGY FOR DUAL-MODE GPS RECEIVER

true that IR drop in DVDD and DVSS lines is significantly improved but the standard cell utilization degrades as a result.

X. POWER DOMAINS & POWER MANAGEMENT KIT

As previously described in section IV airwave1 contains 44 independent digital power domains for fine control of leakage current during operation of the GPS receiver. This is illustrated in Figure 2 below.

Figure 2 – Voltage Domains in airwave1

All communication between blocks utilizes conventional voltage clamp cells from a vendor power management kit. All cells were manually inserted into the design at RTL level with corresponding synthesis don’t touch constraints in the flow. Power domain control cells were automatically inserted by ICC using its built in capabilities from manually generated TCL commands with gate level netlist verification of the resulting design. As part of this process the number and size of the header cells needed by each voltage region had to be calculated and the impact on the chip die and floorplan understood. The library cell used to create the switched voltage domains was internally developed at Air and exported into ICC. There was no requirement for state retention flip-flops due to system level optimizations. Continuous power is required for on-chip RAM with impact on memory macro leakage current.3

XI. CUSTOM LOGIC CELLS OPTIMIZED FOR POWER

The high performance satellite searching DSP contains 105K flip-flops as part of the local datapath to provide a total of 264 discrete memory blocks. The ability of P&R tools to constrain the placement of 105,000 elements and build a structured array presented a risk for the physical design phase of airwave1. Development of a custom macrocell not only eliminates the cell placement risk but also offers an opportunity to optimize the

3 http://www.air-semi.com/media/pdf/AIR__Dolphin_Integration_FINAL.pdf

performance of these local memory functions compared to a traditional array built with multiple flip-flops with synthesis. Knowledge of relative DFF placement, driver and load allows the performance of each flip-flop to be optimized with power for the specific use-case as the target constraint. In these rare circumstances gates with sub-optimal propagation delays and transition times can offer optimized power consumption. The resulting macrocell offered 40% power improvement with an additional 25% area optimization compared to synthesis. Example switching performance is shown in Figure 3. Synopsys provided cell characterization for the macro using Liberty NCX for the cell characterization and then NanoTime to generate the performance data for the cell array which was subsequently included in the standard logic synthesis, static timing and P&R flow.

Figure 3 – Switching Performance of Power Optimized Flip-Flop

XII. IMPACT OF POST-PLACEMENT LOGIC OPTIMIZATION

During the digital layout process there are various points where ICC can re-optimize logic to fix timing and design rule violations. Each optimization step offers the opportunity to transition a block from meeting to violating its power budget! Typically logic synthesis for low power exploits carefully coded RTL with specific synthesis constraints to ensure exactly the desired logic is obtained. Constraints applied to ICC for optimization steps must match those used for initial synthesis.

XIII. PHYSICAL DESIGN ISSUES (IN A START-UP)

For any pre-revenue company, time-to-market is critical. In the race to bring a new product to market there is an inherent conflict between activities essential to create the optimum device floorplan and a time optimized development schedule. As start-up developing a complex system-level product against an aggressive time to market goal, this is where the fun begins and conflict between front-end and back-end design appears. No top level netlist? No problem! Critical decisions on device floorplan, pad-ring, global signal routing and package need to be made before the major functional block design is complete,

IMPLEMENTATION METHODOLOGY FOR DUAL-MODE GPS RECEIVER

before block level layout is complete and long before the final (or even the preliminary) top level netlist is available.

Figure 4 – airwave1 Floorplan

Can the analog macros be delivered days before tape-out?... Hierarchical layout of a complex IC trades die area for risk. Whilst flat layout of a complex IC allows EDA tools to make unexpected placement and routing optimizations, predictable execution for the back-end phase of development is only possible with hierarchical floorplan and implementation. Although without a fully automated method for implementing the power down regions the time to re-spin a floorplan (including header cells, power routing and voltage aware well TIE and filler cell placement) can be longer than expected, in this project extensive use of TCL scripting was used to minimize the impact of changes and automate the process. Throughout the digital design flow all block interfaces were maintained with minimal connectivity issues for optimized chip-level routing and timing, knowing that a block-by-block hierarchical approach to device layout would be essential and would enable physical IC design to start (at the block level) before the functional RTL development phase had completed. Global routing for a complex system-level product in a six layer metal process where the top two layers of metal are more suited to power supply routing than signal routing is a major issue for a hierarchical based layout flow and demands careful floorplanning in advance. The “signal” processed by a GPS radio is, quite literally, noise. Digital circuits are very good at generating not just wideband noise but also noise at very specific design related frequencies. Careful floorplanning is required to ensure all blocks capable of generating noise that would degrade the radio performance are suitably located on the die. Circuits capable of generating noise and circuits sensitive to noise must be shielded with guard rings. Coupling capacitance between global route signals must be minimized.

XIV. DEVICE PACKAGING OPTIONS AND PAD RING DESIGN

Whilst the internal evaluation package requires a 304 ball BGA for the 244 pad airwave1 engineering sample silicon, the device is offered to customers in a 68 lead QFN package. Careful design of the pad ring was essential to ensure the 176 evaluation only I/O’s could be appropriately bonded in the customer QFN bond option. An example module containing the engineering sample silicon with full GPS reference design is shown in Figure 5. Figure 6 is the first photo geotagged with airwave1 silicon.

XV. DESIGN TOOL FLOW

Digital design followed an conventional logic synthesis based flow using the Synopsys tools DesignCompiler, PrimeTime, PowerCompiler, Formality, ICC and Hercules. Analog design followed a conventional Cadence flow using Composer, Artist, Spectre, SpectreRF, Virtuoso and Assura. Licensed IP from all vendors and macros created by Air were all subject to QA verification for LVS and DRC with Hercules. Final full-chip LVS and DRC was performed in Hercules prior to release by Air of final GDSII to the foundry for manufacture.

Figure 5 – GPS module with engineering sample airwave1 silicon

Figure 6 – The first photograph geotagged with airwave1 silicon

XVI. THE FUTURE

The silicon described in this paper is the engineering sample release of the airwave1 product. Having demonstrated silicon that provided right-first-functionality the development team is active on development of the production version of airwave1.

IMPLEMENTATION METHODOLOGY FOR DUAL-MODE GPS RECEIVER

XVII. CONCLUSION

Air successfully completed development of the 130nm CMOS single-die GPS receiver on-time and on-budget in conjunction with Synopsys Professional Services physical design group. The resulting right-first-time complex mixed signal silicon has been sampled to lead digital camera customers in Japan.4

ACKNOWLEDGMENT

Development of any complex semiconductor product is a group activity involving (and often demanding) system, silicon and software optimizations and tradeoffs. The receiver described in this paper forms part of a system-level GPS semiconductor product developed by the R&D development team at Air Semiconductor. The authors wrote this paper but the product results from the combined contributions of all team members.

David Tester is the CTO and leads the architecture and product development activities for embedded GPS products at Air, having raised series-A venture capital funding and co-founded the company in 2006.

Prior to co-founding Air, he spent 15 years in various semiconductor development and management positions based both in the UK and US with Dialog Semiconductor, LSI Logic, Conexant, Symbionics and GEC Research.

He was listed in GPS World’s “50 Leaders to Watch” during 2008. Air was awarded the Red Herring Europe 100 along with both the Electra and IET start-up of the year awards in 2008.

His high volume, standard product, consumer IC background spans both analog and digital silicon development – ranging from system level to transistor level design. He has participated in the development of over 20 high volume consumer semiconductor products for the navigation, wireless voice, wireless data, digital TV and PC graphics markets.

Mr Tester is a senior member of IEEE, ION and IET; He is registered as a Chartered Engineer with both ECUK and FEANI. He holds nine US patents.

Tom Ryan (left), Jon Young (centre) and Chris Atkinson (right) work for Synopsys Global Technical Support in Reading, UK.

Global Technical Support enables customer adoption and deployment of Synopsys’ technology and flows to improve their design productivity and tape out predictability.

4 http://www.air-semi.com/media/pdf/AIR_firstcustomersrelease_FINAL.pdf