SnUG 1996 - NLD Optimization for ISM - slides
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Transcript of SnUG 1996 - NLD Optimization for ISM - slides
VLSI Technology, Inc.
Non-Linear Delay Table Optimization
Timothy J. Ehrler1 of 16
Input Slope Models & Synopsys NLD Table Analysis
• Analyze previous Synopsys non-linear delay model tables
- output load & input ramp range coverage
- table value interpolation accuracy
• Investigate alternate table configurations
- smaller, more efficient tables
- more accurate sample points
- critical sample point distribution
VLSI Technology, Inc.
Non-Linear Delay Table Optimization
Timothy J. Ehrler2 of 16
Previous Synopsys Non-Linear Delay Model Tables
• single stage non-disable timing relationship analyzed
• 25 x 25 array (output load by input ramp)
• single template to cover complete library (~300 SS rels)
VLSI Technology, Inc.
Non-Linear Delay Table Optimization
Timothy J. Ehrler3 of 16
Fixed Indexed Non-Linear Delay Table
00.5
11.5
22.5
33.5
4 1
2
3
4
5
6
7
8
9
0
5
10
15
20
25
input ramp (ns)
output load (pf)
Critical Input Ramp
Delay Table
delay (ns)
VLSI Technology, Inc.
Non-Linear Delay Table Optimization
Timothy J. Ehrler4 of 16
Sufficient Rel Table Coverage
0.51
1.52
2.53
3.54
4.5 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
0.5
1
1.5
2
2.5
input ramp (ns)
output load (pf)
delay (ns)
Critical Input Ramp
Base Table
VLSI Technology, Inc.
Non-Linear Delay Table Optimization
Timothy J. Ehrler5 of 16
Base Coverage vs. Fixed Interpolated Values
0.5
1
1.5
2
2.5 0
0.05
0.1
0.15
0
0.5
1
1.5
2
input ramp (ns)
Base Table
Fixed Table Interpolation
Critical Input Ramp
output load (pf)
0.4
0.35
0.3
0.25
0.2
VLSI Technology, Inc.
Non-Linear Delay Table Optimization
Timothy J. Ehrler6 of 16
Base Coverage vs. Fixed Interpolated Errors
0.5
1
1.5
2
2.5 0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
-8
-7
-6
-5
-4
-3
-2
-1
0
input ramp (ns)
output load (pf)
% error
Fixed Table Interpolation Error at CIRFixed Table Interpolation Error
- 7.3 %
VLSI Technology, Inc.
Non-Linear Delay Table Optimization
Timothy J. Ehrler7 of 16
Reduced Sufficient Rel Table Coverage
Critical Input Ramp
0.51
1.52
2.53
3.54
4.5 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
0.5
1
1.5
2
2.5
input ramp (ns)
output load (pf)
delay (ns)
Sample Table
VLSI Technology, Inc.
Non-Linear Delay Table Optimization
Timothy J. Ehrler8 of 16
Base Coverage vs. Reduced Sufficient Interpolated Values
Base Table
0.51
1.52
2.53
3.54
4.5 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
0.5
1
1.5
2
2.5
input ramp (ns)
output load (pf)
delay (ns)
Reduced Sufficient Table Interpolation
Critical Input Ramp
VLSI Technology, Inc.
Non-Linear Delay Table Optimization
Timothy J. Ehrler9 of 16
Base Coverage vs. Reduced Sufficient Interpolated Errors
0.5
1
1.5 0
0.05
0.1
0.15
0.2-6
-5
-4
-3
-2
-1
0
1
input ramp (ns)
output load (pf)
% error
Reduced Sufficient Table Interpolation Error at CIR
Reduced Sufficient Table Interpolation Error
- 5.0 %
VLSI Technology, Inc.
Non-Linear Delay Table Optimization
Timothy J. Ehrler10 of 16
Reduced Sufficient vs. Fixed Size Error
0.51
1.52
2.53
3.54
4.5 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
-8
-7
-6
-5
-4
-3
-2
-1
0
1
input ramp (ns)
output load (pf)
% error
Reduced Sufficient Table Interpolation Error
Reduced Sufficient Table Interpolation Error at CIR
Fixed Table Interpolation Error
Fixed Table Interpolation Error at CIR
VLSI Technology, Inc.
Non-Linear Delay Table Optimization
Timothy J. Ehrler11 of 16
Non-Linearly Indexed Table
0.51
1.52
2.53
3.54
4.55 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0
0.5
1
1.5
2
2.5
3
input ramp (ns)
output load (pf)
delay (ns)
Critical Input Ramp
Non-linear Sample Table
VLSI Technology, Inc.
Non-Linear Delay Table Optimization
Timothy J. Ehrler12 of 16
Non-Linearly Indexed Interpolated Values
0.51
1.52
2.53
3.54
4.5 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
0.5
1
1.5
2
2.5
input ramp (ns)
output load (pf)
delay (ns)
Non-linear Base Table
Non-linear Sample Table Interpolation
Critical Input Ramp
VLSI Technology, Inc.
Non-Linear Delay Table Optimization
Timothy J. Ehrler13 of 16
Non-Linearly Indexed Interpolated Errors
0.50.55
0.60.65
0.70.75
0.80.85
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
input ramp (ns)
output load (pf)
% error
Non-linear Table Interpolation Error at CIRNon-linear Table Interpolation Error
- 3.0 %
VLSI Technology, Inc.
Non-Linear Delay Table Optimization
Timothy J. Ehrler14 of 16
Optimized Non-Linearly Indexed vs. Fixed Linearly Indexed Error
Fixed Linearly Indexed Interpolation Error at CIR
Fixed Linearly Indexed Interpolation Error
Optimized Non-Linearly Indexed Interpolation Error at CIR
Optimized Non-Linearly Indexed Interpolation Error
0.51
1.52
2.53
3.54
4.5
0.1
0.2
0.3
0.4
0.5
0.6
0.7
-8
-7
-6
-5
-4
-3
-2
-1
0
1
input ramp (ns)output load (pf)
% error
VLSI Technology, Inc.
Non-Linear Delay Table Optimization
Timothy J. Ehrler15 of 16
Applied Results
• library containing 538 single-stage non-disable timing rels
• 5.0 % interpolation error within a 64x64 overlaid matrix
Property Previous Current % of Previous
minimum size - 3x3 -
maximum size - 18x18 -
average size 25x25 7.6x7.6 30 %
average entries/table 625 57.4 9.2 %
total entries 336,250 30,906 9.2 %
VLSI Technology, Inc.
Non-Linear Delay Table Optimization
Timothy J. Ehrler16 of 16
Conclusions
• smaller tables can cover full output load and critical input ramp ranges
• smaller tables reduce resource usage considerably
• custom coverage ensures more accurate interpolation
• non-linear indices assure more accurate critical region coverage