Single Cycle vs. Multiple Cycle
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Transcript of Single Cycle vs. Multiple Cycle
CSCI-365Computer Organization
Lecture
Note: Some slides and/or pictures in the following are adapted from: Computer Organization and Design, Patterson & Hennessy, ©2005
Single Cycle vs. Multiple Cycle
Multiple Cycle Implementation:
Clk
Cycle 1
IF ID EX MEM WB
Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9Cycle 10
IF ID EX MEM
lw sw
IF
R-type
Clk
Single Cycle Implementation:
lw sw Waste
Cycle 1 Cycle 2
General Definitions
• Latency: time to completely execute a certain
task
– E.g., time to read a sector from disk is disk access
time or disk latency
• Throughput: amount of work that can be done
over a period of time
A Pipelined MIPS Processor
• Start the next instruction before the current one has
completed
– improves throughput
– instruction latency is not reduced
– clock cycle (pipeline stage time) limited by slowest stage
– for some instructions, some stages are wasted cycles
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
IF ID EX MEM WBlw
Cycle 7Cycle 6 Cycle 8
sw IF ID EX MEM WB
R-type IF ID EX MEM WB
Single Cycle vs. Multiple Cycle vs. Pipelined
Multiple Cycle Implementation:
Clk
Cycle 1
IF ID EX MEM WB
Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9Cycle 10
IF ID EX MEM
lw sw
IF
R-type
Clk
Single Cycle Implementation:
lw sw Waste
Cycle 1 Cycle 2
lw IF ID EX MEM WB
Pipeline Implementation:
IF ID EX MEM WBsw
IF ID EX MEM WBR-type
Theoretical Performance
• An ideal pipeline divides a task into k independent sequential
subtasks
– Each subtask requires 1 time unit to complete
– The task itself requires k time units to complete
• For n iterations of task, the execution times:
– With no pipelining: nk time units
– With pipelining: k + (n-1) time units
• Speedup of a k-stage pipeline is
– S = nk / [k+(n-1)] ==> k (for large n)
Simplified MIPS Pipelined Datapath
Can you foresee any problems with these right-to-left flows?
Why are we duplicating some functional units?
Pipeline registers
• Need registers between stages
– To hold information produced in previous cycle
IF
ID
EX for Load
MEM for Load
WB for Load
Wrongregisternumber
There is a BUG here
Corrected Datapath for Load