SERVICE · PDF file · 2012-10-01SERVICE MANUAL MODEL NO. PT4206 Please read this...
Transcript of SERVICE · PDF file · 2012-10-01SERVICE MANUAL MODEL NO. PT4206 Please read this...
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CONTENTS Part:PP06 Chassis Features and Circuit………
Part:Introduction on Circuit Functions of PT4206 ……
Part:Analysis on Signal Process of PT4206………
Part:Typical Defectives and Repair of PT4206…………
Annex: 1Main Assembly Drawing& of PT4206
2Wire Connecting Drawing of PT4206
Part:PP06 Chassis Features and CBU Contents
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1.1PP06 Chassis Technical Specifications 1.1.1 PT4206 Panel Datas
PT4206 is the most typical model using PP06 chassis; therefore we take PT4206 as an example.
PDP Panel Resolution 852×3(RGB)×480 Colors 16,777,216 Dot Pitch 1.095mm(H)×1.110mm(V) Brightness High brightness Contrast High contrast Lifespan of Panel 20000 Hours Viewing Angle U/D160 / L/R160 Response Time 933mmH×533mm(V)
Remarks: Brightness and contrast may vary because of different panels being used. PT4206 mainly uses SAMSUNG SDI panel model S42SD-YD04 or S42SD-YD05 1.1.2 Specification Sheet
1.2Main Features
1.2.1 Terminals
RF Input 1Rear S Terminal Input 1Rear
Recommended Input Format 640Ў Б480/60Hz 800Ў Б600/60Hz
Unsupportable Input Format Indication Yes
Color Temp. Adjust. Yes Quick Plug-In & Use Yes
PC
Picture Location Adjust. Yes
HD Signal Ј ЁYPbPrЈ ©
Compatible with 480PЎў576PЎў720P Ўў1080i
HD SignalЈ ЁDVIЈ ©
Compatible with 480PЎ ў576PЎ ў720P Ўў1080i and HDTV
Picture System PAL/NTSC/SECAM Sound System D/KЎ ўIЎ ўB/GЎ ўM Digital Comb Filter Yes 3D Comb FilterЈ ЁNTSCЈ ©
Yes
Video Ј ЁIncluding S-VideoЈ ©
Movement Compensation Function Yes Output Voltage 2Ў Б5W Audio Effect WOW NICAM/IGR Yes Video/YpbPr Audio Input Audio L/R
Audio
PC/DVI Audio Input Audio L/R Input Voltage 220V~, 50Hz
Rating Consumption
Ё Q400W
Standby Consumption
Ё Q3W
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A/V Input RCA1Rear YCbCr RCA1Rear DTV YPbPr RCA1Rear VGA/SVGA Input Hi-Density D-SUB 15 pin connector1Rear DVI Input 1 Rear A/V Output RCA Rear
Remarks: PT4206 is equipped with a service terminal, which service people can connect with PC RS232 terminal to upgrade the software. 1.2.2 Working Condition Requirement:
Temperature 040 Humidity 2070 Working Condition Requirement Altitude 02000m
1.2.3 Others
Tuning System FS Tuning236 Programs
NICAM Demodulation Yes Audio Effect Process AV stereoSRS WOW5 Bands Equalizer Picture Freeze TV/AV/S-VIDEO/YcbCr Only On Screen Display Chinese/English, Menu Location movable by user. Blue Background without Signal Yes Power Saving When TV is connected with PC input, while there is no
signal from PC, after 60 seconds, TV will be automatically off and enter into Power Saving Mode. Press any key on TV or R/C, or there is signal from PC again, TV will be switched on automatically.
Pixel Movement When this function is on, pictures will move on regularly to protect the screen.
White Screen Display When this function is on, the screen will be completely white to clear up slight shadowsplease see the instruction manual for more details
Home/Commercial Mode Optional Users can choose between 15 minutes auto-off without signal or 3 hours auto-off without operation please see the instruction manual for more details
1.3CBU Content
1.3.1 PDP Inside Drawing:
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rial No. Name Front Cabinet
Filter Glass Shelve Bar PDP Panel Module Down Cover Module etc. Back Cabinet
Remarks: This drawing is for references only, please see the main assembly diagram and wire-connecting diagram for details. 1.3.2 Circuit Content
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The main content of PP06 circuit include: Power Regulating Circuit, RF Circuit, VGA, Analog Video, Digital Video Signal Processing Circuit, System Control Circuit, Button Control Circuit. Reference drawing as below:
Part:Introduction on Circuit Functions of PT4206 2.1 Changhong PDP TV PT4206 main IC functions
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NO. NAME TYPE Function 1 N901 TDQ-6F7-FM2W Unify tuner 2 N601 MSP3410G-C12-100 Sound disposal 3 U705 TA2024 sound amplifier 4 U701 uPD64083GF-3BA NTSC 3D comb filter 5 N902 TEA6425D AV video switch 6 U1 VPC3230D-QA-B3 Digital video disposal 7 U6 MST9885 A/D converter 8 U11 SiI161BCT100 DVI signal disposal 9 U16 PW113-20Q Format transform and MCU
10 U17 AM29LV800BT-90 FLASH ROM 11 U22 DS90C383AMTD Difference transmit 12 U20 ST232CD RS-232 signal disposal 13 U7 24LC21A/SN E²PROMdisplay parameter information 14 U9/U13 SN74LVC126AD Suffer amplifier 15 U71 74LV32D Sync. face lifting enlarge 16 U8 24LC21A/SN E²PROMDVI parameter information 17 U19 24LC32A/SN E²PROMuser control information 18 U4 IS42S16400(A)-7T SDRAM 19 U5 PI5V330(Q) RGB/YpbPr switch 20 U3 PW1235 IP transform and picture improve
2.2Changhong PDP TV PT4206 main IC functions introduction 2.2.1 A/D converter MST9885 General The MST9885 is a fully integrated analog interface for digitizing high-resolution RGB graphics signals from PCs and workstations. With a sampling rate capability of up to 140 MHz, it can accurately support display resolutions up to 1280x1024 (SXGA) at 75 Hz. The clamped input circuits provide sufficient bandwidth to accurately digitize each pixel. The MST9885B provides a high performance highly integrated solution to support the digitization process, including the ADCs, a voltage reference, a PLL to generate the pixel sampling clock from HSYNC, clamping circuits, and programmable offset and gain circuits to provide brightness and contrast controls. When the COAST signal is asserted, the PLL will maintain its output frequency when HSYNC pulses are absent, such as during the VSYNC period in some systems. A 32-step programmable phase adjustment control (0-360 deg) is provided for the pixel sampling clock to adjust for the difference between the HSYNC edge and RGB pixel edge timing. The MST9885B can send output data through one 24-bit port at the pixel clock rate. The MST9885B can also support R, G, B to Y, U, V conversion. The MST9885B has internal programmable pattern generator for testing. The MST9885B can accept either standard TTL, CMOS levels or sawtooth vertical deflection signals for VSYNC input. MST9885 Pin Function Descriptions
Pin(s) name Function 7077 RED0RED7 Red output data
29 GREEN0 Green output data
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GREEN7 1219 BLUE0BLUE7 Blue output data
67 DATACK Output data clock 66 HSOUT HSYNC output 65 SOGOUT Sync-on- Green Slicer output 64 VSOUT VSYNC output 37 MIDSCV Internal mid-scale voltage bypass 58 REFBYP Internal reference bypass 31 VSYNC Vertical SYNC input 30 HSYNC Horizontal SYNC input 43 BAIN Blue analog input 49 SOGIN Sync-on- Green analog input 48 GAIN Green analog input 54 RAIN Red analog input 29 COAST Hold PLL frequency and do not track HSYNC 38 CLAMP External clamp input(we connect it to ground 55 A0 Serial interface address pin 56 SCL I2C busclock 57 SDA I2C busdata 33 FILT PLL connect to external filter
262739424546515259
62
AVDD Analog power
112223697879
V33 Digital output power
3435 PVDD PLL power 1102021242528323640414447505360616368
80
GND ground
MST9885 Block Diagram
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2.2.2VPC3230 General VPC3230 Pin Function Descriptions Pin No. Pin Name Short Description
13 R1G1B1IN RGB Analog Component Input 1 46 R2G2B2IN RGB Analog Component Input 2
76430111225356577465168
80
GND GND
8 NC NC 9 VSUPCAP Supply Voltage, Digital Decoupling Circuitry
1029364552
V33 Supply Voltage, Digital Circuitry
596976 AVCC Analog Voltage 13 SCL I2C Bus Clock 14 SDA I2C Bus Data 15 RESQ Reset Input 16 TEST Test Pin 17 VGAV VGAV Input 18 YCOEQ Y/C Output Enable Input
1923 FFIE NC 24 CLK20 Main Clock Output 27 LLC2 Clock Output 28 LLC1 NC
3134 3740
Y0Y7 YUV signal output (Digital ITU-R656 format)
4144 4750
C0C7 Digital chromatic signal output
53 INTLC Interlace scan control output (0-odd,1-even) 54 AVO Active Video Output 55 FSY/HC NC 56 MSY/HS Horizontal Sync Pulse output 57 VS Vertical Sync Pulse 58 FPDAT NC 60 CLK5 5 MHz Clock Output 61 NC NC 62 XTAL1 20.25M Analog Crystal Input 63 XTAL2 20.25M Analog Crystal Output 66 VRT Reference Voltage Top, Analog 67 I2CSEL I2C Bus Address Select 70 VOUT Analog Video Output 71 CIN Chroma / Analog Video 5 Input 72 VIN1 Video 1 Analog Input 73 VIN2 Video 2 Analog Input 74 VIN3 Video 3 Analog Input 78 VREF Reference Voltage Top 79 FB1IN Fast Blank Input
VPC3230 Block Diagram
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2.2.3PW113 General
The PW113 integrates an industry-leading scaler, an advanced OSD engine, a flexible input port system, system memory, and a powerful 80186-based horizontal and vertical image scaler swith intelligent Auto Image Optimization circuitryThe Image Processor supports NTSC or PAL video data with a 4:3 aspect ratio and 16:9 aspect ratio sources, such as DVD or HDTV. Video Input formats can be in either YUV4:4:4 (24 bit) or YUV4:2:2 (16 bit) input modesThe PW113 uses an integrated PLL to synchronize the display interface timing to the input timingAn integrated OSD controller supports sophisticated bit-mapped based OSDs The OSD controller supports transparent, translucent, and fade-in/ fade-out functions.
Pin Function Descriptions Pin(s) name Function
Video Port Pin Descriptions 71 VCLK VPort Pixel Clock input 74 VVS VPort Vertical Sync input 75 VHS VPort Horizontal Sync input 69 VFIELD VGPort Field Input 70 VPEN VPort Pixel Enable
4756 YUV0YUV7 VGPort ITUR656 Pixel Data.I/O port We use 47 MUTE mute control 48 PW1230E PW1235output enable49 VGASEL VGA/YpbPr select50 S1 sound system control51 DVIPD DVI interface standby54 STANDBY power standby control56 RST1 peripheral IC reset
Graphics Port Pin Descriptions 31 GCLK GPort Pixel Clock input 32 GVS GPort Vertical Sync input 33 GHSSOG GPort Horizontal Sync/GPort Sync- on-Green input 34 GPEN GPort Pixel Enable input
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35 GFBK GPort PLL Feedback / Line Advance Input 2027 GRE0GRE7 GPort Red Pixel Data input
10151819 GGE0 GGE7
GPort Green Pixel Data input
29 GBE0GBE7 GPort Blue Pixel Data input Display/Graphics Port Pin Descriptions
129136 DGR0DGR7 DGPort Red Pixel Data(odd outputs) 119122125128
DGG0DGG7 DGPort Green Pixel Data(odd outputs)
111118 DGB0DGB7 DGPort Blue Pixel Data(odd outputs) Display Port Pin Descriptions
106 DCLK DPort Pixel Clock output 108 DVS DPort Vertical Sync output 109 DHS DPort Horizontal Sync output 110 DEN DPort Pixel Enable output
96103 DR0DR7 DPort Red Pixel Data(even outputs) 8895 DR0DR7 DPort Green Pixel Data(even outputs) 7683 DB0DB7 DPort Blue Pixel Data(even outputs)
Microprocessor Interface Pin Descriptions 194 WR Write Enable low indicates a write to external RAM or other
devices 195 RD Read Enable low indicates a read to external RAM or other
devices 196 ROMOE ROM Output Enable low output indi cates a read from
external ROM. 197 ROMWE ROM Write Enable low indicates a write to external ROM. 198 CS0 Chip select signal 199 CS1 Chip select signal 193 NMI Non-maskable Interrupt
164173184187
192
A1A19 Microprocessor address bus output bits
148163 D0D15 Microprocessor 16-bit bidirectional data bus Peripheral Interface Pin Descriptions
207 PORTA0 DISPEN signal output(PDP display control) 206 PORTA1 READY signal inputPDP display ready 205 PORTA2 SDA 204 PORTA3 SCL 203 PORTA4 IR receive signal input 201 PORTA6 DVI digital interface select control 203 PORTA4 IR receive signal input
57586064
PORTB0 PORTB7
Key control input
39 PORTC0 MA-EN enable control 40 PORTC1 480ISEL 480I anti-copy control 41 PORTC2 RST-1235 PW1235 reset 42 PORTC3 DIGSEL DVI digital interface select 43 PORTC4 LVDSON LVDS enable control 44 PORTC5 S0 sound system control
4546 PORTC6 PORTC7
LED control
67 RXD Serial Receive Data 68 TXD Serial Transmit Data
Miscellaneous Pin Descriptions 142 TEST Test mode enable 139 RESET Bidirectional reset pin
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169 XI Crystal input 170 XO Crystal output
Power and Ground Pin Descriptions 16376584137185 VDD1 1.8V digital core power. 17386685138186 VSS Digital core ground 29527286104123140171208
VDDQ3 3.3V digital I/O power.
130537387105124141172
VSSQ Digital I/O ground.
165 VDDPA2 1.8V analog clock generator power. 166 VSSPA2 Clock generator analog ground. 167 VDDPA1 1.8V analog clock generator power. 168 VSSPA1 Clock generator analog ground.
PW113 Block Diagram
2.2.4PW1235 General PW1235 supports standard digital video signal incorporates deinterlacing
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scaling .the PW1235 is able to effectively deinterlace video input by creating motion vectors that follow frame-to-frame movement, and provide clear, progressive output in both analog and digital formats. The PW1235 integrates input interfaceMEMORY control circuitpicture improveoutput interface circuitI2C bus interface and so onall the function are controlled by I2C bus Pin Function Descriptions
Pin(s) Name Function Video Port Pin Descriptions
27 PVVS Primary Video (PV) Port vertical sync input. 28 PVHS Port horizontal sync input 25 PVCLK Port pixel clock input 26 CREF Video input clock reference 12 SVVS Port (ITU-R BT656 format) vertical sync input 11 SVHS Port (ITU-R BT656 format) horizontal sync input 13 SVCLK Port (ITU-R BT656 format) pixel clock input
30333538 VR0VR7 Video port red data input 15182023 VG0VG7 Video port green data input
1469 VB0VB7 Video port blue data input Digital/Graphics (DG) Port Pins
68 DGCLK Digital/Graphics (DG) port pixel clock 67 DGVS Digital/Graphics (DG) port vertical sync. 66 DGHS Digital/Graphics (DG) port horizontal sync
9192949597100
DGR0 DGR7
Digital/Graphics (DG) port red data
81848689 DGG0 DGG7
Digital/Graphics (DG) port green data.
70 73,75 76 7879
DGB0 DGB7
Digital/Graphics (DG) port blue data
Analog Display Port Pin Descriptions 156 ADR Analog display port red (V/Pr) data 153 ADG Analog display port green (Y/Y) data 150 ADB Analog display port blue (U/Pb) data 161 VREFIN Reference voltage input. 162 VREFOUT Reference voltage output. 159 RSET Full-Scale adjust resistor 160 COMP Compensation pin
Digital Display Output Port Pin Descriptions 102 DCLK Digital display output port pixel clock 103 DVS Digital display output port vertical sync 104 DHS Digital display output port horizontal sync. 108 DENR Display pixel enable red/Vertical blanking period
(VBLANK) 106 DENG Display pixel enable green 107 DENB Display pixel enable blue/Horizontal blanking period
(HBLANK) 145 DEN Digital display output port output enable
132 133 135 136 138 139 141142
DR0DR7 Digital display output port red data
121 122 124 125 127130
DG0DG7 Digital display output port green data.
110 111 113 114
DB0DB7 Digital display output port blue data.
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116119 Memory Pin Descriptions
229 MCLK SDRAM clock 223 MCLKFB SDRAM clock feedback 225 MRAS SDRAM row address strobe 226 MCAS SDRAM column address strobe 227 MWE SDRAM write enable
213210207204203206209211214217215220221218
MA0 MA13
SDRAM address bus
255252248245242239236232231234238241244247250254
MD0 MD15
SDRAM data bus
Host Interface Pin Descriptions 47 2WDAT SDA 45 2WCLK SCL 43 2WA1 Programmable two-wire serial bus address bit 1 44 2WA2 Programmable two-wire serial bus address bit 2
178179181186 MCUD0 MCUD7
MCU data bus
168170172174176177
PORTB1 MCU address bus
190 MCUCS Chip select 191 MCUWR MCUR/W signal 192 MCUCMD MCU command signal 188 MCURDY MCU Ready signal
Miscellaneous Pin Descriptions 56 TEST Test mode
144 TESTCLK Used for testing, can be used to supply display clock 55 RESETn Hardware asynchronous reset. 40 XTALI Crystal oscillator input 41 XTALO Crystal oscillator output
146 CGMS CGMS Enable 201 MVE Macrovision write protected enable
62, 63, 194,195 NC System Power Pin Descriptions 5, 34, 93, 123,140,
175,205, 235 VDD Digital core power (2.5V).
19, 49, 77, 112, 134, 187, 219, 251
VSS Digital core ground.
14, 29, 42, 54, 64, 69, 80, 90, 101,
109, 120, 131, 143, 165, 180, 200, 208, 216, 224, 230, 237,
243, 249, 256
PVDD Digital I/O power (3.3V).
10, 24, 39, 46, 57, 65, 74, 85, 96, 105, 115, 126, 137, 147, 171, 189, 193, 202, 212, 222, 228, 233,
240, 246, 253
PVSS Ground.
60 MPAVDD Memory PLL analog power 2.5V.
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61 MPAVSS Memory PLL analog ground. 58 MPDVDD Memory PLL guard ring / digital power 2.5V. 59 MPDVSS Memory PLL guard ring / digital ground.
197 DPAVDD Display PLL analog power 2.5V. 196 DPAVSS Display PLL analog ground. 199 DPDVDD Display PLL digital power 2.5V. 198 DPDVSS Display PLL digital ground. 157 AVD33R Analog power (+3.3V) for R (V/Pr) channel. 154 AVD33G Analog power (+3.3V) for G (Y/Y) channel. 151 AVD33B Analog power (+3.3V) for B (U/Pb) channel. 158 AVS33R Analog ground for R (V/Pr) channel. 155 AVS33G Analog ground for G (Y/Y) channel. 152 AVS33B Analog ground for B (U/Pb) channel. 163 ADAVDD Analog power supply (+2.5V) for the analog display port. 164 ADAVSS Analog ground for the analog display port. 149 ADDVDD Digital power supply (+2.5V) for the analog display port. 148 ADDVSS Digital ground for the analog display port. 166 ADGVDD Guard ring power for the analog display port. 167 ADGVSS Guard ring ground for the analog display port.
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2.2.5TA2024 general: The TA2024 is a 10W/ch continuous average two-channel Class-T Digital Audio Power
Amplifier IC using Tripath’s proprietary Digital Power Processing™ technology. Class-T amplifiers offer both the audio fidelity of Class-AB and the power efficiency of Class-D amplifiers. Pin Function Descriptions
Pin(s) Name Function 2, 3 DCAP2, DCAP1 Charge pump switching pins 4, 9 V5D, V5A Digital 5VDC, Analog 5VDC
5, 8, 17 AGND1, AGND2, AGND3 Analog Ground 6 REF Internal reference voltage 7 OVERLOADB A logic low output indicates the input signal
has overloaded the amplifier 1014 OAOUT1, OAOUT2 Input stage output pins. 11, 15 INV1, INV2 Single-ended inputs
12 MUTE Mute control 16 BIASCAP Input stage bias voltage 18 SLEEP Sleep mode control 19 FAULT A logic high output indicates thermal
overload 20, 35 PGND2, PGND1 Power Grounds (high current)
22 DGND Digital Ground 24, 27; 31, 28 OUTP2 & OUTM2; OUTP1
& OUTM1 Bridged outputs
25, 26, 29, 30 VDD2, VDD2 VDD1, VDD1
Supply pins for high current H-bridges, nominally 12VDC.
13, 21, 23, 32, 34 NC Not connected 33 VDDA Analog 12VDC 36 CPUMP Charge pump output 1 5VGEN Regulated 5VDC source used to supply
power to the input section (pins 4 and 9).
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TA2024 Block Diagram
2.2.6DS90CF383A General
The DS90C383A/DS90CF383A transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 227 Mbytes/ sec. The DS90C383A transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. The DS90CF383A is fixed as a Falling edge strobe transmitter.
Pin Function Descriptions Pin(s) Name Function
1,9,17,26,34 44
VCC Power supply
5,13,21,29,53 33,35,36,43,49
GND Ground
2,3,50,51,52 54,55,56
DRE0DRE7 8bit red data input
4,6,7,11,12,14 8,10
DGE0DGE7 8bit green data input
15,19,20,22 23,24,8,16
DBE0DBE7 8bit blue data input
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27 HSYNC Horizontal Sync input 28 VSYNC Vertical Sync input 30 DE pixel display enable 31 TXCLK IN pixel display clock input 32 PWRDWN LVDS control
37,38,41,42 45,46,47,48
TXOUT+ TXOUT-
4 channels LVDS data signal output
39,40 TXCLKOUT+ TXCLKOUT-
1 channel LVDS clock signal output
DS90CF383 Block Diagram
2.2.7DVI Digital Receiver SiI161B General
The Sil161B receiver uses Panel Link Digital technology to support high-resolution displays up to UXGA. The Sil161B receiver supports up to true color panels (24 bit/pixel, 16.7M colors) in 1 or 2 pixels/clock mode. In addition, the receiver data output is time staggered to reduce ground bounce that affects EMI. All Panel Link products are designed on a scaleable CMOS architecture. This ensures support for future performance requirements while maintaining the same logical interface. With this scalable architecture, system designers can be assured that the interface will be fixed through a number of technology and performance generations.
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Pin Function Descriptions
Pin(s) Name Function 90 RX0+ TMDS Low Voltage Differential Signal input data pairs 91 RX0- TMDS Low Voltage Differential Signal input data pairs 85 RX1+ TMDS Low Voltage Differential Signal input data pairs 86 RX1- TMDS Low Voltage Differential Signal input data pairs 80 RX2+ TMDS Low Voltage Differential Signal input data pairs 81 RX2- TMDS Low Voltage Differential Signal input data pairs 93 RXC+ TMDS Low Voltage Differential Signal input clock pair. 94 RXC- TMDS Low Voltage Differential Signal input clock pair.
4956 QO0QO7 8bit odd-pixel Blue output 5966 QO8QO15 8bit even-pixel Green output
6975,77 QO16QO23 8bit odd-pixel Red output 1017 QE0QE7 8bit even -pixel Blue output 2027 QE8QE15 8bit even -pixel Green output 3037 QE16QE23 8bit even -pixel Red output
99 RESERVED Must be tied HIGH for normal operation. 100 OCK_INV ODCK Polarity. A LOW level selects normal ODCK
output. A HIGH level selects inverted ODCK output. 1 HS_DJTR This pin enables/disable the HSYNC dejitter function.
To enable the HSYNC function this pin should be tied high. To
2 PD Power Down (active LOW). A HIGH level indicates normal operation. A LOW level indicates power down mode.
3 ST Output Drive. A HIGH level selects HIGH output drive strength. A LOW level selects LOW output drive strength.
4 PIXS Pixel Select. A LOW level indicates one pixel (up to 24-bits) per clock mode using QE[23:0]. A HIGH level indicates two pixels (up to 48-bits) per clock mode using QE [23:0] for first pixel and QO[23:0] for second pixel.
7 STAG_OUT Staggered Output. A HIGH level selects normal simultaneous outputs on all odd and even data lines. A LOW level selects staggered output drive.
8 SCDT Sync Detect. A HIGH level is outputted when DE is actively toggling indicating that the link is alive. A LOW level is outputted when DE is inactive, indicating the link is down.
9 PDO Output Driver Power Down (active LOW). A HIGH level indicates normal operation. A LOW level puts all the output drivers only (except SCDT and CTL1) into a high impedance (tri-state) mode.
44 ODCK Output Data Clock. This output can be inverted using the OCK_INV pin.
46 DE Output Data Enable. 47 VSYNC Vertical Sync input control signal. 48 HSYNC Horizontal Sync input control signal.
18,29,43,57,78 OVCC Output VCC 19,28,45,58,76 OGND Output GND
6,38,67 CVCC Digital Core VCC, 5,39,68 GND Digital Core GND.
82,84,88,95 DAVCC Analog VCC
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99,83,87,89,92 AGND Analog VCC 97 PVCC PLL Analog VCC 98 PGND PLL Analog GND. 96 EXT-RES Impedance Matching Control. In the common case of
50Ω transmission line, an external 390Ω resistor must be connected between AVCC and this pin.
SiI161B Block Diagram
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CHAPTER 3 CHANGHONG PDP TELEVISON PT4206
entire signal flow analyse
3.1Each part signal Disposal Flow general 3.1.1Analog signal Disposal Flow 3.1.1 .1RF Disposal TDQ-6F7-FMW2 disposal the RF signal Pin Function Descriptions
Pin(s) Name Function 1 VT Analog tune voltagenot use 2 BTL +32Vpower 3 BM +5V power 4 ADD Ground 5 S0 Color system Switch control 6 S1 Color system Switch control 7 SCL I2C busclock 8 SDA I2C busdata 9 SIF Second sound IF signal output
10 VIDEO OUT video signal output 11 VIF Power supply 12 AUDIO OUT Sound LF signal output(not use)
First the antenna signal enters the Unify RF TUNER N901, enlarge the RF signal , choose the back track of frequent and mix frequent circuit ,and outputs the IF signal. The video signal from the 9 pin through the video check wave, differs to clap at the same time the Second sound IF signal output.
The frequency synthesizing and tuning needs two power supplies when work normally:+ 32 V tune voltage and + 5 V PLL power supply.
Moreover 5 and 6 pin of N901 switch the Color system , sending out from 44 and 50 pin of PW113.10 pin of N901 outputs video signal ,follows to Q905 ,through the video switch circuit switching with the AV/ S- VIDEO Input signal ,after them disposal in VPC3230.
3.1.1 .2 SOUND Disposal
the 9 pin of N901 outputs the second sound IF signal, enlarged by the Q910,following to Q602 and passing C611 to the 67 pin of MSP3410G to carry on SIF demodulation and the NICAM identify the decodingThe sound of PC, DVI, AV, YCbCr, and YPbPr are transited to MSP3440, and then input to the speakers after transits to TA2024 and to the speakers. . 3.1.1.3 digital signal disposal
In response to input signal of PW113 ,it must convert the input analog video signal, VGA analog signal and DVI signal into digital or video decode outputinclude three partsone, VGA or YpbPr (analog signal)is converted the signal into A/D by MST9885it is 24bit digital tricolor signalsecond various video signalsinclude TV signal are disposalled by VPC3230 then output the signal format ITU-R656 YUV signalThe third part decode DVI1.0 standard digital signal then output 24bitRGB signal
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3.1.1 .4 VGA/YpbPr analog signal disposal R, G, B signal From the VGA 1, 2, 3 pin through the static electricity protection circuit switches with video signal from YpbPr input port in PI5V330. After then RGB signal(PC source) pass C81C82C84 to 544843 pin of MST9885 and A/D converter in it
Moreover , Vertical , Horizontal sync from the VGA 13,14 pin also send to the synchronous pulse orthopedics circuit after static electricity protect processing. Horizontal sync after face lifting in 74LCX32 sends to the PI5V330 to the switch , and then feedback to the 30 pins of MST9885, By the effect of Horizontal sync , MST9885 creates PLL lock providing the MST9885 work clock. Vertical sync after buffer and enlarge in U71 outputs from the 6 pin of U71, and choices in U9(74 LVC126s).In VGA mode ,the signal to the 31 pin of MST9885, provides a Vertical sync to the MST9885.
The PDP display is the exterior equipments, and need an identify signal to examined by host when host communication. The 24LC21s of U8( EEPROM) saves the hardware concerning display parameter.( install etc. such as the factory, model number, resolution) MST9885 under the control of PW113 bus, converts the R,G,B input 8 bit digital R,G,B signal. 67 pin outputs pixel clock signal DATACKThe above signal sends to the PW113 and PW1235s at the same time, disposals the format judged by PW113.
3.1.1.4 Analog video signal disposal 9 pin of N901 outputs video signal passes VN901 and goes to 1 pin of TEA6425Dat the
same time 1 channel AV video signal sends to the 8 pin of TEA6425Dand other channel S-video signal (YC signal) sends to 65 pin of TEA6425D respectively. The three signals switches in the TEA6425D. VIDEO or Y signal outputs toVPC3230D from 17pinC signal outputs from 18pinat the same time 19 pin video outputs from19 pinVPC3230 The signal from TEA6425 after switch and A/Dsend to chroma decode circuit ,which can identify PAL/NTSC/SECAM signal automatically and to each decode after identify. Such as NTSC video after identify the system switches the TEA6425D channel sends to NTSC 3D comb filter from 14 pin of TEA6425D. After digital 3D comb filter in uPD64083 YC signal sends back to 7371pin of VPC3230Dto AD convertor and saturation control etc. The output digital YUV signalswitches with digital YUV signal after A/D which inputs from 456pinand outputs digital YUV signal sends to video disposalinclude zoomcontrast panorama modebrightnessgain control tc. After then the signal transforms to from 3140pin digital YUV signal4:2:2(ITU-R656 format )and sends to PW1235 to DEINTERLACE etc
3.1.1 .5 DVI digital signal disposal We use DVI-D interface DVI digital signal4channels DS signalfrom DVI jack each send to 9091858680
819394pin of SiI161B. By the control of 1003pin (input bus)after in SiI161B(VCRdata resumesync. Head test enlarge circuitdecode circuit and logic interface circuit)it outputs digital R G B signalwhich has two modeone mode when 4 pin of SiI161B is low it output 24bit even pixelwhen 4pin is high it output 48biteven and odd pixel datawe connect 4pin to groundso each signal from 101720273037pin outputs R,G,B even pixel dataswitch with 24bit VGA digital signal disposalled by MST9885and send to PW113 to transform
24
formatfor sure ,the choice is control by PW113 DVI interface 67pin is DDC data channel U724LC21Ais an E2ROMwhich stores
some DVI data parameter information it connect to DDC data channel by busat the moment of power on the status information is sent to host to identifyafter identifyaccording to E2ROM information outputs digital signal correctly
VGA signalvideo signalDVI signal after digital disposalsends to video format disposal ic PW113 to change the video format outputs the digital R,G,B signal which fits PDP display driver PW113 the input video signal after disposalled by PW113outputs 852×480 resolution digital
R,G,B signal which fits PDP panel spec and relevant syncclock signal and transform them into LVDS by DS90CF383send to PDP panel to control the panel display correctly
3.2 each information flow 3.2.1 TV
25
Tuner
demodulation
1
CVBS
TEA6425 video
switch
17
74
VPC3230 Identify color system
VPC3230
Not NTSC
When NTSCChange the video
switch by bus
16
uPD64083 comb filter 88
NTSC video
Sync
separate
83 84
73
71
Y
C
PW1235 I
channel
SV
Digital video and clock
PW113SCALER
DS90C383
D
LVDS
SDRAM
B
UE
RF
MSP3410GFmorNICAM demodulation
SRS(WOW) sound67SIF
TA2024 sound
amplifier
27 28
S0 S1
PW1235E
LVDSON
Main control signal1RST1#
High enable2STANBY control
Low is power ON3 MUTE high mute
4sound switchS0S1
5PW1235EcontrolHigh enable
BUFFER and polaritycontrolled by Q3
6LVDSON control
MUTE
SO S1D/K 1 0
BG 1 1I 0 1
M 0 0
26
3.2.2 AV
8
cvbs
TEA6425
video switch
17
74
VPC3230Identify color system
VPC3230 decode
Not NTSC
NTSC switch
by bus
16
uPD64083
comb filter
88
NTSC
Sync separate
83 84
73
71
Y
C
PW1235 I channel
SV
Digital video and clock
PW11SCALER
DS90C38
D
LVDS output
SDRA
B E
MSP3410Sound switch
SRS(WOW) sound disposal
53
TA2024 sound amplifier
27 28
PW1235
LVDSO
MUT
E
54
L
R
27
3.2.3 S-VIDEO
6
Y
TEA6425 video
switch
17
Y
VPC3230
decode
PW1235 I
channel
SV
Digital video and clock
PW11SCALER
DS90C38
D
LVDS output
SDRA
B
UE
MSP3410
Sound switch SRS(WOW)
sound disposal
53
TA2024 sound amplifier
27 28
PW1235
LVDSO
MUT
54
L
R
5
C
74
18
72
C
28
3.2.4 YcbCr
DS90C3
LVDS
LVDS
ON
8
CVBS
TEA6425 video
switch
17
74
VPC3230
VPC3230
decode
Not NTSC
When NTSC,switch video
signal
16
uPD64083 comb
fliter
88
NTSC video
Sync.
separate
83 84
73
71
Y
C
PW1235 I
channel
SV
Digital video and clock
PW11
SCALER disposal
DS90C38
D
LVDS output
SDRA
B E
MSP3410Sound switch SRS(WOW)
sound disposal
53
TA2024 sound
amplifier
27 28
PW1235
LVDSO
MUT
E
54
L
R
29
3.2.5 YpbPr
PI330 switch
AD9883
G
PW113Format identify
PW113 SCALER
DS90C383
D
LVDS output
B
UE
Pr
MSP3410 Sound switch SRS(WOW) sound disposal
47
TA2024 sound amplifier
27 28
Y Pb
PW1235
LVDSO
MUT
VGASE
5 11 2
1
4 7 9
54 48 43
R G B
48
L R
30
3.2.6 VGA
PI330 switch
30
HS
MST988
G
PW11Foemat identify
PW113 SCALER
640X480800X600@60Hz signal
PW1235 P
channel
G
D
G
Signal after vertical sync
DS90C38
D
LVDS output
SDRA
B
UE
B
MSP3410
Sound switch
SRS(WOW) sound disposal
50
TA2024 sound
amplifier
27 28
R G
PW1235
LVDSO
Main control signal 1RST1#
High enable2STANBY control Low is power ON 3 MUTE
High mute4VGASEL control High enable 5PW1235E control
High enable BUFFER and polarity are
controlled by Q3
6LVDSON control
MUT
VGASE
3 6 10
1
13
HS
12 4 7 9
54 48 43
R G B
31U9VS
BUFER
PW1235
Not standard modeadjust
AD9883 switch the channel
51
L R
31
3.2.7 DVI
3.3system control process
After connect the AC power input (we use 3 pins power jackthe GND pin must ground well).first of all ,standby power workssignal mainboard takes 5V-ST power supply the powers of PW113 begin to workLED turns red. Resetting after V18V33 power is normalPW113 initializes the systemsends STANDBYLsignalwhich controls main power begins to workother power VT9VT5AVCCPVDDAVDDOVCCCVCCPVCCDAVCCAVDDAVCCDVDAPVDD also work normally.MST9885VPC3230SiI161BDS90CF383 take proper power supply. Moreover LED signal control LED to turn yellow and glitterit is said that it controls normally At last LVDSON signal from 43pin of PW113is highit let DS90CF383 begin to workAfter this it is in normal work stateinput source is last time source before power off
SiL161
G
PW113Format identify
PW113 SCALER
vertical sync 60HZ signal
PW1235 P channel G
D
G
Signal after vertical sync change
DS90C383
D
LVDS output
SDRA
B
UE
MSP3410
Sound switch SRS(WOW) sound
50
TA2024 sound
amplifier
27 28
PW1235E
LVDSO
MUT
Digital RGB or YPbPr
BUFFER
PW1235E
Not standard modeSwitch the channel
51
L R
32
3.3.1when choice VGA mode by remote device PW113 controls MST9885 by I2C busenable SiI161B and VPC3230let them work in low consume modewhich can save power and reduce interfereAt the moment VGASEL signal from PW113 output parks VGA input channel in PI5V330. If VGA signal inputs, MST9885 outputs Horizontal and Vertical Sync signal and data signaland send to PW113which outputs format commutation data . After DS90CF383(DS transmitter)it transforms to the signal fitting the PDP panel demand because SiI161BDS90CF383 both in normal work statewhen DVI signal inputs, display videoif no VGA signalMST9885 can not output digital Horizontal and Vertical Sync signal after examined by PW113,displays pc icon on the left and top of PDP panel other part display black. If no input after 60 sec, it hints to enter “save power mode” At the moment , MST9885 in normal work stateexamines VGA signal ceaselesslyso it can arouse automatically in VGA mode. It is said that when VGA signal inputs, it can work normally from standby state
3.3.2when in TVAVYCbCr mode by remote devicePW113 controls VPC3230 by I2Cbusotherwise PW113 controls MST9885 on the fly output in high impedance stateby I2Cbus.Because tuner N901VPC3230 DS90CF383 all in normal work statewhen video signal inputsPDP panel display normallyif no video signal inputunder the control of PW113PDP panel displays blue backgroundif no signal 15 minspower off automatically and into standby state. It can not arouse automatically
3.3.3When in DVI(digital RGB) mode by remote devicePW113 controls SiI161Band enables VPC3230and let it working in low consume modeotherwise PW113 controls MST9885 on the flyoutput in high impedance stateby I2C busbecause SiI161BDS90CF383 both in normal work statewhen DVI signal inputs, display videoif no DVI signalSiI161B do not output digital Horizontal and Vertical Sync signal after examined by PW113,displays DVI icon on the left and top of PDP panel other part display black. If no input after 60 sec, it hints to enter “save power mode”work stateAt the moment ,SiI161B in normal work state examines DVI signal ceaselesslyso it can arouse automatically in DVI mode. It is said that when DVI signal inputs, it can work normally from standby state
3.4power supply system
3.4.1main power supply D6Vsteady voltage to 5V supply for VPV3230AD9883 analog power5V-STstandby
powerto PW113AM29LV800BTROM24LC32MAX202EVDD(3.3V)VPC3230MST9885DS90CF383 power+32VRF tuner tuning powerA6Vsteady voltage to Av board 5V etc. A12Vsteady voltage to AV board 8V etc.12VAMPsound amplifier TA2024 power 3.4.2 main power form and power branch 3.4.2.15V-STpower branch
33
XP8012 pi n 5V-ST
N803LM1117-3. 3
N804LM1117-1. 8
XP10111 pi n
XPK311pi n
K boardconnect
U20MAX202E
U16 PW11316Ў ў37Ў ў65Ў ў84Ў ў137Ў ў185pi nVLL
NK605remot e head
VDK1LED
U16 PW113165Ў ў167pi nVPP
U17 29LV800B37pi n
U19 24LC328pi n
U16 PW11329Ў ў52Ў ў72Ў ў86Ў ў104Ў ў123Ў ў140Ў ў
171Ў ў208pi n
VUU
3.4.2.2D6V power branch
34
XP80111 pi n D6V N802
TA4805F
U5PI 5V330 16 pi n
U27LM1117-3. 3
U26LM1117-3. 3
U1VPC3230
U6 AD9883A26Ў ў27Ў ў39Ў ў42Ў ў45Ў ў46Ў ў
51Ў ў52Ў ў59Ў ў62 pi nVFF
U6 AD9883A34Ў ў35 pi nVEE
VCC
U28LM1086CSX-2. 5
U3 PW12355Ў ў34Ў ў93Ў ў123Ў ў140Ў ў
175Ў ў205Ў ў235 pi n
VXX U3 PW1235197Ў ў199 pi nVYY
U3 PW123558Ў ў60 pi nVZZ
U3 PW1235149Ў ў163Ў ў166
pi nЈ «2. 5
35
3.4.2.3VDD(3.3V) power branch
XP8018Ў ў9pi n
VDD
U11 Si L161B6Ў ў18Ў ў29Ў ў38Ў ў43Ў ў57Ў ў67Ў ў78Ў ў
82Ў ў84Ў ў88Ў ў95Ў ў97pi n
U4 I S42S16400(A)-7T1Ў ў3Ў ў9Ў ў14Ў ў27Ў ў43Ў ў49pi n
U3 PW123514Ў ў29Ў ў42Ў ў54Ў ў64Ў ў69Ў ў80Ў ў90Ў ў101Ў ў109Ў ў120Ў ў131Ў ў143Ў ў165Ў ў
180Ў ў200Ў ў208Ў ў216Ў ў224Ў ў230Ў ў237Ў ў243Ў ў249Ў ў256pi n
U3 PW123551Ў ў54Ў ў57pi n
U22 DC90C3831Ў ў9Ў ў26pi n
U10/ U12/ U14/ U15 74LVC162447Ў ў18Ў ў31Ў ў42 pi n
U22 DC90CF38334pi n
U22 DC90CF38344pi n
U6 AD988311Ў ў22Ў ў23Ў ў69Ў ў
78Ў ў79pi n
U71 74LV3214pi n
U1 VPC323010Ў ў29Ў ў36Ў ў45Ў ў
52pi n
t o reduce i nt er f erenceЈ ¬U11 power i s di vi ded i nt o
VDDЎ ўVI IЎ ўVJJ by LCf i l t erЎ Ј
97 pi n i s VI I powerЈ ¬82Ў ў84Ў ў88Ў ў95 pi n are VJJ
power
VNN
VOO
VNNЎ ўVOO i s i n order t oreduce t he i nt er f erenceЈ ¬f rom VDD af t er LC f i l t er
36
3.4.2.4A6Vpower branch
XP8051pi n
N806TA4805F
N805TA4805F
N650TA4805F
N601 MSP3410G65Ў ў66pi nVCCA6V
N601 MSP3410G11Ў ў12Ў ў13pi n
N901 TDQ-6F73Ў ў11pi n5VTUNER
TV vi deoЎ ўSI Ff ol l ow ampl i f er
ci rcui t
N702LM1117-2. 5
N703LM1117-3. 3
5V2
N701 i nput vi deoand out put YC
f i l t er ampl i f erci rcui t
5V-3D
U701 uPD6408353Ў ў81Ў ў92Ў ў
93pi nA2. 5V
N701 uPD6408331Ў ў32Ў ў45Ў ў46Ў ў64Ў ў
100pi n
D2. 5V
N701 uPD6408338pi nD3. 3V
N701 smal lsi gnal f i l t er
ampl i f er ci rcui t
37
3.4.2.5A12Vpower branch
XP8053pi n
N651TA78M08
PC/ YPbPr soundampl i f er+8V
N902 TEA6425D20pi n
N601 MSP3410G39pi n
AVOUT soundampl i f er
38
Part:Typical Defectives and Repair of PT4206
onered led do not light
red led do not light
yes no
Y N yes no
Check jack XP901 2 pin5V power supply
Check mainboard jack XP8012 pin 5V power
Check resistance RK2LBD VDK1
Check K boardiack XK01 11 pin5V power
Check power filterand power jackAC 220V input
1Check XP801 2 pin short circuitto ground whether or not 2Check mainboard L801 3Check PW113 reset circuitclockcircuit
Check circuitconnect
39
twoThe red led lightsbut doesn’t turn to yellow after power on and black display
power onЈ ¬checkXP801 4 pi n st andbyi s l owЁ Q0. 5Vvol t age
yes
ОЮ check N803Ў ўN804out put vol t age
checkXP801 D6VЎ ўVDDno
1Ў ўcheckconnect or2Ў ўcheck PDPpower
yes
1Ў ўcheck PW113power i mpedance2Ў ўcheckN803Ў ўN804
No
check X3 14. 318Mcryst al
Yes
No change Y2cryst al
check PW113RESET pi nvol t age
Yes
checkreset ci rcui tNo
check AM29LV800BT t oPW113 addressЎ ўdat aЎ ўcont rol
Yes
changeAM29LV800BT orPW113 and wi rebet ween t hem
I 2Cbus
1Ў ўcheck VPC3230Ў ўPW1235power ci rcui t2Ў ўcheck VPC3230Ў ўPW1235reset vol t age3Ў ўcheck VPC3230Ў ўPW1235per i pheral l y ci rcui t
normal
abnormal i t ycheck bus
ci rcui t and PCBwi re
40
threeThe red led lightbut turn to other color after power on and black display
change swi t chf i nd i f t here i si con on t hescreen
f ol l ow nopi ct ure t o checkYes
check mai nboardJ15Ј »check t hel i ne
No
Yes mend
check LVDSsi gnal
No1Ў ўLVDS ON i shi gn or not2Ў ўcheck PW113syncЎ ўpi xelcl ockЎ ўRGB dat asi nal
No
checkDS90c383power suppl y
Yes
check PW113out put por t Ј »change PW113
No
check powersuppl yNo
check DS90C383Ј ¬change
Yes
check PW113syncЎ ўpi xel
cl ockЎ ўRGB dat asi nal
Yes
check cryst alf requent Ј »checkPW113Ј »change
Yes
41
fourno picture check i f t herei s a i con t odi spl ay when
source swi t ches
no pi ct ure onl yVGA
check AD9883A30Ў ў31 pi n sync
Yes
change AD9883A
abnormal i t y
check sync f acel i f t i ng ci rcui t
and I / O syncwave
No
check VGA j ack
i nput abnormal i t y
check sync f acel i f t i ng ci rcui tand per i pheral l yci rcui t
out put abnormal i t y
no pi ct ure onl yDVI
check Si I 161B/ 169 Ј Ё44Ј ©Ј Ё48Ј ©Ј Ё47Ј ©Ј Ё42Ј ©pi n GCLKЎ ўGHSЎ ў
GVSЎ ўGFBK
checkSi I 161B/ 169cont rol si gnal
al l abnormal i t y
1Ў ўcheck si gnal source2Ў ўDVI j ack
3Ў ўchange Si i 161B
part abnormal i t y
ot her par t i sf ol l owi ng
CHECK PW113 G-Port Ј ¬Ј Ё31Ј ©-Ј Ё35Ј © pi nЈ ¬
changePW113No
42
i f t here i s onest at e t o di spl aywhen swi t ch t he
source
TVЎ ўAVЎ ўS-VDEOЎ ўYCbCr al l no
pi ct ure
onl y TVЎ ўAVЎ ўS-VI DE Ono
pi ct ure
onl y TVЎ ўAV i sNTSC no pi ct ure
onl y TV nopi ct ure
check PW1235power Ў ўcl ock
check VPC3230out put
check VPC3230power Ў ўcl ockЦУ
per i pheryci rcui t Ј »change
VPC3230
check and changePW1235Yes
No
repai r abnormal i t y check AV boardconnect or
check TEA6425DI / O
j oi nt wel l
check TEA6425powerЎ ўbusЈ »
change TEA6425
i nput wel l , but out put bad
check TEA6425D14pi n vi deo out out
check uPD64083resetЎ ўcl ockЎ ў
powerЈ »changeuPD64083
check uPD64083I / O f i l t er and
ampl i f er ci rcui t
Yes
check TEA6425D1pi n vi deo si gnal
i nput
checkand
changeTEA642
5D
No Yes
check TDQ-6F7powerЎ ўbus and
vi deo f ol l owwi ngout out ci rcui t
check and changeTDQ-6F7
43
Five picture dissimilation
pi ct uredi ssi mi l at i on
mosai c phenomena
check PW113power
check l i nervol t age ci rcui tNo
change PW113
change memori zerU19 24LC32AЈ ¬check PW113 andU19
No
col ourdi ssi mi l at i on
source swi t ch i fone mode i s wel l
or not
onl y VGA col ourdi ssi mi l at i on
onl y DVI col ourdi ssi mi l at i on
al l col ourdi ssi mi l at i on
check AD9883Aand 74LV16244
RЎ ўGЎ ўB di gi t alsi gnal
check Si l 161BУ лand 74LV16244
RЎ ўGЎ ўB di gi t alsi gnal
change U824LC21AЈ ¬
checkЈ Ё5Ј ©Ј Ё6Ј ©pi n
normal
changeu724LC21AЈ ¬checkЈ Ё5Ј ©Ј Ё6Ј ©
normal
check mai nboardpanel j ack
normal DS90C383A
normal
check PW113out put vi deo
si ganl
normal
f ol l ownext
pi ct ure
al l panel green
checkDS90C383A(37)- (42)(45)- (4
8)
changeDS90C383AЈ ¬
repai r out putconnect or
44
pi ct uredi ssi mi l at i on
l ack col ourЈ єnoRЈ ¬no G, no B
l ack f rontone anal og
si gnal
AV/ TV st at eVGA st at e
check C81Ў ўC82Ў ўC84
checkPI 5V330
check L901Ў ўL902Ў ўL905Ў ў
R904Ў ўR909Ў ўR910
change AD9883A
check PW1235out put dat a
check VPC3230out put
check VPC3230i nput si gnal
check and changePW1235No
check and changeVPC3230
pl ane crossbandi nt er f erence
VGA modecommendat ory
st at e
change U8Ј ¬checkЈ Ё5Ј ©(6)
pi n
DVI modecommendat ory
st at e
onl y VGAЎ ўDVInot commendat ory
st at e
change U7Ј ¬checkЈ Ё5Ј ©(6)
pi n
checkAD9883A andper i pheral l y
devi ce
check Si I 161Band per i pheral l y
devi ce
45
sixno sound or small sound
no sound orsmal l sound
check XP302Ў ўXP303Ј »sound box
connect or
Yes change sound boxcheck XP302Ў ў
XP303out put si gnal
check TA2024powerЎ ўmut e
check TA2024i nput si gnal normal
check MSP3410Gout put si gnal
check MSP3410G out putcoupl i ng ci rcui t C629Ў ў
C630Ў ўFB5Ў ўFB6Ў ўC522Ў ўC543Yes
check and changeTA2024normal
check MSP3410Gi nput si gnal
check 67 pi nSI SF i nputTV
check soundi nput
ot her source
check MSP3410GpowerЎ ўcl ockЎ ў
resetЎ ўbusYes
Yes
checkTDQ-6F7out put SI Fsi gnal
check SI F f i l t erampl i f erci rcui t
normal
check and changeTDQ-6F7abnormal i t y
check and changeMSP3410G
normal
check si gnalsourceЎ ўsoundj ackЎ ўi nput
coupl i ng ci rcui t
no i nput