SemiWiki.com - Introduction to FinFET Technology Part II
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Home Introduction to FinFET technology Part II Introductio n to FinFET technology Part II The previous post in this series provided an overview of FinFET devices. This article will briefly cover FinFET fabrication. The major process steps in fabricating silicon fins are shown in Figures 1 through . The step that defines the fin thic!ness uses "idewall Image Transfer #"IT$. %ow&pressure chemical vapor #isotropic$ deposition provides a uni'ue dielectric profile on the sidewalls of the sacrificial patterned line. ( subse'uent #anisotropic$ etch of the dielectric retains the sidewall material #Figure 1$. )eactive ion etching of the sacrificial line and the e*posed substrate results in silicon pedestals #Figure +$. ,eposition of a dielectric to completely fill the volume between pedestals is followed by a controlled etch&bac! to e*pose the fins #Figure $. Figure 1. -ross§ion of sidewalls on sacrificial lines after -, etch. Figure +. -ross§ion of silicon pedestals after )IE etch/ using "idewall Image Transfer. Figure . -ross§ion of silicon fins after o*ide deposition and etch&bac!/ and gate deposition. %ow&pressure dielectric depositio n to create sidewalls on a polysilicon line is a well&!nown techni'ue 0 it is commonly used to separate #deep$ sourcedrain implant areas from the planar FET transistor channel. FinFET fabrication e*tends this techni'ue to pattern definition for silicon fin etching. There is no photolithography step associated with "IT/ just the patterning of the sacrificial lines. (s a result/ the fin thic!ness can be smaller than the photolithograp hic minimum dimensions. The fin thic!ness is defined by well&controlled dielectric deposition and etching steps rather than photoresist patterning/ reducing the manufacturing variation. However/ there is variation in fin height/ resulting from #local$ variations in the etch&bac! rate of dielectric removal. #For FinFET2s on an "3I substrate/ the fin height is defined by the silicon layer thic!ness/ with a 2natural2 silicon etch&stop at t he insulator interface in contrast to the timed&etch fin h eight for bul! substrate pedestals.$ There are several characteristics to note about "IT technology . 4ominally/ fins come in pairs from the two sidewalls of the sacrificial line. (dding fins in parallel to increase drive current typically involves adding a pair of fins5 delta6w 7 #+8#+8h6fin 9 t6fin$$. To :cut; fins/ a mas!ed silicon etching step is re'uired. There are two considerations for cutting fins. The first involves brea!ing long fins into individual pairs. The other is to create an isolated fin/ by removing its "IT&generated neighbor. -ritical circuits that re'uire high density andor different device si<ing ratios may justify the need for isolated fin patterning 0 e.g./ ")(= bit cells. -ompared to cutting/ isolated fin patterning may involve different design rules and separate #critical$ lithography steps/ and thus additional costs. (dditional proce ss steps are re'uire d to introduce imp urities of the appro priate type below the fin to provide a punchthrough stop #PT"$/ ensuring there is no direct current path between drain and source that is not electrostatically >ou are currentl y viewing "emi?i!i as a guest which g ives you limited access to the site. To view blog comments and e*perience other "emi?i!i features you must be a registered member. )egistration is fast/ simple/ and absolutely free so please/ join our community today@ Remember Me? Aser 4ame Password %og in Register Help Forum Wikis Jobs About EDA Design IP Services Semico n du ctor FP GA Advanced Search by Published on BC&+D&+B1+ B5BB (= + -omments -hipuy Home Se mi Wi ki .c om - Intr od uc ti on to Fi nFET te chnology Pa rt II ht tp:/ /www.semiwiki. com/ foru m/ cont en t/ 1228 -i nt ro duct ion- fi nf et -t ec h. .. 1 of 3 2/3/2015 9:49 PM
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Home Introduction to FinFET technology Part II
Introduction to FinFET technology Part II
The previous post in this series provided an overview of FinFET devices. This
article will briefly cover FinFET fabrication.
The major process steps in fabricating silicon fins are shown in Figures 1 through
. The step that defines the fin thic!ness uses "idewall Image Transfer #"IT$.
%ow&pressure chemical vapor #isotropic$ deposition provides a uni'ue dielectric
profile on the sidewalls of the sacrificial patterned line. ( subse'uent #anisotropic$
etch of the dielectric retains the sidewall material #Figure 1$. )eactive ion etching
of the sacrificial line and the e*posed substrate results in silicon pedestals #Figure
+$. ,eposition of a dielectric to completely fill the volume between pedestals is
followed by a controlled etch&bac! to e*pose the fins #Figure $.
Figure 1. -ross§ion of sidewalls on sacrificial lines after -, etch.
Figure +. -ross§ion of silicon pedestals after )IE etch/ using "idewall Image
Transfer.
Figure . -ross§ion of silicon fins after o*ide deposition and etch&bac!/ and
gate deposition.
%ow&pressure dielectric deposition to create sidewalls on a polysilicon line is a
well&!nown techni'ue 0 it is commonly used to separate #deep$ sourcedrain
implant areas from the planar FET transistor channel. FinFET fabrication e*tends
this techni'ue to pattern definition for silicon fin etching.
There is no photolithography step associated with "IT/ just the patterning of the
sacrificial lines. (s a result/ the fin thic!ness can be smaller than the
photolithographic minimum dimensions. The fin thic!ness is defined by
well&controlled dielectric deposition and etching steps rather than photoresist
patterning/ reducing the manufacturing variation. However/ there is variation in
fin height/ resulting from #local$ variations in the etch&bac! rate of dielectric
removal. #For FinFET2s on an "3I substrate/ the fin height is defined by the silicon
layer thic!ness/ with a 2natural2 silicon etch&stop at the insulator interface in
contrast to the timed&etch fin height for bul! substrate pedestals.$
There are several characteristics to note about "IT technology. 4ominally/ fins
come in pairs from the two sidewalls of the sacrificial line. (dding fins in parallel
to increase drive current typically involves adding a pair of fins5 delta6w 7
#+8#+8h6fin 9 t6fin$$.
To :cut; fins/ a mas!ed silicon etching step is re'uired. There are two
considerations for cutting fins. The first involves brea!ing long fins into individual
pairs. The other is to create an isolated fin/ by removing its "IT&generated
neighbor. -ritical circuits that re'uire high density andor different device si<ingratios may justify the need for isolated fin patterning 0 e.g./ ")(= bit cells.
-ompared to cutting/ isolated fin patterning may involve different design rules and
separate #critical$ lithography steps/ and thus additional costs.
(dditional process steps are re'uired to introduce impurities of the appropriate
type below the fin to provide a punchthrough stop #PT"$/ ensuring there is no
direct current path between drain and source that is not electrostatically
>ou are currently viewing "emi?i!i as a guest which gives you limited access to the site. To view blog comments and e*perienceother "emi?i!i features you must be a registered member. )egistration is fast/ simple/ and absolutely free so please/ join our
community today@
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